SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
MCU_OBSCLK1_MUX0 is provided as a low jitter output for WKUP_HFOSC0_CLK. In this configuration, CTRLMMR_WKUP_MCU_OBSCLK_CTRL[3:0] should be configured as 0001b (1, selecting a logical low signal) and CTRLMMR_WKUP_MCU_OBSCLK_CTRL[24] should be configured as 1.