SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The A72 cluster and each A72 CPU reside in a separate power domain, as follows:
There is a dedicated Local Power Sleep Controller (LPSC) for the A72 cluster and for each A72 core, as well. The LPSC assignment is as follows:
For more details on these LPSCs, including power-up/down sequences, see Power.