SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This section identifies the requirements for initializing the surrounding modules when the UART module is to be used for the first time after a device reset. This initialization of surrounding modules is based on the integration of the UART.
For more information, see Table 12-762.
Surrounding Modules | Comments |
---|---|
LPSC0 | Module reset must be enabled. For more information about the module configuration, see Reset. |
LPSC3 | Module reset must be enabled. For more information about the module configuration, see Reset. |
LPSC54 | Module reset must be enabled. For more information about the module configuration, see Reset. |
LPSC55 | Module reset must be enabled. For more information about the module configuration, see Reset. |
LPSC56 | Module reset must be enabled. For more information about the module configuration, see Reset. |
PLLCTRL0 | PLLCTRL0 configuration must be done to enable the clocks to the UART modules, see Clocking. |
WKUP_PLLCTRL0 | WKUP_PLLCTRL0 configuration must be done to enable the clocks to the UART modules, see Clocking. |
WKUP_HFOSC0 | WKUP_HFOSC0 configuration must be done to enable the clocks to the UART modules, see Clocking. |
PLL1 | PLL1 configuration must be done to enable the clocks to the UART modules, see Clocking. |
MCU_PLL1 | MCU_PLL1 configuration must be done to enable the clocks to the UART modules, see Clocking. |
COMPUTE_CLUSTER0 | Device INTCs must be configured to enable the interrupt request generation. For information about enabling COMPUTE_CLUSTER0 interrupts, see Interrupts. |
MCU_R5FSS0_CORE0/1 | Device INTCs must be configured to enable the interrupt request generation. For information about enabling MCU_R5FSS0_CORE0/1 interrupts, see Interrupts. |
WKUP_DMSC0 | Device INTCs must be configured to enable the interrupt request generation. For information about enabling WKUP_DMSC0 interrupts, see Interrupts. |
MAIN2MCU_LVL_INTROUTER0 | Device INTCs must be configured to enable the interrupt request generation. For information about enabling MAIN2MCU_LVL_INTROUTER0 interrupts, see Interrupts. |
R5FSS0_CORE0/1 | Device INTCs must be configured to enable the interrupt request generation. For information about enabling R5FSS0_CORE0/1 interrupts, see Interrupts. |
MCU_PDMA0 | MCU_PDMA0 controllers configuration must be done to enable the module MCU_PDMA0 channel request, see Data Movement Architecture (DMA). |
PDMA_USART_G0 | PDMA_USART_G0 controllers configuration must be done to enable the module PDMA_USART_G0 channel request, see Data Movement Architecture (DMA). |
PDMA_USART_G1 | PDMA_USART_G1 controllers configuration must be done to enable the module PDMA_USART_G1 channel request, see Data Movement Architecture (DMA). |
PDMA_USART_G2 | PDMA_USART_G2 controllers configuration must be done to enable the module PDMA_USART_G2 channel request, see Data Movement Architecture (DMA). |
Interconnects | For information about the WKUP_CBASS0, MCU_CBASS0, and CBASS0 interconnects configuration, see System Interconnect. |