SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-3544 lists the memory-mapped registers for the PCIE_CPTS. All register offset addresses not listed in Table 12-3544 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6000h |
PCIE_CPTS_IDVER_REG is shown in Figure 12-1797 and described in Table 12-3546.
Return to Summary Table.
Identification and Version Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TX_IDENT | |||||||||||||||
R-4E8Ah | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL_VER | MAJOR_VER | MINOR_VER | |||||||||||||
R-0h | R-1h | R-Bh | |||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | TX_IDENT | R | 4E8Ah | Identification value |
15-11 | RTL_VER | R | 0h | RTL version value |
10-8 | MAJOR_VER | R | 1h | Major version value |
7-0 | MINOR_VER | R | Bh | Minor version value |
PCIE_CPTS_CONTROL_REG is shown in Figure 12-1798 and described in Table 12-3548.
Return to Summary Table.
Time Sync Control Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TS_SYNC_SEL | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TS_GENF_CLR_EN | TS_RX_NO_EVENT | |||||
R/W-X | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
HW8_TS_PUSH_EN | HW7_TS_PUSH_EN | HW6_TS_PUSH_EN | HW5_TS_PUSH_EN | HW4_TS_PUSH_EN | HW3_TS_PUSH_EN | HW2_TS_PUSH_EN | HW1_TS_PUSH_EN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_PPM_DIR | TS_COMP_TOG | MODE | SEQUENCE_EN | TSTAMP_EN | TS_COMP_POLARITY | INT_TEST | CPTS_EN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-1h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | TS_SYNC_SEL | R/W | 0h | TS_SYNC output timestamp counter bit select |
27-18 | RESERVED | R/W | X | |
17 | TS_GENF_CLR_EN | R/W | 0h | Enable for GENF clear when length is zero |
16 | TS_RX_NO_EVENT | R/W | 0h | Receive Produces no Events |
15 | HW8_TS_PUSH_EN | R/W | 0h | Hardware push 8 enable |
14 | HW7_TS_PUSH_EN | R/W | 0h | Hardware push 7 enable |
13 | HW6_TS_PUSH_EN | R/W | 0h | Hardware push 6 enable |
12 | HW5_TS_PUSH_EN | R/W | 0h | Hardware push 5 enable |
11 | HW4_TS_PUSH_EN | R/W | 0h | Hardware push 4 enable |
10 | HW3_TS_PUSH_EN | R/W | 0h | Hardware push 3 enable |
9 | HW2_TS_PUSH_EN | R/W | 0h | Hardware push 2 enable |
8 | HW1_TS_PUSH_EN | R/W | 0h | Hardware push 1 enable |
7 | TS_PPM_DIR | R/W | 0h | Timestamp PPM Direction |
6 | TS_COMP_TOG | R/W | 0h | Timestamp Compare Toggle mode: |
5 | MODE | R/W | 0h | Timestamp mode |
4 | SEQUENCE_EN | R/W | 0h | Sequence Enable |
3 | TSTAMP_EN | R/W | 0h | Host Receive Timestamp Enable |
2 | TS_COMP_POLARITY | R/W | 1h | TS_COMP polarity |
1 | INT_TEST | R/W | 0h | Interrupt test |
0 | CPTS_EN | R/W | 0h | Time sync enable |
PCIE_CPTS_RFTCLK_SEL_REG is shown in Figure 12-1799 and described in Table 12-3550.
Return to Summary Table.
RFTCLK Select Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RFTCLK_SEL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4-0 | RFTCLK_SEL | R/W | 0h | Reference clock select |
PCIE_CPTS_TS_PUSH_REG is shown in Figure 12-1800 and described in Table 12-3552.
Return to Summary Table.
Time Stamp Event Push Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 600Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PUSH | ||||||
W-X | W-0h | ||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | X | |
0 | TS_PUSH | W | 0h | Time stamp event push |
PCIE_CPTS_TS_LOAD_VAL_REG is shown in Figure 12-1801 and described in Table 12-3554.
Return to Summary Table.
Time Stamp Load Low Value Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_LOAD_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_LOAD_VAL | R/W | 0h | Time stamp load low value |
PCIE_CPTS_TS_LOAD_EN_REG is shown in Figure 12-1802 and described in Table 12-3556.
Return to Summary Table.
Time Stamp Load Enable Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_LOAD_EN | ||||||
W-X | W-0h | ||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | X | |
0 | TS_LOAD_EN | W | 0h | Time stamp load enable |
PCIE_CPTS_TS_COMP_VAL_REG is shown in Figure 12-1803 and described in Table 12-3558.
Return to Summary Table.
Time Stamp Comparison Low Value Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_COMP_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_COMP_VAL | R/W | 0h | Time stamp comparison low value |
PCIE_CPTS_TS_COMP_LEN_REG is shown in Figure 12-1804 and described in Table 12-3560.
Return to Summary Table.
Time Stamp Comparison Length Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 601Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_COMP_LENGTH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_COMP_LENGTH | R/W | 0h | Time stamp comparison length |
PCIE_CPTS_INTSTAT_RAW_REG is shown in Figure 12-1805 and described in Table 12-3562.
Return to Summary Table.
Interrupt Status Register Raw
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PEND_RAW | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | TS_PEND_RAW | R/W | 0h | TS_PEND_RAW int read (before enable) |
PCIE_CPTS_INTSTAT_MASKED_REG is shown in Figure 12-1806 and described in Table 12-3564.
Return to Summary Table.
Interrupt Status Register Masked
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PEND | ||||||
R-X | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | X | |
0 | TS_PEND | R | 0h | TS_PEND masked interrupt read (after enable) |
PCIE_CPTS_INT_ENABLE_REG is shown in Figure 12-1807 and described in Table 12-3566.
Return to Summary Table.
Interrupt Enable Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PEND_EN | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | TS_PEND_EN | R/W | 0h | TS_PEND masked interrupt enable |
PCIE_CPTS_TS_COMP_NUDGE_REG is shown in Figure 12-1808 and described in Table 12-3568.
Return to Summary Table.
Time Stamp Comparison Nudge Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 602Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUDGE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | NUDGE | R/W | 0h | This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount |
PCIE_CPTS_EVENT_POP_REG is shown in Figure 12-1809 and described in Table 12-3570.
Return to Summary Table.
Event Pop Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVENT_POP | ||||||
W-X | W-0h | ||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | W | X | |
0 | EVENT_POP | W | 0h | Event pop |
PCIE_CPTS_EVENT_0_REG is shown in Figure 12-1810 and described in Table 12-3572.
Return to Summary Table.
Event 0 Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIME_STAMP | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TIME_STAMP | R | 0h | Time Stamp |
PCIE_CPTS_EVENT_1_REG is shown in Figure 12-1811 and described in Table 12-3574.
Return to Summary Table.
Event 1 Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PREMPT_QUEUE | PORT_NUMBER | |||||
R-X | R-0h | R-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EVENT_TYPE | MESSAGE_TYPE | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SEQUENCE_ID | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SEQUENCE_ID | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R | X | |
29 | PREMPT_QUEUE | R | 0h | Prempt QUEUE |
28-24 | PORT_NUMBER | R | 0h | Port number |
23-20 | EVENT_TYPE | R | 0h | Event type |
19-16 | MESSAGE_TYPE | R | 0h | Message type |
15-0 | SEQUENCE_ID | R | 0h | Sequence ID |
PCIE_CPTS_EVENT_2_REG is shown in Figure 12-1812 and described in Table 12-3576.
Return to Summary Table.
Event 2 Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 603Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DOMAIN | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | X | |
7-0 | DOMAIN | R | 0h | Domain |
PCIE_CPTS_EVENT_3_REG is shown in Figure 12-1813 and described in Table 12-3578.
Return to Summary Table.
Event 3 Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TIME_STAMP | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TIME_STAMP | R | 0h | Time Stamp |
PCIE_CPTS_TS_LOAD_HIGH_VAL_REG is shown in Figure 12-1814 and described in Table 12-3580.
Return to Summary Table.
Time Stamp Load High Value Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_LOAD_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_LOAD_VAL | R/W | 0h | Time stamp load high value |
PCIE_CPTS_TS_COMP_HIGH_VAL_REG is shown in Figure 12-1815 and described in Table 12-3582.
Return to Summary Table.
Time Stamp Comparison High Value Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_COMP_HIGH_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_COMP_HIGH_VAL | R/W | 0h | Time stamp comparison high value |
PCIE_CPTS_TS_ADD_VAL_REG is shown in Figure 12-1816 and described in Table 12-3584.
Return to Summary Table.
TS Add Value Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 604Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ADD_VAL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | X | |
2-0 | ADD_VAL | R/W | 0h | Add Value |
PCIE_CPTS_TS_PPM_LOW_VAL_REG is shown in Figure 12-1817 and described in Table 12-3586.
Return to Summary Table.
Time Stamp PPM Low Value Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_PPM_LOW_VAL | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | TS_PPM_LOW_VAL | R/W | 0h | Time stamp PPM Low value |
PCIE_CPTS_TS_PPM_HIGH_VAL_REG is shown in Figure 12-1818 and described in Table 12-3588.
Return to Summary Table.
Time Stamp PPM High Value Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_PPM_HIGH_VAL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | TS_PPM_HIGH_VAL | R/W | 0h | Time stamp PPM High value |
PCIE_CPTS_TS_NUDGE_VAL_REG is shown in Figure 12-1819 and described in Table 12-3590.
Return to Summary Table.
Time Stamp Nudge Value Register
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TS_NUDGE_VAL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | TS_NUDGE_VAL | R/W | 0h | Time stamp Nudge value |
PCIE_CPTS_COMP_LOW_REG is shown in Figure 12-1820 and described in Table 12-3592.
Return to Summary Table.
Time Stamp Generate Function Comparison Low Value
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 60E0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_LOW | R/W | 0h | Time Stamp Generate Function Comparison Low Value |
PCIE_CPTS_COMP_HIGH_REG is shown in Figure 12-1821 and described in Table 12-3594.
Return to Summary Table.
Time Stamp Generate Function Comparison high Value
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 60E4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_HIGH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_HIGH | R/W | 0h | Time Stamp Generate Function Comparison High Value |
PCIE_CPTS_CONTROL_REG is shown in Figure 12-1822 and described in Table 12-3596.
Return to Summary Table.
Time Stamp Generate Function Control
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 60E8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | POLARITY_INV | PPM_DIR | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | POLARITY_INV | R/W | 0h | Time Stamp Generate Function Polarity Invert |
0 | PPM_DIR | R/W | 0h | Time Stamp Generate Function PPM Direction |
PCIE_CPTS_LENGTH_REG is shown in Figure 12-1823 and described in Table 12-3598.
Return to Summary Table.
Time Stamp Generate Function Length Value
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 60ECh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LENGTH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LENGTH | R/W | 0h | Time Stamp Generate Function Length Value |
PCIE_CPTS_PPM_LOW_REG is shown in Figure 12-1824 and described in Table 12-3600.
Return to Summary Table.
Time Stamp Generate Function PPM Low Value
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 60F0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PPM_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PPM_LOW | R/W | 0h | Time Stamp Generate Function PPM Low Value |
PCIE_CPTS_PPM_HIGH_REG is shown in Figure 12-1825 and described in Table 12-3602.
Return to Summary Table.
Time Stamp Generate Function PPM High Value
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 60F4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PPM_HIGH | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | PPM_HIGH | R/W | 0h | Time Stamp Generate Function PPM High Value |
PCIE_CPTS_NUDGE_REG is shown in Figure 12-1826 and described in Table 12-3604.
Return to Summary Table.
Time Stamp Generate Function Nudge Value
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 60F8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUDGE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | NUDGE | R/W | 0h | Time Stamp Generate Function Nudge Value |
PCIE_CPTS_COMP_LOW_REG is shown in Figure 12-1827 and described in Table 12-3606.
Return to Summary Table.
Time Stamp ESTF Generate Function Comparison Low Value
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_LOW | R/W | 0h | Time Stamp ESTF Generate Function Comparison Low Value |
PCIE_CPTS_COMP_HIGH_REG is shown in Figure 12-1828 and described in Table 12-3608.
Return to Summary Table.
Time Stamp ESTF Generate Function Comparison high Value
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COMP_HIGH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | COMP_HIGH | R/W | 0h | Time Stamp ESTF Generate Function Comparison High Value |
PCIE_CPTS_CONTROL_REG is shown in Figure 12-1829 and described in Table 12-3610.
Return to Summary Table.
Time Stamp ESTF Generate Function Control
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | POLARITY_INV | PPM_DIR | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | POLARITY_INV | R/W | 0h | Time Stamp ESTF Generate Function Polarity Invert |
0 | PPM_DIR | R/W | 0h | Time Stamp ESTF Generate Function PPM Direction |
PCIE_CPTS_LENGTH_REG is shown in Figure 12-1830 and described in Table 12-3612.
Return to Summary Table.
Time Stamp ESTF Generate Function Length Value
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 620Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LENGTH | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | LENGTH | R/W | 0h | Time Stamp ESTF Generate Function Length Value |
PCIE_CPTS_PPM_LOW_REG is shown in Figure 12-1831 and described in Table 12-3614.
Return to Summary Table.
Time Stamp ESTF Generate Function PPM Low Value
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6210h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PPM_LOW | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PPM_LOW | R/W | 0h | Time Stamp ESTF Generate Function PPM Low Value |
PCIE_CPTS_PPM_HIGH_REG is shown in Figure 12-1832 and described in Table 12-3616.
Return to Summary Table.
Time Stamp ESTF Generate Function PPM High Value
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6214h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PPM_HIGH | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R/W | X | |
9-0 | PPM_HIGH | R/W | 0h | Time Stamp ESTF Generate Function PPM High Value |
PCIE_CPTS_NUDGE_REG is shown in Figure 12-1833 and described in Table 12-3618.
Return to Summary Table.
Time Stamp ESTF Generate Function Nudge Value
Instance | Physical Address |
---|---|
PCIE1_CORE_CPTS_CFG_CPTS_VBUSP | 0291 6218h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUDGE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | NUDGE | R/W | 0h | Time Stamp ESTF Generate Function Nudge Value |