SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The interrupt router (INTRTR) module provides a mechanism to mux M interrupt inputs to N interrupt outputs, where all M inputs are selectable to be driven per N ouput. There is one register per output (MUXCNTL_N) that controls the selection.
There are several INTRTR modules in the device. Their purpose is described in Section 9.1, Interrupt Architecture. Table 9-41 summarizes the configuration details for the various interrupt routers.
Module | Number of Inputs | Number of Outputs | Input Interrupt Type |
---|---|---|---|
WKUP_GPIOMUX_INTRTR0 | 120 | 32 | Pulse |
GPIOMUX_INTRTR0 | 304 | 64 | Pulse |
MAIN2MCU_LVL_INTRTR0 | 320 | 64 | Level |
MAIN2MCU_PLS_INTRTR0 | 104 | 48 | Pulse |
Some INTRTR instances support an additional input bus (IN_BIT0) that provides a dedicated input interrupt line for each MUXCNTL_N bit [0] location. However, this bus is not intended to be used in this device. Software should avoid writing '0' to the ENABLE (mux control) bit field in the MUXCNTL_N register for those interrupt routers. For more details, see MUXCNTL_N register descriptions in Section 9.3.3, INTRTR Registers.
The user should take the following into account when programming the MUXCNTL_N register:
The recommended general programming sequence is as follows: