SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Each ARMi_COREn has its own power domain, see Table 5-1345. Each (PD_A72_k) of these power domains can be transitioned independently. Table 5-1356 lists the possible A72 Core power states. See also Figure 5-659 for the power states of a core. No ARMi_COREn can transition out of the ARMi_COREn_OFF or ARMi_COREn_RESET states unless respective CC_ARMSS is in the A72SS_ON state.
ARMi_COREn can be in either WFI or WFE state after executing a WFI (Wait for Interrupt) or WFE (Wait For Event) Instruction, in which the block is On, but has additional clock gating applied to lower power.
Power Domain (PD_A72_n) | L2 Domain | L2 RAM Domain | Processors State |
---|---|---|---|
OFF | OFF | OFF | OFF |
L2 Dormant Mode Not supported in this family of devices. | OFF | ON | OFF |
RET(1) | |||
L2 Retention Mode Not supported in this family of devices. | ON | RET | WFx(1) |
RET | |||
OFF | |||
ON | ON | ON | ON |
WFx | |||
RET | |||
OFF |
Note that this family of device does not support retention. For more information about the Arm A72 core transitions among the power states, see Power Management Section in Arm® Cortex®-A72 MPCore Processor Technical Reference Manual, available at http://infocenter.arm.com/help/index.jsp.
Cold reset signal of the ARMi_COREn of A72SS is directly mapped to PORz reset on PSC0. The primary reset signals are directly mapped to MOD_G_RST on PSC0.