SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The MMCSD0 and MMCSD1 modules are hereinafter referred to as MMCSDi module.
This section describes the MMCSDi external connections (environment).
The MMCSD0 can be used for connection to 1, 4, or 8-bit devices (dedicated for connection to eMMC devices). The MMCSD1 can be used for connection to 1 or 4-bit devices (dedicated for connection to SD or SDIO devices). For each MMCSD an integrated UHS-I PHY provides interface to external device.
Figure 12-2195 shows the MMCSDi (where i = 0 to 1) connected to MMC, SD, or SDIO device.
Table 12-4329 describes the MMCSDi I/O signals.
Module Pin | Device Level Signal | I/O(1) | Description | Module Pin Reset Value |
---|---|---|---|---|
MMCSD0 | ||||
CLK | MMC0_CLK | O | External Clock | 0x0 |
CMD | MMC0_CMD | I/O | Command Line | 0x0 |
DAT[7:0] | MMC0_DAT[7:0] | I/O | Data Signals | 0x0 |
DS | MMC0_DS | I | Data Strobe | 0x0 |
CALPAD | MMC0_CALPAD(2) | A | PHY Calibration Resistor | HiZ |
MMCSD1 | ||||
CLK | MMC1_CLK | O | External Clock | 0x0 |
CMD | MMC1_CMD | I/O | Command Line | 0x0 |
DAT[3:0] | MMC1_DAT[3:0] | I/O | Data Signals | 0x0 |
WP | MMC1_SDWP | I | SD Card Write Protect | 0x1 |
CD | MMC1_SDCD | I | SD Card Detect | 0x0 |
For MMC1_CLK signal to work properly, the RXACTIVE bit of the PADMMR_PADCONFIG164PADMMR_PADCONFIG164CTRLMMR0_PADCONFIG63 register should be set to 0x1 because of retiming purposes.
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), refer to the device-specific Datasheet.