SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 5-657 lists the memory-mapped registers for the MCU_SEC_MMR0_BOOT_CTRL. All register offset addresses not listed in Table 5-657 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_SEC_MMR0_BOOT_CTRL | 45A5 0000h |
Offset | Acronym | Register Name | MCU_SEC_MMR0_BOOT_CTRL Physical Address |
---|---|---|---|
20h | CTRLMMR_MCUSEC_CLSTR0_DEF | Cluster0 Definition Register | 45A5 0020h |
40h | CTRLMMR_MCUSEC_CLSTR0_CFG | Cluster0 Configuration Register | 45A5 0040h |
100h | CTRLMMR_MCUSEC_CLSTR0_CORE0_CFG | Cluster0 Core0 Configuration Register | 45A5 0100h |
110h | CTRLMMR_MCUSEC_CLSTR0_CORE0_BOOTVECT_LO | Cluster0 Core0 Boot Vector Lo Register | 45A5 0110h |
114h | CTRLMMR_MCUSEC_CLSTR0_CORE0_BOOTVECT_HI | Cluster0 Core0 Boot Vector Hi Register | 45A5 0114h |
120h | CTRLMMR_MCUSEC_CLSTR0_CORE0_PMCTRL | Cluster0 Core0 Power Management Control | 45A5 0120h |
130h | CTRLMMR_MCUSEC_CLSTR0_CORE0_PMSTAT | Cluster0 Core0 Power Management Status Register | 45A5 0130h |
180h | CTRLMMR_MCUSEC_CLSTR0_CORE1_CFG | Cluster0 Core1 Configuration Register 0 | 45A5 0180h |
190h | CTRLMMR_MCUSEC_CLSTR0_CORE1_BOOTVECT_LO | Cluster0 Core1 Boot Vector Lo Register | 45A5 0190h |
194h | CTRLMMR_MCUSEC_CLSTR0_CORE1_BOOTVECT_HI | Cluster0 Core1 Boot Vector Hi Register | 45A5 0194h |
1A0h | CTRLMMR_MCUSEC_CLSTR0_CORE1_PMCTRL | Cluster0 Core1 Power Management Control | 45A5 01A0h |
1B0h | CTRLMMR_MCUSEC_CLSTR0_CORE1_PMSTAT | Cluster0 Core1 Power Management Status Register | 45A5 01B0h |
CTRLMMR_MCUSEC_CLSTR0_DEF is shown in Figure 5-321 and described in Table 5-659.
Return to Summary Table.
Defines the type of the processor cluster.
Instance | Physical Address |
---|---|
MCU_SEC_MMR0_BOOT_CTRL | 45A5 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CORE_NUM | ||||||
R-0h | R-2h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DSP_CORE_TYPE | |||||||
R-FFh | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ARM_CORE_TYPE | |||||||
R-10h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18-16 | CORE_NUM | R | 2h | Number of cores in cluster |
15-8 | DSP_CORE_TYPE | R | FFh | DSP core type configuration 00h - C7x 01h - C6x FFh - Not DSP |
7-0 | ARM_CORE_TYPE | R | 10h | ARM core type configuration 00h - A53 01h - A57 10h - R5 FFh - Not ARM |
CTRLMMR_MCUSEC_CLSTR0_CFG is shown in Figure 5-322 and described in Table 5-661.
Return to Summary Table.
Configures cluster level characteristics.
Instance | Physical Address |
---|---|
MCU_SEC_MMR0_BOOT_CTRL | 45A5 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CLSTR_CFG_RSVD | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CLSTR_CFG_RSVD | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CLSTR_CFG_RSVD | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CLSTR_CFG_RSVD | MEM_INIT_DIS | LOCKSTEP_EN | DBG_NO_CLKSTOP | TEINIT | LOCKSTEP | ||
R/W-0h | R/W-0h | R-X | R/W-0h | R/W-0h | R/W-X | ||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | CLSTR_CFG_RSVD | R/W | 0h | Reserved for future use. Write '0' to ensure compatibility with future devices. |
4 | MEM_INIT_DIS | R/W | 0h | Disables SRAM initialization (TCM, etc) at reset, |
3 | LOCKSTEP_EN | R | X | Lockstep enable. Indicates if R5 lockstep operation is supported on the device |
2 | DBG_NO_CLKSTOP | R/W | 0h | CPU clockstop behavior |
1 | TEINIT | R/W | 0h | Exception handling state at reset: |
0 | LOCKSTEP | R/W | X | When set, Core0 and Core1 operate in lockstep mode. Can only be changed if lockstep operation is supported as indicated by CLSTR0_CFG_lockstep_en = 1. If CLSTR0_CFG_lockstep_en = 0, lockstep is not supported, this bit will be read only with a value of 0. |
CTRLMMR_MCUSEC_CLSTR0_CORE0_CFG is shown in Figure 5-323 and described in Table 5-663.
Return to Summary Table.
Configures the TCM and interrupt operation of R5 Core0.
Instance | Physical Address |
---|---|
MCU_SEC_MMR0_BOOT_CTRL | 45A5 0100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NMFI_EN | RESERVED | TCM_RSTBASE | RESERVED | ||||
R/W-0h | R-0h | R/W-1h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTCM_EN | RESERVED | ATCM_EN | RESERVED | ||||
R/W-1h | R-0h | R/W-0h | R-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | NMFI_EN | R/W | 0h | Enable Core0 Non-Maskable Fast Interrupts |
14-12 | RESERVED | R | 0h | Reserved |
11 | TCM_RSTBASE | R/W | 1h | Core0 A/BTCM Reset Base Address Indicator |
10-8 | RESERVED | R | 0h | Reserved |
7 | BTCM_EN | R/W | 1h | Enable Core0 BTCM RAM at reset |
6-4 | RESERVED | R | 0h | Reserved |
3 | ATCM_EN | R/W | 0h | Enable Core0 ATCM RAM at reset |
2-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_MCUSEC_CLSTR0_CORE0_BOOTVECT_LO is shown in Figure 5-324 and described in Table 5-665.
Return to Summary Table.
Contains the lower 32 bits of the boot vector location for R5 Core0. Bits 6:0 are not used and are always 0.
Instance | Physical Address |
---|---|
MCU_SEC_MMR0_BOOT_CTRL | 45A5 0110h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VECT_ADDR | RESERVED | ||||||||||||||||||||||||||||||
R/W-830000h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | VECT_ADDR | R/W | 830000h | Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0. |
6-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_MCUSEC_CLSTR0_CORE0_BOOTVECT_HI is shown in Figure 5-325 and described in Table 5-667.
Return to Summary Table.
Contains the lower 16 bits of the boot vector location for R5 Core0.
Instance | Physical Address |
---|---|
MCU_SEC_MMR0_BOOT_CTRL | 45A5 0114h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VECT_ADDR | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VECT_ADDR | R/W | 0h | Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]. |
CTRLMMR_MCUSEC_CLSTR0_CORE0_PMCTRL is shown in Figure 5-326 and described in Table 5-669.
Return to Summary Table.
Instance | Physical Address |
---|---|
MCU_SEC_MMR0_BOOT_CTRL | 45A5 0120h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CORE_HALT | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | CORE_HALT | R/W | 0h | Halt Core0. When 0, indicates that Core0 is in the Halt state. |
CTRLMMR_MCUSEC_CLSTR0_CORE0_PMSTAT is shown in Figure 5-327 and described in Table 5-671.
Return to Summary Table.
Shows Cluster Core0 power status.
Instance | Physical Address |
---|---|
MCU_SEC_MMR0_BOOT_CTRL | 45A5 0130h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLK_GATE | RESERVED | WFE | WFI | |||
R-0h | R-X | R-0h | R-X | R-X | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CLK_GATE | R | X | Core0 Clocked stopped due to WFI or WFE state |
2 | RESERVED | R | 0h | Reserved |
1 | WFE | R | X | Core0 WFE |
0 | WFI | R | X | Core0 WFI |
CTRLMMR_MCUSEC_CLSTR0_CORE1_CFG is shown in Figure 5-328 and described in Table 5-673.
Return to Summary Table.
Configures the TCM and interrupt operation of R5 Core1.
Instance | Physical Address |
---|---|
MCU_SEC_MMR0_BOOT_CTRL | 45A5 0180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NMFI_EN | RESERVED | TCM_RSTBASE | RESERVED | ||||
R/W-0h | R-0h | R/W-1h | R-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BTCM_EN | RESERVED | ATCM_EN | RESERVED | ||||
R/W-1h | R-0h | R/W-0h | R-0h | ||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15 | NMFI_EN | R/W | 0h | Enable Core1 Non-Maskable Fast Interrupts |
14-12 | RESERVED | R | 0h | Reserved |
11 | TCM_RSTBASE | R/W | 1h | Core1 A/BTCM Reset Base Address Indicator |
10-8 | RESERVED | R | 0h | Reserved |
7 | BTCM_EN | R/W | 1h | Enable Core1 BTCM RAM at reset |
6-4 | RESERVED | R | 0h | Reserved |
3 | ATCM_EN | R/W | 0h | Enable Core1 ATCM RAM at reset |
2-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_MCUSEC_CLSTR0_CORE1_BOOTVECT_LO is shown in Figure 5-329 and described in Table 5-675.
Return to Summary Table.
Contains the lower 32 bits of the boot vector location for R5 Core1. Bits 6:0 are not used and are always 0.
Instance | Physical Address |
---|---|
MCU_SEC_MMR0_BOOT_CTRL | 45A5 0190h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VECT_ADDR | RESERVED | ||||||||||||||||||||||||||||||
R/W-830000h | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | VECT_ADDR | R/W | 830000h | Specifies the lower 25 bits of the 41-bit vector address corresponding to Vector Table address bits[31:7]. Note bits 6:0 of the Vector Table address are always 0. |
6-0 | RESERVED | R | 0h | Reserved |
CTRLMMR_MCUSEC_CLSTR0_CORE1_BOOTVECT_HI is shown in Figure 5-330 and described in Table 5-677.
Return to Summary Table.
Contains the lower 16 bits of the boot vector location for R5 Core1.
Instance | Physical Address |
---|---|
MCU_SEC_MMR0_BOOT_CTRL | 45A5 0194h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VECT_ADDR | ||||||||||||||||||||||||||||||
R-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | VECT_ADDR | R/W | 0h | Specifies the upper 16 bits of the 41-bit vector address corresponding to Vector Table address bits[47:32]. |
CTRLMMR_MCUSEC_CLSTR0_CORE1_PMCTRL is shown in Figure 5-331 and described in Table 5-679.
Return to Summary Table.
Configures Cluster Core1 power state.
Instance | Physical Address |
---|---|
MCU_SEC_MMR0_BOOT_CTRL | 45A5 01A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CORE_HALT | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | CORE_HALT | R/W | 0h | Halt Core1. When 0, indicates that Core1 is in the Halt state. |
CTRLMMR_MCUSEC_CLSTR0_CORE1_PMSTAT is shown in Figure 5-332 and described in Table 5-681.
Return to Summary Table.
Shows Cluster Core1 power status.
Instance | Physical Address |
---|---|
MCU_SEC_MMR0_BOOT_CTRL | 45A5 01B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | CLK_GATE | RESERVED | WFE | WFI | |||
R-0h | R-X | R-0h | R-X | R-X | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | CLK_GATE | R | X | Core1 Clocked stopped due to WFI or WFE state |
2 | RESERVED | R | 0h | Reserved |
1 | WFE | R | X | Core1 WFE |
0 | WFI | R | X | Core1 WFI |