SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This register contains the upper address bits of the transaction error that was captured. If the address is 32-bits or smaller, this field will be all 0. N is the number of bits on the source/dest address bus minus 33.
Bits | Field | Type | Reset | Description |
---|---|---|---|---|
31:N | Reserved | r | 0x0 | Reserved. Read as 0. |
N-1:0 | addr_u | r | 0x0 | Upper Address bits – If the captured transaction was a Timeout Error, this field represents the lower address bits N -1:32] of the original transaction. If the error was an Unexpected Response error, then this field is not applicable. |