SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 3-1 through Table 3-3 summarize the integration of WKUP_CBASS0 in device WKUP domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | ||
WKUP_CBASS0 | WKUP_PSC0 | PD0 | LPSC0 | |
WKUP_CBASS_FW0 | WKUP_PSC0 | PD0 | LPSC0 |
Clocks | |||
Module Instance | Source Clock Signal | Source | Description |
WKUP_CBASS0 | MCU_SYSCLK0/3 | WKUP_PLLCTRL0 | WKUP_CBASS0 clocks |
MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | ||
MCU_SYSCLK0/12 | WKUP_PLLCTRL0 | ||
WKUP_CBASS_FW0 | MCU_PLL_CLKOUT/3 | MCU_PLL0 | Clock for all WKUP_CBASS0 firewalls |
Resets | |||
Module Instance | Source Reset Signal | Source | Description |
WKUP_CBASS0 | MOD_G_RST | LPSC0 | WKUP_CBASS0 reset |
WKUP_CBASS_FW0 | MOD_G_RST | LPSC0 | Reset for all WKUP_CBASS0 firewalls |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
WKUP_CBASS0 | WKUP_COMMON_ERR_INTR | GIC500_SPI_IN_952 | GIC500 | WKUP CBASS null endpoint error interrupt | Level |
WKUP_DMSC0_INTR_IN_37 | WKUP_DMSC0 | ||||
R5FSS0_CORE0_INTR_IN_485 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_485 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_151 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_151 | MCU_R5FSS0_CORE1 | ||||
WKUP_FW_COMMON_ERR_INTR | GIC500_SPI_IN_953 | GIC500 | WKUP FW CBASS null endpoint error interrupt | Level | |
WKUP_DMSC0_INTR_IN_3 | WKUP_DMSC0 | ||||
R5FSS0_CORE0_INTR_IN_483 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_483 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_150 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_150 | MCU_R5FSS0_CORE1 | ||||
WKUP_TIMEOUT_INFRA0 | WKUP_TIMEOUT_INFRA0_SAFEG_TRANS_ERR_LVL_0 | WKUP_ESM0_LVL_IN_16 | WKUP_ESM0 | WKUP_TIMEOUT_INFRA0 timeout interrupt | Level |
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
WKUP_CBASS0 | - | - | - | - | - |
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.