SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Interrupt Input Line | Peripheral Interrupt | MAIN2MCU_PLS_INTRTR0_MUXCNTL_n [6-0] ENABLE Field Value (DEC) |
---|---|---|
RESERVED | RESERVED | 0(1) |
MAIN2MCU_PLS_INTRTR0_IN_1 | EHRPWM0_EPWM_ETINT_0 | 1 |
MAIN2MCU_PLS_INTRTR0_IN_2 | EHRPWM1_EPWM_ETINT_0 | 2 |
MAIN2MCU_PLS_INTRTR0_IN_3 | EHRPWM2_EPWM_ETINT_0 | 3 |
MAIN2MCU_PLS_INTRTR0_IN_4 | EHRPWM3_EPWM_ETINT_0 | 4 |
MAIN2MCU_PLS_INTRTR0_IN_5 | EHRPWM4_EPWM_ETINT_0 | 5 |
MAIN2MCU_PLS_INTRTR0_IN_6 | EHRPWM5_EPWM_ETINT_0 | 6 |
MAIN2MCU_PLS_INTRTR0_IN_7 | EHRPWM0_EPWM_TRIPZINT_0 | 7 |
MAIN2MCU_PLS_INTRTR0_IN_8 | EHRPWM1_EPWM_TRIPZINT_0 | 8 |
MAIN2MCU_PLS_INTRTR0_IN_9 | EHRPWM2_EPWM_TRIPZINT_0 | 9 |
MAIN2MCU_PLS_INTRTR0_IN_10 | EHRPWM3_EPWM_TRIPZINT_0 | 10 |
MAIN2MCU_PLS_INTRTR0_IN_11 | EHRPWM4_EPWM_TRIPZINT_0 | 11 |
MAIN2MCU_PLS_INTRTR0_IN_12 | EHRPWM5_EPWM_TRIPZINT_0 | 12 |
MAIN2MCU_PLS_INTRTR0_IN_13 | EQEP0_EQEP_INT_0 | 13 |
MAIN2MCU_PLS_INTRTR0_IN_14 | EQEP1_EQEP_INT_0 | 14 |
MAIN2MCU_PLS_INTRTR0_IN_15 | EQEP2_EQEP_INT_0 | 15 |
MAIN2MCU_PLS_INTRTR0_IN_16 | ECAP0_ECAP_INT_0 | 16 |
MAIN2MCU_PLS_INTRTR0_IN_17 | ECAP1_ECAP_INT_0 | 17 |
MAIN2MCU_PLS_INTRTR0_IN_18 | ECAP2_ECAP_INT_0 | 18 |
MAIN2MCU_PLS_INTRTR0_IN_27 | GLUELOGIC_SOCA_INT_GLUE_SOCA_INT_0 | 27 |
MAIN2MCU_PLS_INTRTR0_IN_28 | GLUELOGIC_SOCB_INT_GLUE_SOCB_INT_0 | 28 |
MAIN2MCU_PLS_INTRTR0_IN_39 | PCIE1_PCIE_LEGACY_PULSE_0 | 39 |
MAIN2MCU_PLS_INTRTR0_IN_40 | PCIE1_PCIE_DOWNSTREAM_PULSE_0 | 40 |
MAIN2MCU_PLS_INTRTR0_IN_41 | PCIE1_PCIE_FLR_PULSE_0 | 41 |
MAIN2MCU_PLS_INTRTR0_IN_42 | PCIE1_PCIE_ERROR_PULSE_0 | 42 |
MAIN2MCU_PLS_INTRTR0_IN_43 | PCIE1_PCIE_LINK_STATE_PULSE_0 | 43 |
MAIN2MCU_PLS_INTRTR0_IN_44 | PCIE1_PCIE_PWR_STATE_PULSE_0 | 44 |
MAIN2MCU_PLS_INTRTR0_IN_45 | PCIE1_PCIE_PTM_VALID_PULSE_0 | 45 |
MAIN2MCU_PLS_INTRTR0_IN_46 | PCIE1_PCIE_HOT_RESET_PULSE_0 | 46 |
MAIN2MCU_PLS_INTRTR0_IN_47 | PCIE1_PCIE_DPA_PULSE_0 | 47 |
MAIN2MCU_PLS_INTRTR0_IN_63 | GPIOMUX_INTRTR0_OUTP_0 | 63 |
MAIN2MCU_PLS_INTRTR0_IN_64 | GPIOMUX_INTRTR0_OUTP_1 | 64 |
MAIN2MCU_PLS_INTRTR0_IN_65 | GPIOMUX_INTRTR0_OUTP_2 | 65 |
MAIN2MCU_PLS_INTRTR0_IN_66 | GPIOMUX_INTRTR0_OUTP_3 | 66 |
MAIN2MCU_PLS_INTRTR0_IN_67 | GPIOMUX_INTRTR0_OUTP_4 | 67 |
MAIN2MCU_PLS_INTRTR0_IN_68 | GPIOMUX_INTRTR0_OUTP_5 | 68 |
MAIN2MCU_PLS_INTRTR0_IN_69 | GPIOMUX_INTRTR0_OUTP_6 | 69 |
MAIN2MCU_PLS_INTRTR0_IN_70 | GPIOMUX_INTRTR0_OUTP_7 | 70 |
MAIN2MCU_PLS_INTRTR0_IN_71 | GPIOMUX_INTRTR0_OUTP_8 | 71 |
MAIN2MCU_PLS_INTRTR0_IN_72 | GPIOMUX_INTRTR0_OUTP_9 | 72 |
MAIN2MCU_PLS_INTRTR0_IN_73 | GPIOMUX_INTRTR0_OUTP_10 | 73 |
MAIN2MCU_PLS_INTRTR0_IN_74 | GPIOMUX_INTRTR0_OUTP_11 | 74 |
MAIN2MCU_PLS_INTRTR0_IN_75 | GPIOMUX_INTRTR0_OUTP_12 | 75 |
MAIN2MCU_PLS_INTRTR0_IN_76 | GPIOMUX_INTRTR0_OUTP_13 | 76 |
MAIN2MCU_PLS_INTRTR0_IN_77 | GPIOMUX_INTRTR0_OUTP_14 | 77 |
MAIN2MCU_PLS_INTRTR0_IN_78 | GPIOMUX_INTRTR0_OUTP_15 | 78 |
MAIN2MCU_PLS_INTRTR0_IN_79 | GPIOMUX_INTRTR0_OUTP_16 | 79 |
MAIN2MCU_PLS_INTRTR0_IN_80 | GPIOMUX_INTRTR0_OUTP_17 | 80 |
MAIN2MCU_PLS_INTRTR0_IN_81 | GPIOMUX_INTRTR0_OUTP_18 | 81 |
MAIN2MCU_PLS_INTRTR0_IN_82 | GPIOMUX_INTRTR0_OUTP_19 | 82 |
MAIN2MCU_PLS_INTRTR0_IN_83 | GPIOMUX_INTRTR0_OUTP_20 | 83 |
MAIN2MCU_PLS_INTRTR0_IN_84 | GPIOMUX_INTRTR0_OUTP_21 | 84 |
MAIN2MCU_PLS_INTRTR0_IN_85 | GPIOMUX_INTRTR0_OUTP_22 | 85 |
MAIN2MCU_PLS_INTRTR0_IN_86 | GPIOMUX_INTRTR0_OUTP_23 | 86 |
MAIN2MCU_PLS_INTRTR0_IN_87 | GPIOMUX_INTRTR0_OUTP_24 | 87 |
MAIN2MCU_PLS_INTRTR0_IN_88 | GPIOMUX_INTRTR0_OUTP_25 | 88 |
MAIN2MCU_PLS_INTRTR0_IN_89 | GPIOMUX_INTRTR0_OUTP_26 | 89 |
MAIN2MCU_PLS_INTRTR0_IN_90 | GPIOMUX_INTRTR0_OUTP_27 | 90 |
MAIN2MCU_PLS_INTRTR0_IN_91 | GPIOMUX_INTRTR0_OUTP_28 | 91 |
MAIN2MCU_PLS_INTRTR0_IN_92 | GPIOMUX_INTRTR0_OUTP_29 | 92 |
MAIN2MCU_PLS_INTRTR0_IN_93 | GPIOMUX_INTRTR0_OUTP_30 | 93 |
MAIN2MCU_PLS_INTRTR0_IN_94 | GPIOMUX_INTRTR0_OUTP_31 | 94 |
MAIN2MCU_PLS_INTRTR0_IN_95 | CMPEVENT_INTRTR0_OUTP_4 | 95 |
MAIN2MCU_PLS_INTRTR0_IN_96 | CMPEVENT_INTRTR0_OUTP_5 | 96 |
MAIN2MCU_PLS_INTRTR0_IN_97 | CMPEVENT_INTRTR0_OUTP_6 | 97 |
MAIN2MCU_PLS_INTRTR0_IN_98 | CMPEVENT_INTRTR0_OUTP_7 | 98 |