SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The OBSCLK0, OBSCLK1, and OBSCLK2 output pins are controlled simultaneously,so that the three pins are connected to the same signal. OBSCLK0, OBSCLK1, and OBSCLK2 outputs are controlled by CTRLMMR_OBSCLK0_CTRL register in the CTRL_MMR0 module; for more information about control registers, see Section 5.1, Control Module (CTRL_MMR). Figure 5-754 shows a block diagram of internal OBSCLK0 mux connections.
OBSCLK2 has lot more jitter due to PD limitations/long routing. If the intent is to use OBSCLK2 to do anything beyond just observe clock toggle, customers should switch to OBSCLK0 or OBSCLK1.
CTRLMMR_OBSCLK1_CTRL(1)[1-0] CLK_SEL | OBSCLK0_MUX1_CLKOUT Selection |
---|---|
0x0 | 0 (GND)(2) |
0x1 | MAIN_PLL8_HSDIV0_CLKOUT / 8 |
0x2 | 0 (GND)(2) |
0x3 | 0 (GND)(2) |
CTRLMMR_OBSCLK0_CTRL(2)[4-0] CLK_SEL | OBSCLK0, OBSCLK1, and OBSCLK2 Selection (1) |
---|---|
0x0 | MAIN_PLL0_HSDIV0_CLKOUT |
0x1 | MAIN_PLL1_HSDIV0_CLKOUT |
0x2 | MAIN_PLL2_HSDIV0_CLKOUT |
0x3 | MAIN_PLL3_HSDIV0_CLKOUT |
0x4 | MAIN_PLL4_HSDIV0_CLKOUT |
0x5 | 0 (GND)(3) |
0x6 | 0 (GND)(3) |
0x7 | 0 (GND)(3) |
0x8 | 0 (GND)(3) |
0x9 | 0 (GND)(3) |
0xA | 0 (GND)(3) |
0xB | 0 (GND)(3) |
0xC | MAIN_PLL12_HSDIV0_CLKOUT |
0xD | Input from Table 5-1570 |
0xE | MAIN_PLL14_HSDIV0_CLKOUT |
0xF | 0 (GND)(3) |
0x10 | 0 (GND)(3) |
0x11 | 0 (GND)(3) |
0x12 | 0 (GND)(3) |
0x13 | 0 (GND)(3) |
0x14 | 0 (GND)(3) |
0x15 | 0 (GND)(3) |
0x16 | 0 (GND)(3) |
0x17 | 0 (GND)(3) |
0x18 | 0 (GND)(3) |
0x19 | 0 (GND)(3) |
0x1A | CPTS_GENF3 |
0x1B | CLK_12M_RC |
0x1C | WKUP_LFOSC0_CLKOUT |
0x1D | PLLCTRL_OBSCLK (PLL0 input reference clock) |
0x1E | HFOSC1_CLK |
0x1F | WKUP_HFOSC0_CLKOUT |
The value of the software-controlled 8-bit divider is determined by register CTRLMMR_OBSCLK0_CTRL[15-8] OBSCLK_CTRL_CLK_DIV; for more information about control registers, see Section 5.1, Control Module (CTRL_MMR).