SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-1757 lists the memory-mapped registers for the MCU_CPSW0_CONTROL. All register offset addresses not listed in Table 12-1757 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4600 0000h |
Offset | Acronym | Register Name | MCU_CPSW0_NUSS_CONTROL Physical Address |
---|---|---|---|
00020000h | CPSW_CPSW_ID_VER_REG | ID Version Register | 4602 0000h |
00020004h | CPSW_CONTROL_REG | Control Register | 4602 0004h |
00020010h | CPSW_EM_CONTROL_REG | Emulation Control Register | 4602 0010h |
00020014h | CPSW_STAT_PORT_EN_REG | Statistics Port Enable Register | 4602 0014h |
00020018h | CPSW_PTYPE_REG | Transmit Priority Type Register | 4602 0018h |
0002001Ch | CPSW_SOFT_IDLE_REG | Software Idle Register | 4602 001Ch |
00020020h | CPSW_THRU_RATE_REG | Thru Rate Register | 4602 0020h |
00020024h | CPSW_GAP_THRESH_REG | Transmit FIFO Short Gap Threshold Register | 4602 0024h |
00020028h | CPSW_TX_START_WDS_REG | Transmit FIFO Start Words Register | 4602 0028h |
0002002Ch | CPSW_EEE_PRESCALE_REG | Energy Efficient Ethernet Prescale Value Register | 4602 002Ch |
00020030h | CPSW_TX_G_OFLOW_THRESH_SET_REG | PFC Tx Global Out Flow Threshold Set Register | 4602 0030h |
00020034h | CPSW_TX_G_OFLOW_THRESH_CLR_REG | PFC Tx Global Out Flow Threshold Clear Register | 4602 0034h |
00020038h | CPSW_TX_G_BUF_THRESH_SET_L_REG | PFC Global Tx Buffer Threshold Set Low Register | 4602 0038h |
0002003Ch | CPSW_TX_G_BUF_THRESH_SET_H_REG | PFC Global Tx Buffer Threshold Set High Register | 4602 003Ch |
00020040h | CPSW_TX_G_BUF_THRESH_CLR_L_REG | PFC Global Tx Buffer Threshold Clear Low Register | 4602 0040h |
00020044h | CPSW_TX_G_BUF_THRESH_CLR_H_REG | PFC Global Tx Buffer Threshold Clear High Register | 4602 0044h |
00020050h | CPSW_VLAN_LTYPE_REG | VLAN LTYPE Outer and Inner Register | 4602 0050h |
00020054h | CPSW_EST_TS_DOMAIN_REG | EST Timestamp Domain Register | 4602 0054h |
00020100h | CPSW_TX_PRI0_MAXLEN_REG | Priority 0 Maximum Transmit Packet Length Register | 4602 0100h |
00020104h | CPSW_TX_PRI1_MAXLEN_REG | Priority 1 Maximum Transmit Packet Length Register | 4602 0104h |
00020108h | CPSW_TX_PRI2_MAXLEN_REG | Priority 2 Maximum Transmit Packet Length Register | 4602 0108h |
0002010Ch | CPSW_TX_PRI3_MAXLEN_REG | Priority 3 Maximum Transmit Packet Length Register | 4602 010Ch |
00020110h | CPSW_TX_PRI4_MAXLEN_REG | Priority 4 Maximum Transmit Packet Length Register | 4602 0110h |
00020114h | CPSW_TX_PRI5_MAXLEN_REG | Priority 5 Maximum Transmit Packet Length Register | 4602 0114h |
00020118h | CPSW_TX_PRI6_MAXLEN_REG | Priority 6 Maximum Transmit Packet Length Register | 4602 0118h |
0002011Ch | CPSW_TX_PRI7_MAXLEN_REG | Priority 7 Maximum Transmit Packet Length Register | 4602 011Ch |
00021004h | CPSW_P0_CONTROL_REG | CPPI Port 0 Control Register | 4602 1004h |
00021008h | CPSW_P0_FLOW_ID_OFFSET_REG | CPPI Port 0 Transmit FLOW ID Offset Register | 4602 1008h |
00021010h | CPSW_P0_BLK_CNT_REG | CPPI Port 0 FIFO Block Usage Count Register | 4602 1010h |
00021014h | CPSW_P0_PORT_VLAN_REG | CPPI Port 0 VLAN Register | 4602 1014h |
00021018h | CPSW_P0_TX_PRI_MAP_REG | CPPI Port 0 Tx Header Priority to Switch Priority Map Register | 4602 1018h |
0002101Ch | CPSW_P0_PRI_CTL_REG | CPPI Port 0 Priority Control Register | 4602 101Ch |
00021020h | CPSW_P0_RX_PRI_MAP_REG | CPPI Port 0 RX Paket Priority to Header Priority Map Register | 4602 1020h |
00021024h | CPSW_P0_RX_MAXLEN_REG | CPPI Port 0 Receive Frame Max Length Register | 4602 1024h |
00021028h | CPSW_P0_TX_BLKS_PRI_REG | CPPI Port 0 Transmit Block Sub Per Priority Register | 4602 1028h |
00021030h | CPSW_P0_IDLE2LPI_REG | CPPI Port 0 EEE Idle to LPI Count Register | 4602 1030h |
00021034h | CPSW_P0_LPI2WAKE_REG | CPPI Port 0 EEE LPI to Wakeup Count Register | 4602 1034h |
00021038h | CPSW_P0_EEE_STATUS_REG | CPPI Port 0 EEE Port Status Register | 4602 1038h |
0002103Ch | CPSW_P0_RX_PKTS_PRI_REG | CPPI Port 0 Receive Packets Per Priority Register | 4602 103Ch |
0002104Ch | CPSW_P0_RX_GAP_REG | CPPI Port 0 Receive Gap Register | 4602 104Ch |
00021050h | CPSW_P0_FIFO_STATUS_REG | CPPI Port 0 FIFO Status Register | 4602 1050h |
00021120h + formula | CPSW_P0_RX_DSCP_MAP_REG_y | CPPI Port 0 Receive IPV4/IPV6 DSCP Map 0 to Map 7 Registers | 4602 1120h + formula |
00021140h + formula | CPSW_P0_PRI_CIR_REG_y | CPPI Port 0 Rx Priority 0 to Priority 7 Committed Information Rate Registers | 4602 1140h + formula |
00021160h + formula | CPSW_P0_PRI_EIR_REG_y | CPPI Port 0 Rx Priority 0 to Priority 7 Excess Information Rate Registers | 4602 1160h + formula |
00021180h | CPSW_P0_TX_D_THRESH_SET_L_REG | CPPI Port 0 Tx PFC Destination Threshold Set Low Register | 4602 1180h |
00021184h | CPSW_P0_TX_D_THRESH_SET_H_REG | CPPI Port 0 Tx PFC Destination Threshold Set High Register | 4602 1184h |
00021188h | CPSW_P0_TX_D_THRESH_CLR_L_REG | CPPI Port 0 Tx PFC Destination Threshold Clear Low Register | 4602 1188h |
0002118Ch | CPSW_P0_TX_D_THRESH_CLR_H_REG | CPPI Port 0 Tx PFC Destination Threshold Clear High Register | 4602 118Ch |
00021190h | CPSW_P0_TX_G_BUF_THRESH_SET_L_REG | CPPI Port 0 Tx PFC Global Buffer Threshold Set Low Register | 4602 1190h |
00021194h | CPSW_P0_TX_G_BUF_THRESH_SET_H_REG | CPPI Port 0 Tx PFC Global Buffer Threshold Set High Register | 4602 1194h |
00021198h | CPSW_P0_TX_G_BUF_THRESH_CLR_L_REG | CPPI Port 0 Tx PFC Global Buffer Threshold Clear Low Register | 4602 1198h |
0002119Ch | CPSW_P0_TX_G_BUF_THRESH_CLR_H_REG | CPPI Port 0 Tx PFC Global Buffer Threshold Clear High Register | 4602 119Ch |
00021300h | CPSW_P0_SRC_ID_A_REG | CPPI Port 0 CPPI Source ID A Register | 4602 1300h |
00021304h | RESERVED | Reserved | 4602 1304h |
00021320h | CPSW_P0_HOST_BLKS_PRI_REG | CPPI Port 0 Host Blocks Priority Register | 4602 1320h |
00022000h | CPSW_PN_RESERVED_REG | Reserved Register | 4602 2000h |
00022004h | CPSW_PN_CONTROL_REG | Ethernet Port N Control Register | 4602 2004h |
00022008h | CPSW_PN_MAX_BLKS_REG | Ethernet Port N Maximum Blocks Register | 4602 2008h |
00022010h | CPSW_PN_BLK_CNT_REG | Ethernet Port N FIFO Block Usage Count Register | 4602 2010h |
00022014h | CPSW_PN_PORT_VLAN_REG | Ethernet Port N VLAN Register | 4602 2014h |
00022018h | CPSW_PN_TX_PRI_MAP_REG | Ethernet Port N Tx Header Priority to Switch Priority Mapping Register | 4602 2018h |
0002201Ch | CPSW_PN_PRI_CTL_REG | Ethernet Port N Priority Control Register | 4602 201Ch |
00022020h | CPSW_PN_RX_PRI_MAP_REG | Ethernet Port N RX Paket Priority to Header Priority Map | 4602 2020h |
00022024h | CPSW_PN_RX_MAXLEN_REG | Ethernet Port N Receive Frame Maximum Length Register | 4602 2024h |
00022028h | CPSW_PN_TX_BLKS_PRI_REG | Ethernet Port N Transmit Block Sub Per Priority Register | 4602 2028h |
0002202Ch | CPSW_PN_RX_FLOW_THRESH_REG | Ethernet Port N Receive Flow Threshold Register | 4602 202Ch |
00022030h | CPSW_PN_IDLE2LPI_REG | Ethernet Port N EEE Idle to LPI Count Register | 4602 2030h |
00022034h | CPSW_PN_LPI2WAKE_REG | Ethernet Port N EEE LPI to Wake Count Register | 4602 2034h |
00022038h | CPSW_PN_EEE_STATUS_REG | Ethernet Port N EEE Status Register | 4602 2038h |
00022040h | CPSW_PN_IET_CONTROL_REG | Ethernet Port N FIFO Status Register | 4602 2040h |
00022044h | CPSW_PN_IET_STATUS_REG | Ethernet Port N Enhanced Scheduled Traffic (EST) Control Register | 4602 2044h |
00022048h | CPSW_PN_IET_VERIFY_REG | Ethernet Port N Receive IPV4/IPV6 DSCP Map 0 to Map 7 Registers | 4602 2048h |
00022050h | CPSW_PN_FIFO_STATUS_REG | Ethernet Port N Rx Priority 0 to Priority 7 Committed Information Rate Registers | 4602 2050h |
00022060h | CPSW_PN_EST_CONTROL_REG | Ethernet Port N Rx Priority 0 to Priority 7 Excess Information Rate Registers | 4602 2060h |
00022120h + formula | CPSW_PN_RX_DSCP_MAP_REG_y | Ethernet Port N Tx PFC Destination Threshold Set Low Register | 4602 2120h + formula |
00022140h + formula | CPSW_PN_PRI_CIR_REG_y | Ethernet Port N Tx PFC Destination Threshold Set High Register | 4602 2140h + formula |
00022160h + formula | CPSW_PN_PRI_EIR_REG_y | Ethernet Port N Tx PFC Destination Threshold Clear Low Register | 4602 2160h + formula |
00022180h | CPSW_PN_TX_D_THRESH_SET_L_REG | Ethernet Port N Tx PFC Destination Threshold Clear High Register | 4602 2180h |
00022184h | CPSW_PN_TX_D_THRESH_SET_H_REG | Ethernet Port N Tx PFC Global Buffer Threshold Set Low Register | 4602 2184h |
00022188h | CPSW_PN_TX_D_THRESH_CLR_L_REG | Ethernet Port N Tx PFC Global Buffer Threshold Set High Register | 4602 2188h |
0002218Ch | CPSW_PN_TX_D_THRESH_CLR_H_REG | Ethernet Port N Tx PFC Global Buffer Threshold Clear Low Register | 4602 218Ch |
00022190h | CPSW_PN_TX_G_BUF_THRESH_SET_L_REG | Ethernet Port N Tx PFC Global Buffer Threshold Clear High Register | 4602 2190h |
00022194h | CPSW_PN_TX_G_BUF_THRESH_SET_H_REG | Ethernet Port N Tx Destination Out Flow Add Values Low Register | 4602 2194h |
00022198h | CPSW_PN_TX_G_BUF_THRESH_CLR_L_REG | Ethernet Port N Tx Destination Out Flow Add Values High Register | 4602 2198h |
0002219Ch | CPSW_PN_TX_G_BUF_THRESH_CLR_H_REG | Ethernet Port N Tx Pause Frame Source Address Low Register | 4602 219Ch |
00022300h | CPSW_PN_TX_D_OFLOW_ADDVAL_L_REG | Ethernet Port N Tx Pause Frame Source Address High Register | 4602 2300h |
00022304h | CPSW_PN_TX_D_OFLOW_ADDVAL_H_REG | Ethernet Port N Time Sync Control Register | 4602 2304h |
00022308h | CPSW_PN_SA_L_REG | Ethernet Port N Time Sync LTYPE Register (and SEQ_ID_OFFSET) | 4602 2308h |
0002230Ch | CPSW_PN_SA_H_REG | Ethernet Port N Time Sync VLAN2 and VLAN2 Register | 4602 230Ch |
00022310h | CPSW_PN_TS_CTL_REG | Ethernet Port N Time Sync Control and LTYPE 2 Register | 4602 2310h |
00022314h | CPSW_PN_TS_SEQ_LTYPE_REG | Ethernet Port N Time Sync Control 2 Register | 4602 2314h |
00022318h | CPSW_PN_TS_VLAN_LTYPE_REG | Ethernet Port N Mac Control Register | 4602 2318h |
0002231Ch | CPSW_PN_TS_CTL_LTYPE2_REG | Ethernet Port N Mac Status Register | 4602 231Ch |
00022320h | CPSW_PN_TS_CTL2_REG | Ethernet Port N Mac Software Reset Register | 4602 2320h |
00022330h | CPSW_PN_MAC_CONTROL_REG | Ethernet Port N Mac Backoff Test Register | 4602 2330h |
00022334h | CPSW_PN_MAC_STATUS_REG | Ethernet Port N 802.3 Receive Pause Timer Register | 4602 2334h |
00022338h | CPSW_PN_MAC_SOFT_RESET_REG | Ethernet Port N PFC Priority 0 to Priority 7 Rx Pause Timer Registers | 4602 2338h |
0002233Ch | CPSW_PN_MAC_BOFFTEST_REG | Ethernet Port N 802.3 Tx Pause Timer Registers | 4602 233Ch |
00022340h | CPSW_PN_MAC_RX_PAUSETIMER_REG | Ethernet Port N PFC Priority 0 to Priority 7 Tx Pause Timer Registers | 4602 2340h |
00022350h + formula (1) | CPSW_PN_MAC_RXN_PAUSETIMER_REG_y | Ethernet Port N Emulation Control Register | 4602 2350h + formula |
00022370h | CPSW_PN_MAC_TX_PAUSETIMER_REG | Ethernet Port N Tx Inter Packet Gap Register | 4602 2370h |
00022380h + formula | CPSW_PN_MAC_TXN_PAUSETIMER_REG_y | 4602 2380h + formula | |
000223A0h | CPSW_PN_MAC_EMCONTROL_REG | 4602 23A0h | |
000223A4h | CPSW_PN_MAC_TX_GAP_REG | 4602 23A4h | |
000223ACh | CPSW_PN_INTERVLAN_OPX_POINTER_REG | 4602 23ACh | |
000223B0h | CPSW_PN_INTERVLAN_OPX_A_REG | 4602 23B0h | |
000223B4h | CPSW_PN_INTERVLAN_OPX_B_REG | 4602 23B4h | |
000223B8h | CPSW_PN_INTERVLAN_OPX_C_REG | 4602 23B8h | |
000223BCh | CPSW_PN_INTERVLAN_OPX_D_REG | 4602 23BCh |
CPSW_CPSW_ID_VER_REG is shown in Figure 12-604 and described in Table 12-1138.
Return to Summary Table.
CPSW ID Version Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
IDENT | |||||||
R-6BA8h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IDENT | |||||||
R-6BA8h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RTL_VER | MAJOR_VER | ||||||
R-0h | R-1h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CUSTOM_VER | MINOR_VER | ||||||
R-0h | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | IDENT | R | 6BA8h | Identification Value |
15-11 | RTL_VER | R | Eh | RTL Version Value |
10-8 | MAJOR_VER | R | 1h | Major Version Value |
7-6 | CUSTOM_VER | R | 0h | Custom Version Value |
5-0 | MINOR_VER | R | 0h | Minor Version Value |
CPSW_CONTROL_REG is shown in Figure 12-605 and described in Table 12-1140.
Return to Summary Table.
CPSW Switch Control Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
ECC_CRC_MODE | RESERVED | ||||||
R/W-0h | R/W-X | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | EST_ENABLE | IET_ENABLE | EEE_ENABLE | ||||
R/W-X | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
P0_RX_PASS_CRC_ERR | P0_RX_PAD | P0_TX_CRC_REMOVE | RESERVED | P8_PASS_PRI_TAGGED | P7_PASS_PRI_TAGGED | P6_PASS_PRI_TAGGED | P5_PASS_PRI_TAGGED |
R/W-0h | R/W-0h | R/W-0h | R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P4_PASS_PRI_TAGGED | P3_PASS_PRI_TAGGED | P2_PASS_PRI_TAGGED | P1_PASS_PRI_TAGGED | P0_PASS_PRI_TAGGED | P0_ENABLE | VLAN_AWARE | S_CN_SWITCH |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | ECC_CRC_MODE | R/W | 0h | ECC CRC Mode. |
30-19 | RESERVED | R/W | X | |
18 | EST_ENABLE | R/W | 0h | Enhanced Scheduled Traffic enable (EST) |
17 | IET_ENABLE | R/W | 0h | Intersperced Express Traffic enable (IET) |
16 | EEE_ENABLE | R/W | 0h | Energy Efficient Ethernet enable |
15 | P0_RX_PASS_CRC_ERR | R/W | 0h | Port 0 Pass Received CRC errors |
14 | P0_RX_PAD | R/W | 0h | Port 0 Receive Short Packet Pad |
13 | P0_TX_CRC_REMOVE | R/W | 0h | Port 0 Transmit CRC remove. |
12 | RESERVED | R/W | X | |
11 | P8_PASS_PRI_TAGGED | R/W | 0h | Port 8 Pass Priority Tagged |
10 | P7_PASS_PRI_TAGGED | R/W | 0h | Port 7 Pass Priority Tagged |
9 | P6_PASS_PRI_TAGGED | R/W | 0h | Port 6 Pass Priority Tagged |
8 | P5_PASS_PRI_TAGGED | R/W | 0h | Port 5 Pass Priority Tagged |
7 | P4_PASS_PRI_TAGGED | R/W | 0h | Port 4 Pass Priority Tagged |
6 | P3_PASS_PRI_TAGGED | R/W | 0h | Port 3 Pass Priority Tagged |
5 | P2_PASS_PRI_TAGGED | R/W | 0h | Port 2 Pass Priority Tagged |
4 | P1_PASS_PRI_TAGGED | R/W | 0h | Port 1 Pass Priority Tagged |
3 | P0_PASS_PRI_TAGGED | R/W | 0h | Port 0 Pass Priority Tagged |
2 | P0_ENABLE | R/W | 0h | Port 0 Enable |
1 | VLAN_AWARE | R/W | 0h | VLAN Aware Mode: |
0 | S_CN_SWITCH | R/W | 0h | Service or Customer VLAN switch. |
CPSW_EM_CONTROL_REG is shown in Figure 12-606 and described in Table 12-1142.
Return to Summary Table.
CPSW Emulation Control Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT | FREE | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | SOFT | R/W | 0h | Emulation Soft Bit |
0 | FREE | R/W | 0h | Emulation Free Bit |
CPSW_STAT_PORT_EN_REG is shown in Figure 12-607 and described in Table 12-1144.
Return to Summary Table.
CPSW Statistics Port Enable Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | P8_STAT_EN | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
P7_STAT_EN | P6_STAT_EN | P5_STAT_EN | P4_STAT_EN | P3_STAT_EN | P2_STAT_EN | P1_STAT_EN | P0_STAT_EN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R/W | X | |
8 | P8_STAT_EN | R/W | 0h | Port 8 Statistics Enable (if N > 8) |
7 | P7_STAT_EN | R/W | 0h | Port 7 Statistics Enable (if N > 7) |
6 | P6_STAT_EN | R/W | 0h | Port 6 Statistics Enable (if N > 6) |
5 | P5_STAT_EN | R/W | 0h | Port 5 Statistics Enable (if N > 5) |
4 | P4_STAT_EN | R/W | 0h | Port 4 Statistics Enable (if N > 4) |
3 | P3_STAT_EN | R/W | 0h | Port 3 Statistics Enable (if N > 3) |
2 | P2_STAT_EN | R/W | 0h | Port 2 Statistics Enable (if N > 2) |
1 | P1_STAT_EN | R/W | 0h | Port 1 Statistics Enable |
0 | P0_STAT_EN | R/W | 0h | Port 0 Statistics Enable |
CPSW_PTYPE_REG is shown in Figure 12-608 and described in Table 12-1146.
Return to Summary Table.
CPSW Transmit Priority Type Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | P8_PTYPE_ESC | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
P7_PTYPE_ESC | P6_PTYPE_ESC | P5_PTYPE_ESC | P4_PTYPE_ESC | P3_PTYPE_ESC | P2_PTYPE_ESC | P1_PTYPE_ESC | P0_PTYPE_ESC |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ESC_PRI_LD_VAL | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-17 | RESERVED | R/W | X | |
16 | P8_PTYPE_ESC | R/W | 0h | Port 8 Priority Type Escalate (if N > 8) |
15 | P7_PTYPE_ESC | R/W | 0h | Port 7 Priority Type Escalate (if N > 7) |
14 | P6_PTYPE_ESC | R/W | 0h | Port 6 Priority Type Escalate (if N > 6) |
13 | P5_PTYPE_ESC | R/W | 0h | Port 5 Priority Type Escalate (if N > 5) |
12 | P4_PTYPE_ESC | R/W | 0h | Port 4 Priority Type Escalate (if N > 4) |
11 | P3_PTYPE_ESC | R/W | 0h | Port 3 Priority Type Escalate (if N > 3) |
10 | P2_PTYPE_ESC | R/W | 0h | Port 2 Priority Type Escalate (if N > 2) |
9 | P1_PTYPE_ESC | R/W | 0h | Port 1 Priority Type Escalate |
8 | P0_PTYPE_ESC | R/W | 0h | Port 0 Priority Type Escalate |
7-5 | RESERVED | R/W | X | |
4-0 | ESC_PRI_LD_VAL | R/W | 0h | Escalate Priority Load Value |
CPSW_SOFT_IDLE_REG is shown in Figure 12-609 and described in Table 12-1148.
Return to Summary Table.
CPSW Software Idle
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT_IDLE | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | SOFT_IDLE | R/W | 0h | Software Idle. |
CPSW_THRU_RATE_REG is shown in Figure 12-610 and described in Table 12-1150.
Return to Summary Table.
CPSW Thru Rate Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
SL_RX_THRU_RATE | RESERVED | ||||||
R/W-3h | R/W-X | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | P0_RX_THRU_RATE | ||||||
R/W-X | R/W-1h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-12 | SL_RX_THRU_RATE | R/W | 3h | Ethernet Port Switch FIFO receive through rate. |
11-4 | RESERVED | R/W | X | |
3-0 | P0_RX_THRU_RATE | R/W | 1h | CPPI FIFO (port 0) receive through rate. |
CPSW_GAP_THRESH_REG is shown in Figure 12-611 and described in Table 12-1152.
Return to Summary Table.
CPSW Transmit FIFO Short Gap Threshold Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | GAP_THRESH | ||||||||||||||
R/W-X | R/W-Bh | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4-0 | GAP_THRESH | R/W | Bh | Ethernet Port Short Gap Threshold. |
CPSW_TX_START_WDS_REG is shown in Figure 12-612 and described in Table 12-1154.
Return to Summary Table.
CPSW Transmit FIFO Start Words Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_START_WDS | ||||||||||||||
R/W-X | R/W-8h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R/W | X | |
10-0 | TX_START_WDS | R/W | 8h | FIFO Packet Transmit (egress) Start Words. |
CPSW_EEE_PRESCALE_REG is shown in Figure 12-613 and described in Table 12-1156.
Return to Summary Table.
CPSW Energy Efficient Ethernet Prescale Value Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 002Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EEE_PRESCALE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R/W | X | |
11-0 | EEE_PRESCALE | R/W | 0h | Energy Efficient Ethernet Pre-scale count load value. |
CPSW_TX_G_OFLOW_THRESH_SET_REG is shown in Figure 12-614 and described in Table 12-1158.
Return to Summary Table.
CPSW PFC Tx Global Out Flow Threshold Set
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI7 | PRI6 | PRI5 | PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | ||||||||||||||||||||||||
R/W-Fh | R/W-Fh | R/W-Fh | R/W-Fh | R/W-Fh | R/W-Fh | R/W-Fh | R/W-Fh | ||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | PRI7 | R/W | Fh | Priority Based Flow Control Global Outflow Usage Threshold for Pri 7 |
27-24 | PRI6 | R/W | Fh | Priority Based Flow Control Global Outflow Usage Threshold for Pri 6 |
23-20 | PRI5 | R/W | Fh | Priority Based Flow Control Global Outflow Usage Threshold for Pri 5 |
19-16 | PRI4 | R/W | Fh | Priority Based Flow Control Global Outflow Usage Threshold for Pri 4 |
15-12 | PRI3 | R/W | Fh | Priority Based Flow Control Global Outflow Usage Threshold for Pri 3 |
11-8 | PRI2 | R/W | Fh | Priority Based Flow Control Global Outflow Usage Threshold for Pri 2 |
7-4 | PRI1 | R/W | Fh | Priority Based Flow Control Global Outflow Usage Threshold for Pri 1 |
3-0 | PRI0 | R/W | Fh | Priority Based Flow Control Global Outflow Usage Threshold for Pri 0 |
CPSW_TX_G_OFLOW_THRESH_CLR_REG is shown in Figure 12-615 and described in Table 12-1160.
Return to Summary Table.
CPSW PFC Tx Global Out Flow Threshold Clear Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI7 | PRI6 | PRI5 | PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | ||||||||||||||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | PRI7 | R/W | 0h | Priority Based Flow Control Global Outflow Usage Threshold for Pri 7 |
27-24 | PRI6 | R/W | 0h | Priority Based Flow Control Global Outflow Usage Threshold for Pri 6 |
23-20 | PRI5 | R/W | 0h | Priority Based Flow Control Global Outflow Usage Threshold for Pri 5 |
19-16 | PRI4 | R/W | 0h | Priority Based Flow Control Global Outflow Usage Threshold for Pri 4 |
15-12 | PRI3 | R/W | 0h | Priority Based Flow Control Global Outflow Usage Threshold for Pri 3 |
11-8 | PRI2 | R/W | 0h | Priority Based Flow Control Global Outflow Usage Threshold for Pri 2 |
7-4 | PRI1 | R/W | 0h | Priority Based Flow Control Global Outflow Usage Threshold for Pri 1 |
3-0 | PRI0 | R/W | 0h | Priority Based Flow Control Global Outflow Usage Threshold for Pri 0 |
CPSW_TX_G_BUF_THRESH_SET_L_REG is shown in Figure 12-616 and described in Table 12-1162.
Return to Summary Table.
CPSW PFC Global Tx Buffer Threshold Set Low Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI3 | PRI2 | PRI1 | PRI0 | ||||||||||||||||||||||||||||
R/W-FFh | R/W-FFh | R/W-FFh | R/W-FFh | ||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | PRI3 | R/W | FFh | Priority Based Flow Control Global Buffer Usage Threshold for Priority 3 |
23-16 | PRI2 | R/W | FFh | Priority Based Flow Control Global Buffer Usage Threshold for Priority 2 |
15-8 | PRI1 | R/W | FFh | Priority Based Flow Control Global Buffer Usage Threshold for Priority 1 |
7-0 | PRI0 | R/W | FFh | Priority Based Flow Control Global Buffer Usage Threshold for Priority 0 |
CPSW_TX_G_BUF_THRESH_SET_H_REG is shown in Figure 12-617 and described in Table 12-1164.
Return to Summary Table.
CPSW PFC Global Tx Buffer Threshold Set High Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI7 | PRI6 | PRI5 | PRI4 | ||||||||||||||||||||||||||||
R/W-FFh | R/W-FFh | R/W-FFh | R/W-FFh | ||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | PRI7 | R/W | FFh | Priority Based Flow Control Global Buffer Usage Threshold for Priority 7 |
23-16 | PRI6 | R/W | FFh | Priority Based Flow Control Global Buffer Usage Threshold for Priority 6 |
15-8 | PRI5 | R/W | FFh | Priority Based Flow Control Global Buffer Usage Threshold for Priority 5 |
7-0 | PRI4 | R/W | FFh | Priority Based Flow Control Global Buffer Usage Threshold for Priority 4 |
CPSW_TX_G_BUF_THRESH_CLR_L_REG is shown in Figure 12-618 and described in Table 12-1166.
Return to Summary Table.
CPSW PFC Global Tx Buffer Threshold Clear Low Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI3 | PRI2 | PRI1 | PRI0 | ||||||||||||||||||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | PRI3 | R/W | 0h | Priority Based Flow Control Global Buffer Usage Threshold for Priority 3 |
23-16 | PRI2 | R/W | 0h | Priority Based Flow Control Global Buffer Usage Threshold for Priority 2 |
15-8 | PRI1 | R/W | 0h | Priority Based Flow Control Global Buffer Usage Threshold for Priority 1 |
7-0 | PRI0 | R/W | 0h | Priority Based Flow Control Global Buffer Usage Threshold for Priority 0 |
CPSW_TX_G_BUF_THRESH_CLR_H_REG is shown in Figure 12-619 and described in Table 12-1168.
Return to Summary Table.
CPSW PFC Global Tx Buffer Threshold Clear High Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI7 | PRI6 | PRI5 | PRI4 | ||||||||||||||||||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | PRI7 | R/W | 0h | Priority Based Flow Control Global Buffer Usage Threshold for Priority 7 |
23-16 | PRI6 | R/W | 0h | Priority Based Flow Control Global Buffer Usage Threshold for Priority 6 |
15-8 | PRI5 | R/W | 0h | Priority Based Flow Control Global Buffer Usage Threshold for Priority 5 |
7-0 | PRI4 | R/W | 0h | Priority Based Flow Control Global Buffer Usage Threshold for Priority 4 |
CPSW_VLAN_LTYPE_REG is shown in Figure 12-620 and described in Table 12-1170.
Return to Summary Table.
VLAN LTYPE Outer and Inner Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VLAN_LTYPE_OUTER | VLAN_LTYPE_INNER | ||||||||||||||||||||||||||||||
R/W-88A8h | R/W-8100h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | VLAN_LTYPE_OUTER | R/W | 88A8h | Outer VLAN LTYPE |
15-0 | VLAN_LTYPE_INNER | R/W | 8100h | Inner VLAN LTYPE |
CPSW_EST_TS_DOMAIN_REG is shown in Figure 12-621 and described in Table 12-1172.
Return to Summary Table.
Enhanced Scheduled Traffic Host Event Domain Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EST_TS_DOMAIN | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R/W | X | |
7-0 | EST_TS_DOMAIN | R/W | 0h | Enhanced Scheduled Traffic Host Event Domain. |
CPSW_TX_PRI0_MAXLEN_REG is shown in Figure 12-622 and described in Table 12-1174.
Return to Summary Table.
Priority 0 Maximum Transmit Packet Length Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0100h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_PRI0_MAXLEN | ||||||||||||||||||||||||||||||
R/W-X | R/W-7E8h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_PRI0_MAXLEN | R/W | 7E8h | Transmit Priority 0 Maximum Packet Length |
CPSW_TX_PRI1_MAXLEN_REG is shown in Figure 12-623 and described in Table 12-1176.
Return to Summary Table.
Priority 1 Maximum Transmit Packet Length Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0104h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_PRI1_MAXLEN | ||||||||||||||||||||||||||||||
R/W-X | R/W-7E8h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_PRI1_MAXLEN | R/W | 7E8h | Transmit Priority 1 Maximum Packet Length |
CPSW_TX_PRI2_MAXLEN_REG is shown in Figure 12-624 and described in Table 12-1178.
Return to Summary Table.
Priority 2 Maximum Transmit Packet Length Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0108h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_PRI2_MAXLEN | ||||||||||||||||||||||||||||||
R/W-X | R/W-7E8h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_PRI2_MAXLEN | R/W | 7E8h | Transmit Priority 2 Maximum Packet Length |
CPSW_TX_PRI3_MAXLEN_REG is shown in Figure 12-625 and described in Table 12-1180.
Return to Summary Table.
Priority 3 Maximum Transmit Packet Length Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 010Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_PRI3_MAXLEN | ||||||||||||||||||||||||||||||
R/W-X | R/W-7E8h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_PRI3_MAXLEN | R/W | 7E8h | Transmit Priority 3 Maximum Packet Length |
CPSW_TX_PRI4_MAXLEN_REG is shown in Figure 12-626 and described in Table 12-1182.
Return to Summary Table.
Priority 4 Maximum Transmit Packet Length Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0110h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_PRI4_MAXLEN | ||||||||||||||||||||||||||||||
R/W-X | R/W-7E8h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_PRI4_MAXLEN | R/W | 7E8h | Transmit Priority 4 Maximum Packet Length |
CPSW_TX_PRI5_MAXLEN_REG is shown in Figure 12-627 and described in Table 12-1184.
Return to Summary Table.
Priority 5 Maximum Transmit Packet Length Register.
Transmit Priority 5 Maximum LengthInstance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0114h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_PRI5_MAXLEN | ||||||||||||||||||||||||||||||
R/W-X | R/W-7E8h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_PRI5_MAXLEN | R/W | 7E8h | Transmit Priority 5 Maximum Packet Length |
CPSW_TX_PRI6_MAXLEN_REG is shown in Figure 12-628 and described in Table 12-1186.
Return to Summary Table.
Priority 6 Maximum Transmit Packet Length Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 0118h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_PRI6_MAXLEN | ||||||||||||||||||||||||||||||
R/W-X | R/W-7E8h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_PRI6_MAXLEN | R/W | 7E8h | Transmit Priority 6 Maximum Packet Length |
CPSW_TX_PRI7_MAXLEN_REG is shown in Figure 12-629 and described in Table 12-1188.
Return to Summary Table.
Priority 7 Maximum Transmit Packet Length Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 011Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_PRI7_MAXLEN | ||||||||||||||||||||||||||||||
R/W-X | R/W-7E8h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | TX_PRI7_MAXLEN | R/W | 7E8h | Transmit Priority 7 Maximum Packet Length |
CPSW_P0_CONTROL_REG is shown in Figure 12-630 and described in Table 12-1190.
Return to Summary Table.
CPPI Port 0 Control Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RX_REMAP_DSCP_V6 | RX_REMAP_DSCP_V4 | RX_REMAP_VLAN | ||||
R/W-X | R/W-0h | R/W-0h | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RX_ECC_ERR_EN | TX_ECC_ERR_EN | RESERVED | |||||
R/W-0h | R/W-0h | R/W-X | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DSCP_IPV6_EN | DSCP_IPV4_EN | RX_CHECKSUM_EN | ||||
R/W-X | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R/W | X | |
18 | RX_REMAP_DSCP_V6 | R/W | 0h | Port 0 receive remap thread to DSCP IPV6 priority. |
17 | RX_REMAP_DSCP_V4 | R/W | 0h | Port 0 receive remap thread to DSCP IPV6 priority. |
16 | RX_REMAP_VLAN | R/W | 0h | Port 0 receive remap thread to VLAN. |
15 | RX_ECC_ERR_EN | R/W | 0h | Port 0 receive ECC Error Enable |
14 | TX_ECC_ERR_EN | R/W | 0h | Port 0 transmit ECC Error Enable |
13-3 | RESERVED | R/W | X | |
2 | DSCP_IPV6_EN | R/W | 0h | Port 0 IPv6 DSCP enable |
1 | DSCP_IPV4_EN | R/W | 0h | Port 0 IPV4 DSCP enable |
0 | RX_CHECKSUM_EN | R/W | 0h | Port 0 Receive (port 0 ingress) Checksum Enable |
CPSW_P0_FLOW_ID_OFFSET_REG is shown in Figure 12-631 and described in Table 12-1192.
Return to Summary Table.
CPPI Port 0 Transmit FLOW ID Offset Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VALUE | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | VALUE | R/W | 0h | This value is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0 |
CPSW_P0_BLK_CNT_REG is shown in Figure 12-632 and described in Table 12-1194.
Return to Summary Table.
CPPI Port 0 FIFO Block Usage Count Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TX_BLK_CNT | ||||||
R-X | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_BLK_CNT | ||||||
R-X | R-1h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R | X | |
12-8 | TX_BLK_CNT | R | 0h | Port 0 Transmit Block Count Usage. |
7-6 | RESERVED | R | X | |
5-0 | RX_BLK_CNT | R | 1h | Port 0 Receive Block Count Usage. |
CPSW_P0_PORT_VLAN_REG is shown in Figure 12-633 and described in Table 12-1196.
Return to Summary Table.
CPPI Port 0 VLAN Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PORT_PRI | PORT_CFI | PORT_VID | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PORT_VID | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-13 | PORT_PRI | R/W | 0h | Port VLAN Priority |
12 | PORT_CFI | R/W | 0h | Port CFI bit |
11-0 | PORT_VID | R/W | 0h | Port VLAN ID |
CPSW_P0_TX_PRI_MAP_REG is shown in Figure 12-634 and described in Table 12-1198.
Return to Summary Table.
CPPI Port 0 Tx Header Pri to Switch Pri Mapping
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||
R/W-X | R/W-7h | R/W-X | R/W-6h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||
R/W-X | R/W-5h | R/W-X | R/W-4h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||
R/W-X | R/W-3h | R/W-X | R/W-2h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||
R/W-X | R/W-1h | R/W-X | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30-28 | PRI7 | R/W | 7h | Priority 7. |
27 | RESERVED | R/W | X | |
26-24 | PRI6 | R/W | 6h | Priority 6. |
23 | RESERVED | R/W | X | |
22-20 | PRI5 | R/W | 5h | Priority 5. |
19 | RESERVED | R/W | X | |
18-16 | PRI4 | R/W | 4h | Priority 4. |
15 | RESERVED | R/W | X | |
14-12 | PRI3 | R/W | 3h | Priority 3. |
11 | RESERVED | R/W | X | |
10-8 | PRI2 | R/W | 2h | Priority 2. |
7 | RESERVED | R/W | X | |
6-4 | PRI1 | R/W | 1h | Priority 1. |
3 | RESERVED | R/W | X | |
2-0 | PRI0 | R/W | 0h | Priority 0. |
CPSW_P0_PRI_CTL_REG is shown in Figure 12-635 and described in Table 12-1200.
Return to Summary Table.
CPPI Port 0 Priority Control Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 101Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RX_FLOW_PRI | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RX_PTYPE | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-X | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-16 | RX_FLOW_PRI | R/W | 0h | Receive Priority Based Flow Control Enable (per priority). |
15-9 | RESERVED | R/W | X | |
8 | RX_PTYPE | R/W | 0h | Receive Priority Type |
7-0 | RESERVED | R/W | X |
CPSW_P0_RX_PRI_MAP_REG is shown in Figure 12-636 and described in Table 12-1202.
Return to Summary Table.
CPPI Port 0 RX Pkt Pri to Header Pri Map.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||
R/W-X | R/W-7h | R/W-X | R/W-6h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||
R/W-X | R/W-5h | R/W-X | R/W-4h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||
R/W-X | R/W-3h | R/W-X | R/W-2h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||
R/W-X | R/W-1h | R/W-X | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30-28 | PRI7 | R/W | 7h | Priority 7. |
27 | RESERVED | R/W | X | |
26-24 | PRI6 | R/W | 6h | Priority 6. |
23 | RESERVED | R/W | X | |
22-20 | PRI5 | R/W | 5h | Priority 5. |
19 | RESERVED | R/W | X | |
18-16 | PRI4 | R/W | 4h | Priority 4. |
15 | RESERVED | R/W | X | |
14-12 | PRI3 | R/W | 3h | Priority 3. |
11 | RESERVED | R/W | X | |
10-8 | PRI2 | R/W | 2h | Priority 2. |
7 | RESERVED | R/W | X | |
6-4 | PRI1 | R/W | 1h | Priority 1. |
3 | RESERVED | R/W | X | |
2-0 | PRI0 | R/W | 0h | Priority 0. |
CPSW_P0_RX_MAXLEN_REG is shown in Figure 12-637 and described in Table 12-1204.
Return to Summary Table.
CPPI Port 0 Receive Frame Max Length.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_MAXLEN | ||||||||||||||||||||||||||||||
R/W-X | R/W-5EEh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | RX_MAXLEN | R/W | 5EEh | RX Maximum Frame Length. |
CPSW_P0_TX_BLKS_PRI_REG is shown in Figure 12-638 and described in Table 12-1206.
Return to Summary Table.
CPPI Port 0 Transmit Block Sub Per Priority Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI7 | PRI6 | PRI5 | PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | ||||||||||||||||||||||||
R/W-0h | R/W-1h | R/W-2h | R/W-4h | R/W-5h | R/W-6h | R/W-7h | R/W-8h | ||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | PRI7 | R/W | 0h | Port Transmit Blocks Priority 7 |
27-24 | PRI6 | R/W | 1h | Port Transmit Blocks Priority 6 |
23-20 | PRI5 | R/W | 2h | Port Transmit Blocks Priority 5 |
19-16 | PRI4 | R/W | 4h | Port Transmit Blocks Priority 4 |
15-12 | PRI3 | R/W | 5h | Port Transmit Blocks Priority 3 |
11-8 | PRI2 | R/W | 6h | Port Transmit Blocks Priority 2 |
7-4 | PRI1 | R/W | 7h | Port Transmit Blocks Priority 1 |
3-0 | PRI0 | R/W | 8h | Port Transmit Blocks Priority 0 |
CPSW_P0_IDLE2LPI_REG is shown in Figure 12-639 and described in Table 12-1208.
Return to Summary Table.
CPPI Port 0 EEE Idle to LPI Count Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-0 | COUNT | R/W | 0h | Port 0 EEE Idle to LPI counter load value. |
CPSW_P0_LPI2WAKE_REG is shown in Figure 12-640 and described in Table 12-1210.
Return to Summary Table.
CPPI Port 0 EEE LPI to Wakeup Count Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-0 | COUNT | R/W | 0h | Port 0 EEE LPI to wake counter load value. |
CPSW_P0_EEE_STATUS_REG is shown in Figure 12-641 and described in Table 12-1212.
Return to Summary Table.
CPPI Port 0 EEE Port Status Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_FIFO_EMPTY | RX_FIFO_EMPTY | TX_FIFO_HOLD | TX_WAKE | TX_LPI | RX_LPI | WAIT_IDLE2LPI |
R-X | R-1h | R-1h | R-0h | R-0h | R-0h | R-0h | R-0h |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | X | |
6 | TX_FIFO_EMPTY | R | 1h | Port 0 Transmit FIFO packet count zero. |
5 | RX_FIFO_EMPTY | R | 1h | Port 0 Receive FIFO packet count zero. |
4 | TX_FIFO_HOLD | R | 0h | Port 0 Transmit FIFO hold. |
3 | TX_WAKE | R | 0h | Port 0 Receive Wake Time. |
2 | TX_LPI | R | 0h | Port 0 LPI. |
1 | RX_LPI | R | 0h | Port 0 LPI. |
0 | WAIT_IDLE2LPI | R | 0h | Transmit Wait Idle to LPI. |
CPSW_P0_RX_PKTS_PRI_REG is shown in Figure 12-642 and described in Table 12-1214.
Return to Summary Table.
CPPI Port 0 Receive Packets Per Priority Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 103Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI7 | PRI6 | PRI5 | PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | ||||||||||||||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | PRI7 | R/W | 0h | Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 7 |
27-24 | PRI6 | R/W | 0h | Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 6 |
23-20 | PRI5 | R/W | 0h | Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 5 |
19-16 | PRI4 | R/W | 0h | Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 4 |
15-12 | PRI3 | R/W | 0h | Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 3 |
11-8 | PRI2 | R/W | 0h | Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 2 |
7-4 | PRI1 | R/W | 0h | Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 1 |
3-0 | PRI0 | R/W | 0h | Port 0 Receive (same as Port 1 Transmit) Packets Per Priority 0 |
CPSW_P0_RX_GAP_REG is shown in Figure 12-643 and described in Table 12-1216.
Return to Summary Table.
CPPI Port 0 Receive Gap Register.
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 104Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RX_GAP_CNT | ||||||||||||||
R/W-X | R/W-100h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_GAP_EN | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R/W | X | |
25-16 | RX_GAP_CNT | R/W | 100h | Receive Gap Count. |
15-8 | RESERVED | R/W | X | |
7-0 | RX_GAP_EN | R/W | 0h | Port 0 Receive Gap Enable |
CPSW_P0_FIFO_STATUS_REG is shown in Figure 12-644 and described in Table 12-1218.
Return to Summary Table.
Port 0 FIFO Status
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_PRI_ACTIVE | ||||||||||||||
R-X | R-0h | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | X | |
7-0 | TX_PRI_ACTIVE | R | 0h | Port 0 Transmit FIFO Priority Active. |
CPSW_P0_RX_DSCP_MAP_REG_y is shown in Figure 12-645 and described in Table 12-1220.
Return to Summary Table.
CPPI Port 0 Receive IPV4/IPV6 DSCP Map 0 to Map 7 Registers.
Offset = 00021120h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1120h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30-28 | PRI7 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority |
27 | RESERVED | R/W | X | |
26-24 | PRI6 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority |
23 | RESERVED | R/W | X | |
22-20 | PRI5 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority |
19 | RESERVED | R/W | X | |
18-16 | PRI4 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority |
15 | RESERVED | R/W | X | |
14-12 | PRI3 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority |
11 | RESERVED | R/W | X | |
10-8 | PRI2 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority |
7 | RESERVED | R/W | X | |
6-4 | PRI1 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority |
3 | RESERVED | R/W | X | |
2-0 | PRI0 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority |
CPSW_P0_PRI_CIR_REG_y is shown in Figure 12-646 and described in Table 12-1222.
Return to Summary Table.
CPPI Port 0 Rx Priority 0 to Priority 7 Committed Information Rate Registers.
Offset = 00021140h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1140h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI_CIR | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R/W | X | |
27-0 | PRI_CIR | R/W | 0h | Priority “y” Committed Information Rate Count Value |
CPSW_P0_PRI_EIR_REG_y is shown in Figure 12-647 and described in Table 12-1224.
Return to Summary Table.
CPPI Port 0 Rx Priority 0 to Priority 7 Excess Information Rate Registers.
Offset = 00021160h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1160h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI_EIR | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R/W | X | |
27-0 | PRI_EIR | R/W | 0h | Priority “y” Excess Information Rate Count Value |
CPSW_P0_TX_D_THRESH_SET_L_REG is shown in Figure 12-648 and described in Table 12-1226.
Return to Summary Table.
CPPI Port 0 Tx PFC Destination Threshold Set Low
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI3 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 3 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI2 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 2 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI1 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 1 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI0 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 0 |
CPSW_P0_TX_D_THRESH_SET_H_REG is shown in Figure 12-649 and described in Table 12-1228.
Return to Summary Table.
CPPI Port 0 Tx PFC Destination Threshold Set High
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1184h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI7 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 7 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI6 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 6 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI5 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 5 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI4 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 4 |
CPSW_P0_TX_D_THRESH_CLR_L_REG is shown in Figure 12-650 and described in Table 12-1230.
Return to Summary Table.
CPPI Port 0 Tx PFC Destination Threshold Clr Low
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1188h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI3 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 3 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI2 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 2 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI1 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 1 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI0 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 0 |
CPSW_P0_TX_D_THRESH_CLR_H_REG is shown in Figure 12-651 and described in Table 12-1232.
Return to Summary Table.
CPPI Port 0 Tx PFC Destination Threshold Clr High
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 118Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI7 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 7 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI6 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 6 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI5 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 5 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI4 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 4 |
CPSW_P0_TX_G_BUF_THRESH_SET_L_REG is shown in Figure 12-652 and described in Table 12-1234.
Return to Summary Table.
CPPI Port 0 Tx PFC Global Buffer Threshold Set Low
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1190h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI3 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 3 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI2 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 2 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI1 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 1 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI0 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 0 |
CPSW_P0_TX_G_BUF_THRESH_SET_H_REG is shown in Figure 12-653 and described in Table 12-1236.
Return to Summary Table.
CPPI Port 0 Tx PFC Global Buffer Threshold Set High
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1194h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI7 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 7 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI6 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 6 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI5 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 5 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI4 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 4 |
CPSW_P0_TX_G_BUF_THRESH_CLR_L_REG is shown in Figure 12-654 and described in Table 12-1238.
Return to Summary Table.
CPPI Port 0 Tx PFC Global Buffer Threshold Clr Low
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1198h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI3 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 3 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI2 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 2 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI1 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 1 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI0 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 0 |
CPSW_P0_TX_G_BUF_THRESH_CLR_H_REG is shown in Figure 12-655 and described in Table 12-1240.
Return to Summary Table.
CPPI Port 0 Tx PFC Global Buffer Threshold Clr High
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 119Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI7 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 7 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI6 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 6 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI5 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 5 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI4 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 4 |
CPSW_P0_SRC_ID_A_REG is shown in Figure 12-656 and described in Table 12-1242.
Return to Summary Table.
CPPI Port 0 CPPI Source ID A
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1300h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PORT1 | ||||||||||||||||||||||||||||||
R-0h | R/W-1h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved. |
7-0 | PORT1 | R/W | 1h | Port 1 CPPI Info Word0 Source ID Value. |
CPSW_P0_HOST_BLKS_PRI_REG is shown in Figure 12-657 and described in Table 12-1244.
Return to Summary Table.
CPPI Port 0 Host Blocks Priority
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 1320h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI7 | PRI6 | PRI5 | PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | ||||||||||||||||||||||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | PRI7 | R/W | 0h | Host Blocks Per Priority 7 |
27-24 | PRI6 | R/W | 0h | Host Blocks Per Priority 6 |
23-20 | PRI5 | R/W | 0h | Host Blocks Per Priority 5 |
19-16 | PRI4 | R/W | 0h | Host Blocks Per Priority 4 |
15-12 | PRI3 | R/W | 0h | Host Blocks Per Priority 3 |
11-8 | PRI2 | R/W | 0h | Host Blocks Per Priority 2 |
7-4 | PRI1 | R/W | 0h | Host Blocks Per Priority 1 |
3-0 | PRI0 | R/W | 0h | Host Blocks Per Priority 0 |
CPSW_PN_RESERVED_REG is shown in Figure 12-658 and described in Table 12-1246.
Return to Summary Table.
Reserved
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | RESERVED | R | 0h | Reserved register for memory map alignment |
CPSW_PN_CONTROL_REG is shown in Figure 12-659 and described in Table 12-1248.
Return to Summary Table.
Enet Port N Control
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | EST_PORT_EN | IET_PORT_EN | |||||
R/W-X | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RX_ECC_ERR_EN | TX_ECC_ERR_EN | RESERVED | TX_LPI_CLKSTOP_EN | RESERVED | |||
R/W-0h | R/W-0h | R/W-X | R/W-0h | R/W-X | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DSCP_IPV6_EN | DSCP_IPV4_EN | RESERVED | ||||
R/W-X | R/W-0h | R/W-0h | R/W-X | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R/W | X | |
17 | EST_PORT_EN | R/W | 0h | EST Port Enable. |
16 | IET_PORT_EN | R/W | 0h | Intersperced Express Traffic (IET) Port Enable. |
15 | RX_ECC_ERR_EN | R/W | 0h | Port N receive ECC Error Enable |
14 | TX_ECC_ERR_EN | R/W | 0h | Port N transmit ECC Error Enable |
13 | RESERVED | R/W | X | |
12 | TX_LPI_CLKSTOP_EN | R/W | 0h | Transmit LPI Clock Stop Enable. |
11-3 | RESERVED | R/W | X | |
2 | DSCP_IPV6_EN | R/W | 0h | IPV6 DSCP enable |
1 | DSCP_IPV4_EN | R/W | 0h | IPV4 DSCP enable |
0 | RESERVED | R/W | X |
CPSW_PN_MAX_BLKS_REG is shown in Figure 12-660 and described in Table 12-1250.
Return to Summary Table.
Enet Port N FIFO Max Blocks
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_MAX_BLKS | RX_MAX_BLKS | ||||||||||||||
R/W-10h | R/W-4h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-8 | TX_MAX_BLKS | R/W | 10h | Transmit Max Blocks. |
7-0 | RX_MAX_BLKS | R/W | 4h | Receive Max Blocks. |
CPSW_PN_BLK_CNT_REG is shown in Figure 12-661 and described in Table 12-1252.
Return to Summary Table.
Enet Port N FIFO Block Usage Count
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RX_BLK_CNT_P | ||||||
R-X | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TX_BLK_CNT | ||||||
R-X | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_BLK_CNT_E | ||||||
R-X | R-1h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R | X | |
21-16 | RX_BLK_CNT_P | R | 0h | Receive Express Block Count Usage. |
15-13 | RESERVED | R | X | |
12-8 | TX_BLK_CNT | R | 0h | Transmit Block Count Usage. |
7-6 | RESERVED | R | X | |
5-0 | RX_BLK_CNT_E | R | 1h | Receive Express Block Count Usage. |
CPSW_PN_PORT_VLAN_REG is shown in Figure 12-662 and described in Table 12-1254.
Return to Summary Table.
Enet Port N VLAN
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PORT_PRI | PORT_CFI | PORT_VID | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PORT_VID | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-13 | PORT_PRI | R/W | 0h | Port VLAN Priority |
12 | PORT_CFI | R/W | 0h | Port CFI bit |
11-0 | PORT_VID | R/W | 0h | Port VLAN ID |
CPSW_PN_TX_PRI_MAP_REG is shown in Figure 12-663 and described in Table 12-1256.
Return to Summary Table.
Enet Port N Tx Header Pri to Switch Pri Mapping
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||
R/W-X | R/W-7h | R/W-X | R/W-6h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||
R/W-X | R/W-5h | R/W-X | R/W-4h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||
R/W-X | R/W-3h | R/W-X | R/W-2h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||
R/W-X | R/W-1h | R/W-X | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30-28 | PRI7 | R/W | 7h | Priority 7. A packet header priority of 7h is given this switch queue pri. |
27 | RESERVED | R/W | X | |
26-24 | PRI6 | R/W | 6h | Priority 6. A packet header priority of 6h is given this switch queue pri. |
23 | RESERVED | R/W | X | |
22-20 | PRI5 | R/W | 5h | Priority 5. A packet header priority of 5h is given this switch queue pri. |
19 | RESERVED | R/W | X | |
18-16 | PRI4 | R/W | 4h | Priority 4. A packet header priority of 4h is given this switch queue pri. |
15 | RESERVED | R/W | X | |
14-12 | PRI3 | R/W | 3h | Priority 3. A packet header priority of 3h is given this switch queue pri. |
11 | RESERVED | R/W | X | |
10-8 | PRI2 | R/W | 2h | Priority 2. A packet header priority of 2h is given this switch queue pri. |
7 | RESERVED | R/W | X | |
6-4 | PRI1 | R/W | 1h | Priority 1. A packet header priority of 1h is given this switch queue pri. |
3 | RESERVED | R/W | X | |
2-0 | PRI0 | R/W | 0h | Priority 0. A packet header priority of 0h is given this switch queue pri. |
CPSW_PN_PRI_CTL_REG is shown in Figure 12-664 and described in Table 12-1258.
Return to Summary Table.
Enet Port N Priority Control
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 201Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TX_FLOW_PRI | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RX_FLOW_PRI | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TX_HOST_BLKS_REM | RESERVED | ||||||
R/W-9h | R/W-X | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | |||||||
R/W-X | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | TX_FLOW_PRI | R/W | 0h | Transmit Priority Based Flow Control Enable (per priority) |
23-16 | RX_FLOW_PRI | R/W | 0h | Receive Priority Based Flow Control Enable (per priority) |
15-12 | TX_HOST_BLKS_REM | R/W | 9h | Transmit FIFO Blocks that must be free before a non rate-limited CPPI Port 0 receive thread can begin sending a packet |
11-0 | RESERVED | R/W | X |
CPSW_PN_RX_PRI_MAP_REG is shown in Figure 12-665 and described in Table 12-1260.
Return to Summary Table.
Enet Port N RX Pkt Pri to Header Pri Map
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||
R/W-X | R/W-7h | R/W-X | R/W-6h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||
R/W-X | R/W-5h | R/W-X | R/W-4h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||
R/W-X | R/W-3h | R/W-X | R/W-2h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||
R/W-X | R/W-1h | R/W-X | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30-28 | PRI7 | R/W | 7h | Priority 7. |
27 | RESERVED | R/W | X | |
26-24 | PRI6 | R/W | 6h | Priority 6. |
23 | RESERVED | R/W | X | |
22-20 | PRI5 | R/W | 5h | Priority 5. |
19 | RESERVED | R/W | X | |
18-16 | PRI4 | R/W | 4h | Priority 4. |
15 | RESERVED | R/W | X | |
14-12 | PRI3 | R/W | 3h | Priority 3. |
11 | RESERVED | R/W | X | |
10-8 | PRI2 | R/W | 2h | Priority 2. |
7 | RESERVED | R/W | X | |
6-4 | PRI1 | R/W | 1h | Priority 1. |
3 | RESERVED | R/W | X | |
2-0 | PRI0 | R/W | 0h | Priority 0. |
CPSW_PN_RX_MAXLEN_REG is shown in Figure 12-666 and described in Table 12-1262.
Return to Summary Table.
Enet Port N Receive Frame Max Length
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_MAXLEN | ||||||||||||||||||||||||||||||
R/W-X | R/W-5EEh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-14 | RESERVED | R/W | X | |
13-0 | RX_MAXLEN | R/W | 5EEh | RX Maximum Frame Length. |
CPSW_PN_TX_BLKS_PRI_REG is shown in Figure 12-667 and described in Table 12-1264.
Return to Summary Table.
Enet Port N Transmit Block Sub Per Priority
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PRI7 | PRI6 | PRI5 | PRI4 | PRI3 | PRI2 | PRI1 | PRI0 | ||||||||||||||||||||||||
R/W-0h | R/W-1h | R/W-2h | R/W-4h | R/W-5h | R/W-6h | R/W-7h | R/W-8h | ||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | PRI7 | R/W | 0h | Transmit Blocks Per Priority (subtract value) 7 |
27-24 | PRI6 | R/W | 1h | Transmit Blocks Per Priority (subtract value) 6 |
23-20 | PRI5 | R/W | 2h | Transmit Blocks Per Priority (subtract value) 5 |
19-16 | PRI4 | R/W | 4h | Transmit Blocks Per Priority (subtract value) 4 |
15-12 | PRI3 | R/W | 5h | Transmit Blocks Per Priority (subtract value) 3 |
11-8 | PRI2 | R/W | 6h | Transmit Blocks Per Priority (subtract value) 2 |
7-4 | PRI1 | R/W | 7h | Transmit Blocks Per Priority (subtract value) 1 |
3-0 | PRI0 | R/W | 8h | Transmit Blocks Per Priority (subtract value) 0 |
CPSW_PN_RX_FLOW_THRESH_REG is shown in Figure 12-668 and described in Table 12-1266.
Return to Summary Table.
Enet MAC Receive Flow Threshold in Receive Buffer Words
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 202Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-40h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R/W | X | |
8-0 | COUNT | R/W | 40h | Receive Flow Control Threshold in Words. |
CPSW_PN_IDLE2LPI_REG is shown in Figure 12-669 and described in Table 12-1268.
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Enet Port N EEE Idle to LPI counter
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-0 | COUNT | R/W | 0h | EEE Idle to LPI counter load value. |
CPSW_PN_LPI2WAKE_REG is shown in Figure 12-670 and described in Table 12-1270.
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Enet Port N EEE LPI to wake counter
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | X | |
23-0 | COUNT | R/W | 0h | EEE LPI to wake counter load value. |
CPSW_PN_EEE_STATUS_REG is shown in Figure 12-671 and described in Table 12-1272.
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Enet Port N EEE status
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_FIFO_EMPTY | RX_FIFO_EMPTY | TX_FIFO_HOLD | TX_WAKE | TX_LPI | RX_LPI | WAIT_IDLE2LPI |
R-X | R-1h | R-1h | R-0h | R-0h | R-0h | R-1h | R-0h |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-7 | RESERVED | R | X | |
6 | TX_FIFO_EMPTY | R | 1h | Port N Transmit FIFO packet count zero. |
5 | RX_FIFO_EMPTY | R | 1h | Port N Receive FIFO packet count zero. |
4 | TX_FIFO_HOLD | R | 0h | Port N Transmit FIFO hold. |
3 | TX_WAKE | R | 0h | Port N Receive Wake Time. |
2 | TX_LPI | R | 0h | Port N Transmit LPI. |
1 | RX_LPI | R | 1h | Port N Receive LPI. |
0 | WAIT_IDLE2LPI | R | 0h | Transmit Wait Idle to LPI. |
CPSW_PN_IET_CONTROL_REG is shown in Figure 12-672 and described in Table 12-1274.
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Enet Port N IET Control
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MAC_PREMPT | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | MAC_ADDFRAGSIZE | ||||||
R/W-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MAC_LINKFAIL | MAC_DISABLEVERIFY | MAC_HOLD | MAC_PENABLE | |||
R/W-0h | R/W-1h | R/W-0h | R/W-0h | R/W-0h | |||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | 0h | Reserved |
23-16 | MAC_PREMPT | R/W | 0h | Mac Preempt Queue – Indicates which transmit FIFO queues are sent to the preempt MAC. Bit 0 indicates queue zero, bit 1 queue 1 and so on. Packets will be sent to the preempt MAC only when MAC_PENABLE is set, and when MAC_VERIFIED (from CPSW_PN_IET_STATUS_REG) or MAC_DISABLEVERIFY is set, and when IET_PORT_EN is set. |
15-11 | RESERVED | R/W | 0h | Reserved |
10-8 | MAC_ADDFRAGSIZE | R/W | 0h | Mac Fragment Size – An integer in the range 0:7 indicating, as a multiple of 64, the minimum additional length for nonfinal mPackets. 0 = 64 1 = 128 2 = 192 3 = 256 4 = 320 5 = 384 6 = 448 7 = 512 |
7-4 | RESERVED | R/W | 0h | Reserved |
3 | MAC_LINKFAIL | R/W | 1h | Mac Link Fail – Link Fail Indicator to reset the verify state machine. This bit is reset high. Verify and response frames will be sent/allowed when this bit is cleared. |
2 | MAC_DISABLEVERIFY | R/W | 0h | Mac Disable Verify – Disables verification on the port when set. If this bit is set then packets will be sent to the preempt Mac when MAC_PENABLE is set (This is a forced mode with no IET verification). |
1 | MAC_HOLD | R/W | 0h | Mac Hold – Hold Preemption on the port. |
0 | MAC_PENABLE | R/W | 0h | Mac Preemption Enable – Port Preemption Enable. This takes effect only when IET_PORT_EN is set. |
CPSW_PN_IET_STATUS_REG is shown in Figure 12-673 and described in Table 12-1276.
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Enet Port N IET Status
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MAC_VERIFY_ERR | MAC_RESPOND_ERR | MAC_VERIFY_FAIL | MAC_VERIFIED | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | MAC_VERIFY_ERR | R | 0h | Mac Received Verify Packet with Errors – Set when a verify packet with errors is received. Cleared when MAC_PENABLE is cleared to zero. |
2 | MAC_RESPOND_ERR | R | 0h | Mac Received Respond Packet with Errors – Set when a respond packet with errors is received. Cleared when MAC_PENABLE is cleared to zero. |
1 | MAC_VERIFY_FAIL | R | 0h | Mac Verification Failed – Indication that verification was unsuccessful. |
0 | MAC_VERIFIED | R | 0h | Mac Verified – Indication that verification was successful. |
CPSW_PN_IET_VERIFY_REG is shown in Figure 12-674 and described in Table 12-1278.
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Enet Port N IET VERIFY
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MAC_VERIFY_CNT | ||||||||||||||||||||||||||||||
R/W-0h | R/W-001312D0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R/W | 0h | Reserved |
23-0 | MAC_VERIFY_CNT | R/W | 001312D0h | Mac Verify Timeout Count – The number of wireside clocks contained in the verify timeout counter. The default is 0x1312D0 (10ms at 125MHz in gig mode). |
CPSW_PN_FIFO_STATUS_REG is shown in Figure 12-675 and described in Table 12-1280.
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Enet Port N FIFO STATUS
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | EST_BUFACT | EST_ADD_ERR | EST_CNT_ERR | ||||
R-X | R-0h | R-0h | R-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TX_E_MAC_ALLOW | |||||||
R-FFh | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_PRI_ACTIVE | |||||||
R-0h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | X | |
18 | EST_BUFACT | R | 0h | EST RAM active buffer. |
17 | EST_ADD_ERR | R | 0h | EST Address Error. |
16 | EST_CNT_ERR | R | 0h | EST Fetch Count Error. |
15-8 | TX_E_MAC_ALLOW | R | FFh | EST transmit MAC allow. |
7-0 | TX_PRI_ACTIVE | R | 0h | EST Transmit Priority Active. |
CPSW_PN_EST_CONTROL_REG is shown in Figure 12-676 and described in Table 12-1282.
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Enet Port N EST CONTROL
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | EST_FILL_MARGIN | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
EST_FILL_MARGIN | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | EST_FILL_EN | ||||||
R/W-X | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EST_TS_PRI | EST_TS_ONEPRI | EST_TS_FIRST | EST_TS_EN | EST_BUFSEL | EST_ONEBUF | ||
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-26 | RESERVED | R/W | X | |
25-16 | EST_FILL_MARGIN | R/W | 0h | EST Fill Margin. |
15-9 | RESERVED | R/W | X | |
8 | EST_FILL_EN | R/W | 0h | EST Fill Enable. |
7-5 | EST_TS_PRI | R/W | 0h | EST Timestamp Express Priority. |
4 | EST_TS_ONEPRI | R/W | 0h | EST Timestamp One Express Priority. |
3 | EST_TS_FIRST | R/W | 0h | EST Timestamp First Express Packet only. |
2 | EST_TS_EN | R/W | 0h | EST Timestamp Enable. |
1 | EST_BUFSEL | R/W | 0h | EST Buffer Select. |
0 | EST_ONEBUF | R/W | 0h | EST One Fetch Buffer. |
CPSW_PN_RX_DSCP_MAP_REG_y is shown in Figure 12-677 and described in Table 12-1284.
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Enet Port N Receive IPV4/IPV6 DSCP Map 0 to Map 7 Registers.
Offset = 00022120h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2120h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30-28 | PRI7 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority |
27 | RESERVED | R/W | X | |
26-24 | PRI6 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority |
23 | RESERVED | R/W | X | |
22-20 | PRI5 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority |
19 | RESERVED | R/W | X | |
18-16 | PRI4 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority |
15 | RESERVED | R/W | X | |
14-12 | PRI3 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority |
11 | RESERVED | R/W | X | |
10-8 | PRI2 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority |
7 | RESERVED | R/W | X | |
6-4 | PRI1 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority |
3 | RESERVED | R/W | X | |
2-0 | PRI0 | R/W | 0h | A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority |
CPSW_PN_PRI_CIR_REG_y is shown in Figure 12-678 and described in Table 12-1286.
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Ethernet Port N Rx Priority 0 to Priority 7 Committed Information Rate Registers.
Offset = 00022140h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2140h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI_CIR | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R/W | X | |
27-0 | PRI_CIR | R/W | 0h | Priority “y” Committed Information Rate Count Value |
CPSW_PN_PRI_EIR_REG_y is shown in Figure 12-679 and described in Table 12-1288.
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Ethernet Port N Rx Priority 0 to Priority 7 Excess Information Rate Registers
Offset = 00022160h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2160h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI_EIR | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R/W | X | |
27-0 | PRI_EIR | R/W | 0h | Priority “y” Excess Information Rate Count Value |
CPSW_PN_TX_D_THRESH_SET_L_REG is shown in Figure 12-680 and described in Table 12-1290.
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Enet Port N Tx PFC Destination Threshold Set Low
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI3 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 3 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI2 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 2 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI1 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 1 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI0 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 0 |
CPSW_PN_TX_D_THRESH_SET_H_REG is shown in Figure 12-681 and described in Table 12-1292.
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Enet Port N Tx PFC Destination Threshold Set High
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2184h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI7 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 7 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI6 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 6 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI5 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 5 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI4 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 4 |
CPSW_PN_TX_D_THRESH_CLR_L_REG is shown in Figure 12-682 and described in Table 12-1294.
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Enet Port N Tx PFC Destination Threshold Clr Low
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2188h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI3 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 3 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI2 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 2 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI1 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 1 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI0 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 0 |
CPSW_PN_TX_D_THRESH_CLR_H_REG is shown in Figure 12-683 and described in Table 12-1296.
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Enet Port N Tx PFC Destination Threshold Clr High
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 218Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI7 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 7 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI6 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 6 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI5 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 5 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI4 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 4 |
CPSW_PN_TX_G_BUF_THRESH_SET_L_REG is shown in Figure 12-684 and described in Table 12-1298.
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Enet Port N Tx PFC Global Buffer Threshold Set Low
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2190h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI3 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 3 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI2 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 2 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI1 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 1 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI0 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 0 |
CPSW_PN_TX_G_BUF_THRESH_SET_H_REG is shown in Figure 12-685 and described in Table 12-1300.
Return to Summary Table.
Enet Port N Tx PFC Global Buffer Threshold Set High
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2194h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||||||||||
R/W-X | R/W-1Fh | R/W-X | R/W-1Fh | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI7 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 7 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI6 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 6 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI5 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 5 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI4 | R/W | 1Fh | Port Priority Based Flow Control Threshold Set Value for Priority 4 |
CPSW_PN_TX_G_BUF_THRESH_CLR_L_REG is shown in Figure 12-686 and described in Table 12-1302.
Return to Summary Table.
Enet Port N Tx PFC Global Buffer Threshold Clr Low
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2198h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI3 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 3 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI2 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 2 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI1 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 1 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI0 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 0 |
CPSW_PN_TX_G_BUF_THRESH_CLR_H_REG is shown in Figure 12-687 and described in Table 12-1304.
Return to Summary Table.
Enet Port N Tx PFC Global Buffer Threshold Clr High
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 219Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI7 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 7 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI6 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 6 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI5 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 5 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI4 | R/W | 0h | Port Priority Based Flow Control Threshold Clear Value for Priority 4 |
CPSW_PN_TX_D_OFLOW_ADDVAL_L_REG is shown in Figure 12-688 and described in Table 12-1306.
Return to Summary Table.
Enet Port N Tx Destination Out Flow Add Values Low
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2300h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI3 | RESERVED | PRI2 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI1 | RESERVED | PRI0 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI3 | R/W | 0h | Port PFC Destination Based Out Flow Add Value for Priority 3 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI2 | R/W | 0h | Port PFC Destination Based Out Flow Add Value for Priority 2 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI1 | R/W | 0h | Port PFC Destination Based Out Flow Add Value for Priority 1 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI0 | R/W | 0h | Port PFC Destination Based Out Flow Add Value for Priority 0 |
CPSW_PN_TX_D_OFLOW_ADDVAL_H_REG is shown in Figure 12-689 and described in Table 12-1308.
Return to Summary Table.
Enet Port N Tx Destination Out Flow Add Values High
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2304h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRI7 | RESERVED | PRI6 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRI5 | RESERVED | PRI4 | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | RESERVED | R/W | X | |
28-24 | PRI7 | R/W | 0h | Port PFC Destination Based Out Flow Add Value for Priority 7 |
23-21 | RESERVED | R/W | X | |
20-16 | PRI6 | R/W | 0h | Port PFC Destination Based Out Flow Add Value for Priority 6 |
15-13 | RESERVED | R/W | X | |
12-8 | PRI5 | R/W | 0h | Port PFC Destination Based Out Flow Add Value for Priority 5 |
7-5 | RESERVED | R/W | X | |
4-0 | PRI4 | R/W | 0h | Port PFC Destination Based Out Flow Add Value for Priority 4 |
CPSW_PN_SA_L_REG is shown in Figure 12-690 and described in Table 12-1310.
Return to Summary Table.
Enet Port N Tx Pause Frame Source Address Low
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2308h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MACSRCADDR_7_0 | MACSRCADDR_15_8 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-8 | MACSRCADDR_7_0 | R/W | 0h | Source Address Lower 8 bits (byte 0) |
7-0 | MACSRCADDR_15_8 | R/W | 0h | Source Address bits 15-8 (byte 1) |
CPSW_PN_SA_H_REG is shown in Figure 12-691 and described in Table 12-1312.
Return to Summary Table.
Enet Port N Tx Pause Frame Source Address High
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 230Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MACSRCADDR_23_16 | MACSRCADDR_31_24 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MACSRCADDR_39_32 | MACSRCADDR_47_40 | ||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | MACSRCADDR_23_16 | R/W | 0h | Source Address bits 23-16 (byte 2) |
23-16 | MACSRCADDR_31_24 | R/W | 0h | Source Address bits 31-24 (byte 3) |
15-8 | MACSRCADDR_39_32 | R/W | 0h | Source Address bits 39-32 (byte 4) |
7-0 | MACSRCADDR_47_40 | R/W | 0h | Source Address bits 47-40 (byte 5) |
CPSW_PN_TS_CTL_REG is shown in Figure 12-692 and described in Table 12-1314.
Return to Summary Table.
Enet Port N Time Sync Control
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2310h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TS_MSG_TYPE_EN | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TS_MSG_TYPE_EN | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | TS_TX_HOST_TS_EN | TS_TX_ANNEX_E_EN | TS_RX_ANNEX_E_EN | TS_LTYPE2_EN | |||
R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_TX_ANNEX_D_EN | TS_TX_VLAN_LTYPE2_EN | TS_TX_VLAN_LTYPE1_EN | TS_TX_ANNEX_F_EN | TS_RX_ANNEX_D_EN | TS_RX_VLAN_LTYPE2_EN | TS_RX_VLAN_LTYPE1_EN | TS_RX_ANNEX_F_EN |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | TS_MSG_TYPE_EN | R/W | 0h | Time Sync Message Type Enable. |
15-12 | RESERVED | R/W | X | |
11 | TS_TX_HOST_TS_EN | R/W | 0h | Time Sync Transmit Host Time Stamp Enable. |
10 | TS_TX_ANNEX_E_EN | R/W | 0h | Time Sync Transmit Annex E enable. |
9 | TS_RX_ANNEX_E_EN | R/W | 0h | Time Sync Receive Annex E enable. |
8 | TS_LTYPE2_EN | R/W | 0h | Time Sync LTYPE 2 enable (transmit and receive). |
7 | TS_TX_ANNEX_D_EN | R/W | 0h | Time Sync Transmit Annex D enable. |
6 | TS_TX_VLAN_LTYPE2_EN | R/W | 0h | Time Sync Transmit VLAN LTYPE 2 enable. |
5 | TS_TX_VLAN_LTYPE1_EN | R/W | 0h | Time Sync Transmit VLAN LTYPE 1 enable. |
4 | TS_TX_ANNEX_F_EN | R/W | 0h | Time Sync Transmit Annex F enable. |
3 | TS_RX_ANNEX_D_EN | R/W | 0h | Time Sync Receive Annex D enable. |
2 | TS_RX_VLAN_LTYPE2_EN | R/W | 0h | Time Sync Receive VLAN LTYPE 2 enable. |
1 | TS_RX_VLAN_LTYPE1_EN | R/W | 0h | Time Sync Receive VLAN LTYPE 1 enable. |
0 | TS_RX_ANNEX_F_EN | R/W | 0h | Time Sync Receive Annex F Enable. |
CPSW_PN_TS_SEQ_LTYPE_REG is shown in Figure 12-693 and described in Table 12-1316.
Return to Summary Table.
Enet Port N Time Sync LTYPE (and SEQ_ID_OFFSET)
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2314h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TS_SEQ_ID_OFFSET | ||||||||||||||
R/W-X | R/W-1Eh | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_LTYPE1 | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R/W | X | |
21-16 | TS_SEQ_ID_OFFSET | R/W | 1Eh | Time Sync Sequence ID Offset |
15-0 | TS_LTYPE1 | R/W | 0h | Time Sync LTYPE1 |
CPSW_PN_TS_VLAN_LTYPE_REG is shown in Figure 12-694 and described in Table 12-1318.
Return to Summary Table.
Enet Port N Time Sync VLAN2 and VLAN2
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2318h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_VLAN_LTYPE2 | TS_VLAN_LTYPE1 | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | TS_VLAN_LTYPE2 | R/W | 0h | Time Sync VLAN LTYPE2 |
15-0 | TS_VLAN_LTYPE1 | R/W | 0h | Time Sync VLAN LTYPE1 |
CPSW_PN_TS_CTL_LTYPE2_REG is shown in Figure 12-695 and described in Table 12-1320.
Return to Summary Table.
Enet Port N Time Sync Control and LTYPE 2
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 231Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | TS_UNI_EN | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TS_TTL_NONZERO | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_107 |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TS_LTYPE2 | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_LTYPE2 | |||||||
R/W-0h | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | X | |
24 | TS_UNI_EN | R/W | 0h | Time Sync Unicast Enable |
23 | TS_TTL_NONZERO | R/W | 0h | Time Sync Time to Live Non-zero Enable |
22 | TS_320 | R/W | 0h | Time Sync Destination IP Address 320 Enable |
21 | TS_319 | R/W | 0h | Time Sync Destination IP Address 319 Enable |
20 | TS_132 | R/W | 0h | Time Sync Destination IP Address 132 Enable |
19 | TS_131 | R/W | 0h | Time Sync Destination IP Address 131 Enable |
18 | TS_130 | R/W | 0h | Time Sync Destination IP Address 130 Enable |
17 | TS_129 | R/W | 0h | Time Sync Destination IP Address 129 Enable |
16 | TS_107 | R/W | 0h | Time Sync Destination IP Address 107 Enable |
15-0 | TS_LTYPE2 | R/W | 0h | Time Sync LTYPE2 |
CPSW_PN_TS_CTL2_REG is shown in Figure 12-696 and described in Table 12-1322.
Return to Summary Table.
Enet Port N Time Sync Control 2
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2320h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | TS_DOMAIN_OFFSET | ||||||||||||||
R/W-X | R/W-4h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TS_MCAST_TYPE_EN | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R/W | X | |
21-16 | TS_DOMAIN_OFFSET | R/W | 4h | Time Sync Domain Offset. |
15-0 | TS_MCAST_TYPE_EN | R/W | 0h | Time Sync Multicast Destination Address Type Enable. |
CPSW_PN_MAC_CONTROL_REG is shown in Figure 12-697 and described in Table 12-1324.
Return to Summary Table.
Enet Port N Mac Control
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2330h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RX_CMF_EN | ||||||
R/W-X | R/W-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RX_CSF_EN | RX_CEF_EN | TX_SHORT_GAP_LIM_EN | EXT_TX_FLOW_EN | EXT_RX_FLOW_EN | CTL_EN | GIG_FORCE | IFCTL_B |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
IFCTL_A | RESERVED | CRC_TYPE | CMD_IDLE | TX_SHORT_GAP_ENABLE | RESERVED | ||
R/W-0h | R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-X | ||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GIG | TX_PACE | GMII_EN | TX_FLOW_EN | RX_FLOW_EN | MTEST | LOOPBACK | FULLDUPLEX |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | X | |
24 | RX_CMF_EN | R/W | 0h | RX Copy MAC Control Frames Enable. |
23 | RX_CSF_EN | R/W | 0h | RX Copy Short Frames Enable. |
22 | RX_CEF_EN | R/W | 0h | RX Copy Error Frames Enable. |
21 | TX_SHORT_GAP_LIM_EN | R/W | 0h | Transmit Short Gap Limit Enable |
20 | EXT_TX_FLOW_EN | R/W | 0h | External Transmit Flow Control Enable. |
19 | EXT_RX_FLOW_EN | R/W | 0h | External Receive Flow Control Enable. |
18 | CTL_EN | R/W | 0h | External Control Enable. |
17 | GIG_FORCE | R/W | 0h | Gigabit Mode Force. |
16 | IFCTL_B | R/W | 0h | Interface Control B - Not used. |
15 | IFCTL_A | R/W | 0h |
Interface Control A - Determines the RMII link speed 0h = 10Mbps 1h = 100Mbps |
14-13 | RESERVED | R/W | X | |
12 | CRC_TYPE | R/W | 0h | Port CRC Type |
11 | CMD_IDLE | R/W | 0h | Command Idle |
10 | TX_SHORT_GAP_ENABLE | R/W | 0h | Transmit Short Gap Enable |
9-8 | RESERVED | R/W | X | |
7 | GIG | R/W | 0h | Gigabit Mode. |
6 | TX_PACE | R/W | 0h | Transmit Pacing Enable |
5 | GMII_EN | R/W | 0h | GMII Enable. |
4 | TX_FLOW_EN | R/W | 0h | Transmit Flow Control Enable. |
3 | RX_FLOW_EN | R/W | 0h | Receive Flow Control Enable. |
2 | MTEST | R/W | 0h | Manufacturing Test mode. |
1 | LOOPBACK | R/W | 0h | Loop Back Mode. |
0 | FULLDUPLEX | R/W | 0h | Full Duplex mode. |
CPSW_PN_MAC_STATUS_REG is shown in Figure 12-698 and described in Table 12-1326.
Return to Summary Table.
Enet Port N Mac Status
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2334h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
IDLE | E_IDLE | P_IDLE | TX_IDLE | TORF | TORF_PRI | ||
R-1h | R-1h | R-1h | R-1h | R-0h | R-0h | ||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
TX_PFC_FLOW_ACT | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RX_PFC_FLOW_ACT | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXT_RX_FLOW_EN | EXT_TX_FLOW_EN | EXT_GIG | EXT_FULLDUPLEX | RESERVED | RX_FLOW_ACT | TX_FLOW_ACT |
R-X | R-0h | R-0h | R-0h | R-0h | R-X | R-0h | R-0h |
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | IDLE | R | 1h | Enet IDLE. |
30 | E_IDLE | R | 1h | Express MAC is Idle. |
29 | P_IDLE | R | 1h | Prempt MAC is Idle. |
28 | TX_IDLE | R | 1h | Mac Transmit Idle. |
27 | TORF | R | 0h | Top of receive FIFO flow control trigger occurred. |
26-24 | TORF_PRI | R | 0h | The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear. |
23-16 | TX_PFC_FLOW_ACT | R | 0h | Transmit Priority Based Flow Control Active (priority 7 down to 0) |
15-8 | RX_PFC_FLOW_ACT | R | 0h | Receive Priority Based Flow Control Active (priority 7 down to 0) |
7 | RESERVED | R | X | |
6 | EXT_RX_FLOW_EN | R | 0h | External Receive Flow Control Enable. |
5 | EXT_TX_FLOW_EN | R | 0h | External Transmit Flow Control Enable. |
4 | EXT_GIG | R | 0h | External GIG. |
3 | EXT_FULLDUPLEX | R | 0h | External Fullduplex. |
2 | RESERVED | R | X | |
1 | RX_FLOW_ACT | R | 0h | Receive Flow Control Active. |
0 | TX_FLOW_ACT | R | 0h | Transmit Flow Control Active. |
CPSW_PN_MAC_SOFT_RESET_REG is shown in Figure 12-699 and described in Table 12-1328.
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Enet Port N Mac Soft Reset
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2338h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT_RESET | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | SOFT_RESET | R/W | 0h | Software reset. NOTE: If this bit is set CPSW_PN_RX_MAXLEN_REG,CPSW_PN_RX_PRI_MAP_REG, CPSW_PN_MAC_TX_GAP_REG, CPSW_PN_INTERVLAN_OPX_POINTER_REG, CPSW_PN_INTERVLAN_OPX_A_REG, CPSW_PN_INTERVLAN_OPX_B_REG, CPSW_PN_INTERVLAN_OPX_C_REG, CPSW_PN_INTERVLAN_OPX_D_REG will be reset to default value. |
CPSW_PN_MAC_BOFFTEST_REG is shown in Figure 12-700 and described in Table 12-1330.
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Enet Port N Mac Backoff Test
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 233Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | PACEVAL | RNDNUM | |||||
R/W-X | R/W-0h | R/W-0h | |||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RNDNUM | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
COLL_COUNT | RESERVED | TX_BACKOFF | |||||
R-0h | R/W-X | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TX_BACKOFF | |||||||
R-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30-26 | PACEVAL | R/W | 0h | Pacing Current Value. |
25-16 | RNDNUM | R/W | 0h | Backoff Random Number Generator. |
15-12 | COLL_COUNT | R | 0h | Collision Count. |
11-10 | RESERVED | R/W | X | |
9-0 | TX_BACKOFF | R | 0h | Backoff Count. |
CPSW_PN_MAC_RX_PAUSETIMER_REG is shown in Figure 12-701 and described in Table 12-1332.
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Enet Port N 802.3 Receive Pause Timer
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2340h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_PAUSETIMER | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_PAUSETIMER | R/W | 0h | RX Pause Timer Value. |
CPSW_PN_MAC_RXN_PAUSETIMER_REG_y is shown in Figure 12-702 and described in Table 12-1334.
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Ethernet Port N PFC Priority 0 to Priority 7 Rx Pause Timer Registers.
Offset = 00022350h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2350h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RX_PAUSETIMER | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | RX_PAUSETIMER | R/W | 0h | Rx “y” Pause Timer Value. |
CPSW_PN_MAC_TX_PAUSETIMER_REG is shown in Figure 12-703 and described in Table 12-1336.
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Enet Port N 802.3 Tx Pause Timer
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2370h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_PAUSETIMER | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_PAUSETIMER | R/W | 0h | 802.3 Tx Pause Timer Value. |
CPSW_PN_MAC_TXN_PAUSETIMER_REG_y is shown in Figure 12-704 and described in Table 12-1338.
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Ethernet Port N PFC Priority 0 to Priority 7 Tx Pause Timer Registers.
Offset = 00022380h + (y * 4h); where y = 0h to 7h
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 2380h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_PAUSETIMER | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_PAUSETIMER | R/W | 0h | PFC Tx ”y” Pause Timer Value. |
CPSW_PN_MAC_EMCONTROL_REG is shown in Figure 12-705 and described in Table 12-1340.
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Enet Port N Emulation Control
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 23A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT | FREE | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | SOFT | R/W | 0h | Emulation Soft Bit |
0 | FREE | R/W | 0h | Emulation Free Bit |
CPSW_PN_MAC_TX_GAP_REG is shown in Figure 12-706 and described in Table 12-1342.
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Enet Port N Tx Inter Packet Gap
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 23A4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TX_GAP | ||||||||||||||||||||||||||||||
R/W-X | R/W-Ch | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TX_GAP | R/W | Ch | Transmit Inter-Packet Gap |
CPSW_PN_INTERVLAN_OPX_POINTER_REG is shown in Figure 12-707 and described in Table 12-1344.
Return to Summary Table.
Enet Port N Tx Egress InterVLAN Operation Pointer
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 23ACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTERVLAN_OPX_POINTER | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | X | |
2-0 | INTERVLAN_OPX_POINTER | R/W | 0h | Egress InterVLAN Operation Pointer |
CPSW_PN_INTERVLAN_OPX_A_REG is shown in Figure 12-708 and described in Table 12-1346.
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Enet Port N Tx Egress InterVLAN A
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 23B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTERVLAN_OPX_A | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | DA[23:16] | R/W | 0h | Destination Address bits 23-16 – DA byte 4 on wire. |
23-16 | DA[31:24] | R/W | 0h | Destination Address bits 31-24 – DA byte 3 on wire. |
15-8 | DA[39:32] | R/W | 0h | Destination Address bits 39-32 – DA byte 2 on wire. |
7-0 | DA[47:40] | R/W | 0h | Destination Address bits 47-40 – DA byte 1 on wire. |
CPSW_PN_INTERVLAN_OPX_B_REG is shown in Figure 12-709 and described in Table 12-1348.
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Enet Port N Tx Egress InterVLAN B
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 23B4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTERVLAN_OPX_B | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | SA[39:32] | R/W | 0h | Source Address bits 39-32 – SA byte 2 on wire. |
23-16 | SA[47:40] | R/W | 0h | Source Address bits 47-40 – SA byte 1 on wire. |
15-8 | DA[7:0] | R/W | 0h | Destination Address bits 7-0 – DA byte 6 on wire. |
7-0 | DA[15:8] | R/W | 0h | Destination Address bits 15-8 – DA byte 5 on wire. |
CPSW_PN_INTERVLAN_OPX_C_REG is shown in Figure 12-710 and described in Table 12-1350.
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Enet Port N Tx Egress InterVLAN C
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 23B8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
INTERVLAN_OPX_C | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | SA[7:0] | R/W | 0h | Source Address bits 7-0 – SA byte 6 on wire. |
23-16 | SA[15:8] | R/W | 0h | Source Address bits 15-8 – SA byte 5 on wire. |
15-8 | SA[23:16] | R/W | 0h | Source Address bits 23-16 – SA byte 4 on wire. |
7-0 | SA[31:24] | R/W | 0h | Source Address bits 31-24 – SA byte 3 on wire. |
CPSW_PN_INTERVLAN_OPX_D_REG is shown in Figure 12-711 and described in Table 12-1352.
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Enet Port N Tx Egress InterVLAN D
Instance | Physical Address |
---|---|
MCU_CPSW0_NUSS_CONTROL | 4602 23BCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTERVLAN_OPX_D | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | INTERVLAN_OPX_D | R/W | 0h | Egress InterVLAN D |