SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-3620 lists the memory-mapped registers for the PCIE_USER_CFG. All register offset addresses not listed in Table 12-3620 should be considered as reserved locations and the register contents should not be modified.
PCIe Gen4x2 user config registers. Local host access only.
Instance | Base Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7000h |
PCIE_USER_REVID is shown in Figure 12-1834 and described in Table 12-3622.
Return to Summary Table.
Module ID register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
MODID | |||||||||||||||
R-6814h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-8h | R-1h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MODID | R | 6814h | Module ID field |
15-11 | REVRTL | R | 8h | RTL revision. |
10-8 | REVMAJ | R | 1h | Major revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | REVMIN | R | 0h | Minor revision |
PCIE_USER_CMD_STATUS is shown in Figure 12-1835 and described in Table 12-3624.
Return to Summary Table.
Command Status register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | LINK_TRAINING_ENABLE | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | LINK_TRAINING_ENABLE | R/W | 0h | This bit must be set to 1 to enable the LTSSM to bring up the link. |
PCIE_USER_RSTCMD is shown in Figure 12-1836 and described in Table 12-3626.
Return to Summary Table.
Reset Command and Status register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INIT_HOT_RESET | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | INIT_HOT_RESET | R/W | 0h | When this bit is set to 1'b1 in the RP mode, the core initiates a Hot Reset sequence on the PCIe link. |
PCIE_USER_INITCFG is shown in Figure 12-1837 and described in Table 12-3628.
Return to Summary Table.
Initialization configuration register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 700Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CONFIG_ENABLE | ||||||
R/W-X | R/W-1h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
VC_COUNT | MAX_EVAL_ITERATION | ||||||
R/W-3h | R/W-8h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
MAX_EVAL_ITERATION | BYPASS_PHASE23 | BYPASS_REMOTE_TX_EQUALIZATION | SUPPORTED_PRESET | ||||
R/W-8h | R/W-0h | R/W-0h | R/W-7FFh | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SUPPORTED_PRESET | DISABLE_GEN3_DC_BALANCE | SRIS_ENABLE | |||||
R/W-7FFh | R/W-0h | R/W-1h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R/W | X | |
24 | CONFIG_ENABLE | R/W | 1h | When this bit is set to 0 in the EP mode, the Controller will generate a CRS Completion in response to Configuration Requests. |
23-22 | VC_COUNT | R/W | 3h | Number of VCs configured. |
21-15 | MAX_EVAL_ITERATION | R/W | 8h | Denotes the maximum number of iterations to be performed during the DirectionChange Feedback Link Equalization in case the direction change feedback does not converge to 00. |
14 | BYPASS_PHASE23 | R/W | 0h | This MMR should be programmed during system boot or initialization. |
13 | BYPASS_REMOTE_TX_EQUALIZATION | R/W | 0h | This MMR should be programmed during system boot or initialization. |
12-2 | SUPPORTED_PRESET | R/W | 7FFh | This MMR should be programmed during system boot or initialization. |
1 | DISABLE_GEN3_DC_BALANCE | R/W | 0h | This bit it is used to disable the transmission of special DC Balance symbols in TS1 training sequences for improving the DC balance of the bit stream at 8.0 GT/s or higher speed. |
0 | SRIS_ENABLE | R/W | 1h | Should be set as per the System Reference Clocking Implementation. |
PCIE_USER_PMCMD is shown in Figure 12-1838 and described in Table 12-3630.
Return to Summary Table.
Power Management command register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | POWER_STATE_CHANGE_ACK | CLIENT_REQ_EXIT_L1_SUBSTATE | CLIENT_REQ_EXIT_L1 | ||||
R/W-X | R/W-0h | R/W-0h | R/W-0h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | X | |
2 | POWER_STATE_CHANGE_ACK | R/W | 0h | Software must assert this bit for a minimum of one cycle in response to the assertion of POWER_STATE_CHANGE_INTERRUPT, when it is ready to transition to the low-power state requested by the configuration write request. |
1 | CLIENT_REQ_EXIT_L1_SUBSTATE | R/W | 0h | Client logic can trigger an explicit L |
0 | CLIENT_REQ_EXIT_L1 | R/W | 0h | Client logic can trigger an explicit L1 exit by setting this bit. |
PCIE_USER_LINKSTATUS is shown in Figure 12-1839 and described in Table 12-3632.
Return to Summary Table.
Link Status register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | LTSSM_STATE | ||||||
R-X | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
POWER_STATE_CHANGE_FUNCTION_NUM | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | L1_PM_SUBSTATE | LINK_POWER_STATE | |||||
R-X | R-0h | R-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NEGOTIATED_SPEED | NEGOTIATED_LINK_WIDTH | LINK_STATUS | ||||
R-X | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | RESERVED | R | X | |
29-24 | LTSSM_STATE | R | 0h | Current state of the Link Training and Status
State Machine within the core. |
23-16 | POWER_STATE_CHANGE_FUNCTION_NUM | R | 0h | Function number of the function for which a power state change occurred. |
15 | RESERVED | R | X | |
14-12 | L1_PM_SUBSTATE | R | 0h | This register provides the current state of the L1 PM substates state machine. |
11-8 | LINK_POWER_STATE | R | 0h | Current power state of the PCIe link. |
7-6 | RESERVED | R | X | |
5-4 | NEGOTIATED_SPEED | R | 0h | Current operating speed of the link is as follows: |
3-2 | NEGOTIATED_LINK_WIDTH | R | 0h | Current link width are as follows: |
1-0 | LINK_STATUS | R | 0h | Status of the PCI Express link. |
PCIE_USER_LEGACY_INTR_SET is shown in Figure 12-1840 and described in Table 12-3634.
Return to Summary Table.
Legacy interrupt set register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7018h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INTD_IN | INTC_IN | INTB_IN | INTA_IN | |||
R/W-X | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3 | INTD_IN | R/W | 0h | When the core is configured as EP, this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express. |
2 | INTC_IN | R/W | 0h | When the core is configured as EP, this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express. |
1 | INTB_IN | R/W | 0h | When the core is configured as EP, this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express. |
0 | INTA_IN | R/W | 0h | When the core is configured as EP, this bit is used by the client application to signal an interrupt from any of its PCI Functions to the RP using the Legacy PCI Express Interrupt Delivery mechanism of PCI Express. |
PCIE_USER_LEGACY_INT_PENDING is shown in Figure 12-1841 and described in Table 12-3636.
Return to Summary Table.
Legacy interrupt pending set register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 701Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | INT_ACK | ||||||
R-0h | R/W1C-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | INT_PENDING_STATUS | ||||||
R-0h | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-9 | RESERVED | R | X | Reserved |
8 | INT_ACK | R/W1C | 0h | When using legacy interrupts, this bit indicates that the core has sent an INTx Assert or Deassert message in response to a change in the state of one of the INTx inputs. |
7-6 | RESERVED | R | X | Reserved |
5-0 | INT_PENDING_STATUS | R/W | 0h | When using legacy interrupts, this input is used to indicate the interrupt pending status of the Physical Functions. The bit i must be set when an interrupt is pending in Function i. |
PCIE_USER_MSI_STAT is shown in Figure 12-1842 and described in Table 12-3638.
Return to Summary Table.
MSI status register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MSI_ENABLE | ||||||||||||||
R-X | R-0h | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | X | |
5-0 | MSI_ENABLE | R | 0h | When the core is configured in the EndPoint mode to support MSI interrupts, this output is driven by the MSI Enable bit of the MSI Control Registers of the Physical Functions. |
PCIE_USER_MSI_VECTOR is shown in Figure 12-1843 and described in Table 12-3640.
Return to Summary Table.
MSI vector register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7024h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MSI_VECTOR_COUNT | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R | X | |
17-0 | MSI_VECTOR_COUNT | R | 0h | When the core is configured in the EndPoint mode to support MSI interrupts, these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Physical Functions. |
PCIE_USER_MSI_MASK_PF0 is shown in Figure 12-1844 and described in Table 12-3642.
Return to Summary Table.
PF0 MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7028h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_PF0 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_PF0 | R | 0h | These bits provide the setting of the MSI Mask registers of the Physical Function0. |
PCIE_USER_MSI_MASK_PF1 is shown in Figure 12-1845 and described in Table 12-3644.
Return to Summary Table.
PF1 MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 702Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_PF1 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_PF1 | R | 0h | These bits provide the setting of the MSI Mask registers of the Physical Function1. |
PCIE_USER_MSI_MASK_PF2 is shown in Figure 12-1846 and described in Table 12-3646.
Return to Summary Table.
PF2 MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_PF2 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_PF2 | R | 0h | These bits provide the setting of the MSI Mask registers of the Physical Function2. |
PCIE_USER_MSI_MASK_PF3 is shown in Figure 12-1847 and described in Table 12-3648.
Return to Summary Table.
PF3 MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_PF3 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_PF3 | R | 0h | These bits provide the setting of the MSI Mask registers of the Physical Function3. |
PCIE_USER_MSI_MASK_PF4 is shown in Figure 12-1848 and described in Table 12-3650.
Return to Summary Table.
PF4 MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_PF4 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_PF4 | R | 0h | These bits provide the setting of the MSI Mask registers of the Physical Function4. |
PCIE_USER_MSI_MASK_PF5 is shown in Figure 12-1849 and described in Table 12-3652.
Return to Summary Table.
PF5 MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 703Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_PF5 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_PF5 | R | 0h | These bits provide the setting of the MSI Mask registers of the Physical Function5. |
PCIE_USER_MSI_PENDING_STATUS_PF0 is shown in Figure 12-1850 and described in Table 12-3654.
Return to Summary Table.
PF0 MSI pending status input register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_PENDING_STATUS_PF0 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_PENDING_STATUS_PF0 | R/W | 0h | These inputs provide the status of the MSI pending interrupts for the Physical Function0 from the client to the core. |
PCIE_USER_MSI_PENDING_STATUS_PF1 is shown in Figure 12-1851 and described in Table 12-3656.
Return to Summary Table.
PF1 MSI pending status input register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7044h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_PENDING_STATUS_PF1 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_PENDING_STATUS_PF1 | R/W | 0h | These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core, if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management,the setting of this register determines the value read from the MSI Pending Bits Register PF1. |
PCIE_USER_MSI_PENDING_STATUS_PF2 is shown in Figure 12-1852 and described in Table 12-3658.
Return to Summary Table.
PF2 MSI pending status input register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7048h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_PENDING_STATUS_PF2 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_PENDING_STATUS_PF2 | R/W | 0h | These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core, if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management,the setting of this register determines the value read from the MSI Pending Bits Register PF2. |
PCIE_USER_MSI_PENDING_STATUS_PF3 is shown in Figure 12-1853 and described in Table 12-3660.
Return to Summary Table.
PF3 MSI pending status input register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 704Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_PENDING_STATUS_PF3 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_PENDING_STATUS_PF3 | R/W | 0h | These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core, if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management,the setting of this register determines the value read from the MSI Pending Bits Register PF3. |
PCIE_USER_MSI_PENDING_STATUS_PF4 is shown in Figure 12-1854 and described in Table 12-3662.
Return to Summary Table.
PF4 MSI pending status input register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_PENDING_STATUS_PF4 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_PENDING_STATUS_PF4 | R/W | 0h | These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core, if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management,the setting of this register determines the value read from the MSI Pending Bits Register PF4. |
PCIE_USER_MSI_PENDING_STATUS_PF5 is shown in Figure 12-1855 and described in Table 12-3664.
Return to Summary Table.
PF5 MSI pending status input register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7054h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_PENDING_STATUS_PF5 | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_PENDING_STATUS_PF5 | R/W | 0h | These inputs provide the status of the MSI pending interrupts for the Physical Function1 from the client to the core, if MSI Pending Status In Mode Select is set to 1 in the Debug Mux Control 2 register in local management,the setting of this register determines the value read from the MSI Pending Bits Register PF5. |
PCIE_USER_MSI_STAT_VF is shown in Figure 12-1856 and described in Table 12-3666.
Return to Summary Table.
MSI_VF status register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7058h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VF_MSI_ENABLE | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | VF_MSI_ENABLE | R | 0h | When the core is configured in the EndPoint mode to support MSI interrupts, this output is driven by the MSI Enable bit of the MSI Control Registers of the Virtual Functions. |
PCIE_USER_MSI_VECTOR0_VF is shown in Figure 12-1857 and described in Table 12-3668.
Return to Summary Table.
MSI_VF vector count register0
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 705Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VF_MSI_VECTOR_COUNT0 | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | X | |
23-0 | VF_MSI_VECTOR_COUNT0 | R | 0h | When the core is configured in the Endpoint mode to support MSI interrupts, these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function0 thru Virtual Function7. |
PCIE_USER_MSI_VECTOR1_VF is shown in Figure 12-1858 and described in Table 12-3670.
Return to Summary Table.
MSI_VF vector count register1
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VF_MSI_VECTOR_COUNT1 | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | RESERVED | R | X | |
23-0 | VF_MSI_VECTOR_COUNT1 | R | 0h | When the core is configured in the Endpoint mode to support MSI interrupts, these outputs are driven by the Multiple Message Enable bits of the MSI Control Registers associated with Virtual Function8 thru Virtual Function15. |
PCIE_USER_MSI_MASK_VF0 is shown in Figure 12-1859 and described in Table 12-3672.
Return to Summary Table.
VF0MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF0 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF0 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function0. |
PCIE_USER_MSI_MASK_VF1 is shown in Figure 12-1860 and described in Table 12-3674.
Return to Summary Table.
VF1MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7068h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF1 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF1 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function1. |
PCIE_USER_MSI_MASK_VF2 is shown in Figure 12-1861 and described in Table 12-3676.
Return to Summary Table.
VF2MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 706Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF2 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF2 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function2. |
PCIE_USER_MSI_MASK_VF3 is shown in Figure 12-1862 and described in Table 12-3678.
Return to Summary Table.
VF3MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7070h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF3 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF3 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function3. |
PCIE_USER_MSI_MASK_VF4 is shown in Figure 12-1863 and described in Table 12-3680.
Return to Summary Table.
VF4MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF4 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF4 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function4. |
PCIE_USER_MSI_MASK_VF5 is shown in Figure 12-1864 and described in Table 12-3682.
Return to Summary Table.
VF5MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7078h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF5 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF5 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function5. |
PCIE_USER_MSI_MASK_VF6 is shown in Figure 12-1865 and described in Table 12-3684.
Return to Summary Table.
VF6MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 707Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF6 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF6 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function6. |
PCIE_USER_MSI_MASK_VF7 is shown in Figure 12-1866 and described in Table 12-3686.
Return to Summary Table.
VF7MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF7 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF7 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function7. |
PCIE_USER_MSI_MASK_VF8 is shown in Figure 12-1867 and described in Table 12-3688.
Return to Summary Table.
VF8MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7084h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF8 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF8 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function8. |
PCIE_USER_MSI_MASK_VF9 is shown in Figure 12-1868 and described in Table 12-3690.
Return to Summary Table.
VF9MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7088h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF9 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF9 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function9. |
PCIE_USER_MSI_MASK_VF10 is shown in Figure 12-1869 and described in Table 12-3692.
Return to Summary Table.
VF10MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 708Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF10 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF10 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function10. |
PCIE_USER_MSI_MASK_VF11 is shown in Figure 12-1870 and described in Table 12-3694.
Return to Summary Table.
VF11MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7090h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF11 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF11 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function11. |
PCIE_USER_MSI_MASK_VF12 is shown in Figure 12-1871 and described in Table 12-3696.
Return to Summary Table.
VF12MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7094h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF12 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF12 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function12. |
PCIE_USER_MSI_MASK_VF13 is shown in Figure 12-1872 and described in Table 12-3698.
Return to Summary Table.
VF13MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 7098h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF13 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF13 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function13. |
PCIE_USER_MSI_MASK_VF14 is shown in Figure 12-1873 and described in Table 12-3700.
Return to Summary Table.
VF14MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 709Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF14 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF14 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function14. |
PCIE_USER_MSI_MASK_VF15 is shown in Figure 12-1874 and described in Table 12-3702.
Return to Summary Table.
VF15MSI mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 70A0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MSI_MASK_VF15 | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | MSI_MASK_VF15 | R | 0h | These bits provide the setting of the MSI Mask registers of the Virtual Function15. |
PCIE_USER_MSIX_STAT is shown in Figure 12-1875 and described in Table 12-3704.
Return to Summary Table.
MSIX status register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 70A4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MSIX_ENABLE | ||||||||||||||
R-X | R-0h | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | X | |
5-0 | MSIX_ENABLE | R | 0h | These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of Physical Functions.Bit0 represents the MSIX Enable for Physical Function0 and Bit1 represents the MSIX Enable for Physical Function 1 |
PCIE_USER_MSIX_MASK is shown in Figure 12-1876 and described in Table 12-3706.
Return to Summary Table.
MSIX mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 70A8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | MSIX_MASK | ||||||||||||||
R-X | R-0h | ||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | X | |
5-0 | MSIX_MASK | R | 0h | These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Physical Functions. |
PCIE_USER_MSIX_STAT_VF is shown in Figure 12-1877 and described in Table 12-3708.
Return to Summary Table.
Virtual Function MSIX status register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 70ACh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VF_MSIX_ENABLE | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | VF_MSIX_ENABLE | R | 0h | These bits reflect the states of the MSI-X Enable bits in the PCI configuration space of virtual Functions.Bit0 represents the MSIX Enable for Virtual Function0, Bit1 represents the MSIX Enable for Virtual Function 1 and so on |
PCIE_USER_MSIX_MASK_VF is shown in Figure 12-1878 and described in Table 12-3710.
Return to Summary Table.
Virtual Function MSIX mask register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 70B0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VF_MSIX_MASK | ||||||||||||||||||||||||||||||
R-X | R-0h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | X | |
15-0 | VF_MSIX_MASK | R | 0h | These bits reflect the states of the MSI-X Function Mask bits in the PCI configuration space of Virtual Functions. |
PCIE_USER_FLR_DONE is shown in Figure 12-1879 and described in Table 12-3712.
Return to Summary Table.
Physical Function-Level Reset Done register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 70B4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FLR_DONE | ||||||||||||||
W-X | W-0h | ||||||||||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | W | X | |
5-0 | FLR_DONE | W | 0h | These bits are connected to the PCIE_USER_FLR_DONE
bits on the PCIe controller core. |
PCIE_USER_VF_FLR_DONE is shown in Figure 12-1880 and described in Table 12-3714.
Return to Summary Table.
Virtual Function-Level Reset Done register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 70B8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VF_FLR_DONE | ||||||||||||||||||||||||||||||
W-X | W-0h | ||||||||||||||||||||||||||||||
LEGEND: W = Write Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | W | X | |
15-0 | VF_FLR_DONE | W | 0h | These bits are connected to the
PCIE_USER_VF_FLR_DONE bits on the PCIe controller core. |
PCIE_USER_PTM_CFG is shown in Figure 12-1881 and described in Table 12-3716.
Return to the Summary Table.
PTM Timestamp configuration register
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 70BCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | PTM_EP_TIMER_ADJ | ||||||
R-0h | R/W-1h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PTM_CLK_SEL | ||||||
R-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | X | Reserved |
10-8 | PTM_EP_TIMER_ADJ | R/W | 1h | PTM EP Timer tick adjust value. 1 will increment ptm_ep_timer by 1 each clock cycle, 2 will increment the timer by 2 .. 7 will increment the timer by 7. The adjust value should be set prior to enabling PTM operation in the PCIe controller. |
7 | RESERVED | R | X | Reserved |
6-0 | PTM_CLK_SEL | R/W | 0h | Select CPTS HW1 push input. 0 will select ptm_local_timer[0], 1 will select ptm_local_timer[1] ... 63 will select ptm_local_timer[63] and 64 will select ptm_local_timer_out_valid. The values 65 to 127 are unused. The PTM clock select bit should be set prior to enabling the PTM operation in the PCIe controller |
PCIE_USER_PTM_TIMER_LOW is shown in Figure 12-1882 and described in Table 12-3718.
Return to Summary Table.
PTM timer value lower 32-bits
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 70C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PTM_TIMER_OUT_LOW | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PTM_TIMER_OUT_LOW | R | 0h | ptm_timer_out[31:0] value from PCIe core. |
PCIE_USER_PTM_TIMER_HIGH is shown in Figure 12-1883 and described in Table 12-3720.
Return to Summary Table.
PTM timer value upper 32-bits
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 70C4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PTM_TIMER_OUT_HIGH | |||||||||||||||||||||||||||||||
R-0h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | PTM_TIMER_OUT_HIGH | R | 0h | ptm_timer_out[63:32] value from PCIe core. |
PCIE_USER_EOI_VECTOR is shown in Figure 12-1884 and described in Table 12-3722.
Return to the Summary Table.
EOI vector for re-triggering interrupts
Instance | Physical Address |
---|---|
PCIE1_CORE_USER_CFG_USER_CFG | 0291 70C8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_VECTOR | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | X | Reserved |
7-0 | EOI_VECTOR | R/W | 0h | EOI vector for level interrupts. Writing the EOI value as specfied to this register will re-trigger a pending interrupt. 0 - Downstream interrupt 1 - FLR interrupt 2 - Legacy interrupt 3 - Power state interrupt |