SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Each UDMA-P has an associated dedicated Ring Accelerator that is accessible by it alone (not accessible by other subsystems). The UDMA-P configuration is listed in Table 10-130.
Module Instance | Parameters | ||
Ring Count | Number of Monitors | Proxy Target Base | |
MCU_NAVSS0_UDMASS_RINGACC0 | 286 | 32 | 0x00002B000000 |
Table 10-131 shows the RINGACC ring mapping.
Mapping | Rings | Description |
MCU_NAVSS0_UDMASS_UDMAP0 Transmit | ring[47:0] | 48 UDMAP0 transmit channels |
MCU_NAVSS0_UDMASS_UDMAP0 Receive | ring[95:48] | 48 UDMAP0 receive channels |
General purpose | ring[255:96] | General-purpose rings |
MCU_NAVSS0_SEC_PROXY0 | ring[285:256] | SEC_PROXY0 rings |
For Ring Accelerator functional description, see Section 10.2.4, Ring Accelerator.
Table 10-132 shows the MSRAM configuration parameters set during SoC design. MSRAM is accessible only from the ring accelerator (DST port).
Module Instance | Parameters | ||
Depth | Width | Base Address | |
MCU_NAVSS0_UDMASS_MSRAM0 | 3594 | 64 | 0x000028000000 |
MCU_NAVSS0_UDMASS_MSRAM1 | 4096 | 64 | 0x000028010000 |