SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 6-49 lists the memory-mapped registers for the A72SS. All register offset addresses not listed in Table 6-49 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0000h |
Offset | Acronym | Register Name | COMPUTE_CLUSTER0_ A72SS0_COMMON_ ECC_AGGR Physical Address |
---|---|---|---|
0h | A72SS_CLUSTER_ECC_REV | Aggregator revision register | 4D 2001 0000h |
8h | A72SS_CLUSTER_ECC_VECTOR | ECC vector register | 4D 2001 0008h |
Ch | A72SS_CLUSTER_ECC_STAT | Misc status register | 4D 2001 000Ch |
3Ch | A72SS_CLUSTER_ECC_SEC_EOI_REG | SEC EOI register | 4D 2001 003Ch |
40h | A72SS_CLUSTER_ECC_SEC_STATUS_REG0 | SEC interrupt status register 0 | 4D 2001 0040h |
44h | A72SS_CLUSTER_ECC_SEC_STATUS_REG1 | SEC interrupt status register 1 | 4D 2001 0044h |
80h | A72SS_CLUSTER_ECC_SEC_ENABLE_SET_REG0 | SEC interrupt enable set register 0 | 4D 2001 0080h |
84h | A72SS_CLUSTER_ECC_SEC_ENABLE_SET_REG1 | SEC interrupt enable set register 1 | 4D 2001 0084h |
C0h | A72SS_CLUSTER_ECC_SEC_ENABLE_CLR_REG0 | SEC interrupt enable clear register 0 | 4D 2001 00C0h |
C4h | A72SS_CLUSTER_ECC_SEC_ENABLE_CLR_REG1 | SEC interrupt enable clear register 1 | 4D 2001 00C4h |
13Ch | A72SS_CLUSTER_ECC_DED_EOI_REG | DED EOI register | 4D 2001 013Ch |
140h | A72SS_CLUSTER_ECC_DED_STATUS_REG0 | DED interrupt status register 0 | 4D 2001 0140h |
144h | A72SS_CLUSTER_ECC_DED_STATUS_REG1 | DED interrupt status register 1 | 4D 2001 0144h |
180h | A72SS_CLUSTER_ECC_DED_ENABLE_SET_REG0 | DED interrupt enable set register 0 | 4D 2001 0180h |
184h | A72SS_CLUSTER_ECC_DED_ENABLE_SET_REG1 | DED interrupt enable set register 1 | 4D 2001 0184h |
1C0h | A72SS_CLUSTER_ECC_DED_ENABLE_CLR_REG0 | DED interrupt enable clear register 0 | 4D 2001 01C0h |
1C4h | A72SS_CLUSTER_ECC_DED_ENABLE_CLR_REG1 | DED interrupt enable clear register 1 | 4D 2001 01C4h |
200h | A72SS_CLUSTER_ECC_AGGR_ENABLE_SET | AGGR interrupt enable set register | 4D 2001 0200h |
204h | A72SS_CLUSTER_ECC_AGGR_ENABLE_CLR | AGGR interrupt enable clear register | 4D 2001 0204h |
208h | A72SS_CLUSTER_ECC_AGGR_STATUS_SET | AGGR interrupt status set register | 4D 2001 0208h |
20Ch | A72SS_CLUSTER_ECC_AGGR_STATUS_CLR | AGGR interrupt status clear register | 4D 2001 020Ch |
A72SS_CLUSTER_ECC_REV is shown in Figure 6-18 and described in Table 6-51.
Return to Summary Table.
IP revision register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66A0EA00h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66A0EA00h | TI internal data. Identifies revision of peripheral. |
A72SS_CLUSTER_ECC_VECTOR is shown in Figure 6-19 and described in Table 6-53.
Return to Summary Table.
ECC vector register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R | 0h | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
A72SS_CLUSTER_ECC_STAT is shown in Figure 6-20 and described in Table 6-55.
Return to Summary Table.
Misc status register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-2Ah | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-0 | NUM_RAMS | R | 2Ah | Indicates the number of RAMs serviced by the ECC aggregator |
A72SS_CLUSTER_ECC_SEC_EOI_REG is shown in Figure 6-21 and described in Table 6-57.
Return to Summary Table.
SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI value |
A72SS_CLUSTER_ECC_SEC_STATUS_REG0 is shown in Figure 6-22 and described in Table 6-59.
Return to Summary Table.
SEC interrupt status register 0.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_PEND | L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_PEND | L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_PEND | L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK15_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK14_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK13_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK12_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
L2_TAG_SPRAM_BANK11_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK10_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK9_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK8_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK7_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK6_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK5_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK4_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
L2_TAG_SPRAM_BANK3_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK2_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK0_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK7_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK6_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK5_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK4_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
L2_DATA_SPRAM_BANK3_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK2_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK1_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK0_ECC_SVBUS_PEND | L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_PEND | L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_PEND | L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_incl_plru_spram_bank1_ecc_svbus_pend |
30 | L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_incl_plru_spram_bank0_ecc_svbus_pend |
29 | L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_dirty_spram_bank1_ecc_svbus_pend |
28 | L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_dirty_spram_bank0_ecc_svbus_pend |
27 | L2_TAG_SPRAM_BANK15_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank15_ecc_svbus_pend |
26 | L2_TAG_SPRAM_BANK14_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank14_ecc_svbus_pend |
25 | L2_TAG_SPRAM_BANK13_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank13_ecc_svbus_pend |
24 | L2_TAG_SPRAM_BANK12_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank12_ecc_svbus_pend |
23 | L2_TAG_SPRAM_BANK11_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank11_ecc_svbus_pend |
22 | L2_TAG_SPRAM_BANK10_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank10_ecc_svbus_pend |
21 | L2_TAG_SPRAM_BANK9_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank9_ecc_svbus_pend |
20 | L2_TAG_SPRAM_BANK8_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank8_ecc_svbus_pend |
19 | L2_TAG_SPRAM_BANK7_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank7_ecc_svbus_pend |
18 | L2_TAG_SPRAM_BANK6_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank6_ecc_svbus_pend |
17 | L2_TAG_SPRAM_BANK5_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank5_ecc_svbus_pend |
16 | L2_TAG_SPRAM_BANK4_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank4_ecc_svbus_pend |
15 | L2_TAG_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank3_ecc_svbus_pend |
14 | L2_TAG_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank2_ecc_svbus_pend |
13 | L2_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank1_ecc_svbus_pend |
12 | L2_TAG_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank0_ecc_svbus_pend |
11 | L2_DATA_SPRAM_BANK7_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank7_ecc_svbus_pend |
10 | L2_DATA_SPRAM_BANK6_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank6_ecc_svbus_pend |
9 | L2_DATA_SPRAM_BANK5_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank5_ecc_svbus_pend |
8 | L2_DATA_SPRAM_BANK4_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank4_ecc_svbus_pend |
7 | L2_DATA_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank3_ecc_svbus_pend |
6 | L2_DATA_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank2_ecc_svbus_pend |
5 | L2_DATA_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank1_ecc_svbus_pend |
4 | L2_DATA_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank0_ecc_svbus_pend |
3 | L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_snp_tag_spram_bank3_ecc_svbus_pend |
2 | L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_snp_tag_spram_bank2_ecc_svbus_pend |
1 | L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_snp_tag_spram_bank1_ecc_svbus_pend |
0 | L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_snp_tag_spram_bank0_ecc_svbus_pend |
A72SS_CLUSTER_ECC_SEC_STATUS_REG1 is shown in Figure 6-23 and described in Table 6-61.
Return to Summary Table.
SEC interrupt status register 1.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VBUSP_CFG_DST_M2P_DST_BUSECC_PEND | VBUSP_CFG_M2M_M2M_VBUSS_PEND | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBUSP_CFG_M2M_DST_VBUSS_PEND | VBUSP_CFG_DST_M2P_SRC_BUSECC_PEND | A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_PEND | A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND | A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_PEND | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_PEND | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_PEND | EDC_CTRL_ECCAGGR_COREPAC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | VBUSP_CFG_DST_M2P_DST_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for vbusp_cfg_dst_m2p_dst_busecc_pend |
8 | VBUSP_CFG_M2M_M2M_VBUSS_PEND | R/W1S | 0h | Interrupt pending status for vbusp_cfg_m2m_m2m_vbuss_pend |
7 | VBUSP_CFG_M2M_DST_VBUSS_PEND | R/W1S | 0h | Interrupt pending status for vbusp_cfg_m2m_dst_vbuss_pend |
6 | VBUSP_CFG_DST_M2P_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for vbusp_cfg_dst_m2p_src_busecc_pend |
5 | A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend |
4 | A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend |
3 | A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend |
2 | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend |
1 | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend |
0 | EDC_CTRL_ECCAGGR_COREPAC_PEND | R/W1S | 0h | Interrupt pending status for edc_ctrl_eccaggr_corepac_pend |
A72SS_CLUSTER_ECC_SEC_ENABLE_SET_REG0 is shown in Figure 6-24 and described in Table 6-63.
Return to Summary Table.
SEC interrupt enable set register 0.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_incl_plru_spram_bank1_ecc_svbus_pend |
30 | L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_incl_plru_spram_bank0_ecc_svbus_pend |
29 | L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_dirty_spram_bank1_ecc_svbus_pend |
28 | L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_dirty_spram_bank0_ecc_svbus_pend |
27 | L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank15_ecc_svbus_pend |
26 | L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank14_ecc_svbus_pend |
25 | L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank13_ecc_svbus_pend |
24 | L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank12_ecc_svbus_pend |
23 | L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank11_ecc_svbus_pend |
22 | L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank10_ecc_svbus_pend |
21 | L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank9_ecc_svbus_pend |
20 | L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank8_ecc_svbus_pend |
19 | L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank7_ecc_svbus_pend |
18 | L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank6_ecc_svbus_pend |
17 | L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank5_ecc_svbus_pend |
16 | L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank4_ecc_svbus_pend |
15 | L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank3_ecc_svbus_pend |
14 | L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank2_ecc_svbus_pend |
13 | L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank1_ecc_svbus_pend |
12 | L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank0_ecc_svbus_pend |
11 | L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank7_ecc_svbus_pend |
10 | L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank6_ecc_svbus_pend |
9 | L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank5_ecc_svbus_pend |
8 | L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank4_ecc_svbus_pend |
7 | L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank3_ecc_svbus_pend |
6 | L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank2_ecc_svbus_pend |
5 | L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank1_ecc_svbus_pend |
4 | L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank0_ecc_svbus_pend |
3 | L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_snp_tag_spram_bank3_ecc_svbus_pend |
2 | L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_snp_tag_spram_bank2_ecc_svbus_pend |
1 | L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_snp_tag_spram_bank1_ecc_svbus_pend |
0 | L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_snp_tag_spram_bank0_ecc_svbus_pend |
A72SS_CLUSTER_ECC_SEC_ENABLE_SET_REG1 is shown in Figure 6-25 and described in Table 6-65.
Return to Summary Table.
SEC interrupt enable set register 1.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_SET | VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_SET | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBUSP_CFG_M2M_DST_VBUSS_ENABLE_SET | VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_SET | A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_SET | A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET | A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_SET | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_SET | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_SET | EDC_CTRL_ECCAGGR_COREPAC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for vbusp_cfg_dst_m2p_dst_busecc_pend |
8 | VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for vbusp_cfg_m2m_m2m_vbuss_pend |
7 | VBUSP_CFG_M2M_DST_VBUSS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for vbusp_cfg_m2m_dst_vbuss_pend |
6 | VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for vbusp_cfg_dst_m2p_src_busecc_pend |
5 | A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend |
4 | A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend |
3 | A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend |
2 | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend |
1 | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend |
0 | EDC_CTRL_ECCAGGR_COREPAC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for edc_ctrl_eccaggr_corepac_pend |
A72SS_CLUSTER_ECC_SEC_ENABLE_CLR_REG0 is shown in Figure 6-26 and described in Table 6-67.
Return to Summary Table.
SEC interrupt enable clear register 0.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 00C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_incl_plru_spram_bank1_ecc_svbus_pend |
30 | L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_incl_plru_spram_bank0_ecc_svbus_pend |
29 | L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_dirty_spram_bank1_ecc_svbus_pend |
28 | L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_dirty_spram_bank0_ecc_svbus_pend |
27 | L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank15_ecc_svbus_pend |
26 | L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank14_ecc_svbus_pend |
25 | L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank13_ecc_svbus_pend |
24 | L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank12_ecc_svbus_pend |
23 | L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank11_ecc_svbus_pend |
22 | L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank10_ecc_svbus_pend |
21 | L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank9_ecc_svbus_pend |
20 | L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank8_ecc_svbus_pend |
19 | L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank7_ecc_svbus_pend |
18 | L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank6_ecc_svbus_pend |
17 | L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank5_ecc_svbus_pend |
16 | L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank4_ecc_svbus_pend |
15 | L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank3_ecc_svbus_pend |
14 | L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank2_ecc_svbus_pend |
13 | L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank1_ecc_svbus_pend |
12 | L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank0_ecc_svbus_pend |
11 | L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank7_ecc_svbus_pend |
10 | L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank6_ecc_svbus_pend |
9 | L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank5_ecc_svbus_pend |
8 | L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank4_ecc_svbus_pend |
7 | L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank3_ecc_svbus_pend |
6 | L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank2_ecc_svbus_pend |
5 | L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank1_ecc_svbus_pend |
4 | L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank0_ecc_svbus_pend |
3 | L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_snp_tag_spram_bank3_ecc_svbus_pend |
2 | L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_snp_tag_spram_bank2_ecc_svbus_pend |
1 | L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_snp_tag_spram_bank1_ecc_svbus_pend |
0 | L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_snp_tag_spram_bank0_ecc_svbus_pend |
A72SS_CLUSTER_ECC_SEC_ENABLE_CLR_REG1 is shown in Figure 6-27 and described in Table 6-69.
Return to Summary Table.
SEC interrupt enable clear register 1.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 00C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_CLR | VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_CLR | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBUSP_CFG_M2M_DST_VBUSS_ENABLE_CLR | VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_CLR | A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_CLR | A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_CLR | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_CLR | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_CLR | EDC_CTRL_ECCAGGR_COREPAC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for vbusp_cfg_dst_m2p_dst_busecc_pend |
8 | VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for vbusp_cfg_m2m_m2m_vbuss_pend |
7 | VBUSP_CFG_M2M_DST_VBUSS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for vbusp_cfg_m2m_dst_vbuss_pend |
6 | VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for vbusp_cfg_dst_m2p_src_busecc_pend |
5 | A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend |
4 | A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend |
3 | A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend |
2 | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend |
1 | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend |
0 | EDC_CTRL_ECCAGGR_COREPAC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for edc_ctrl_eccaggr_corepac_pend |
A72SS_CLUSTER_ECC_DED_EOI_REG is shown in Figure 6-28 and described in Table 6-71.
Return to Summary Table.
DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 013Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI value |
A72SS_CLUSTER_ECC_DED_STATUS_REG0 is shown in Figure 6-29 and described in Table 6-73.
Return to Summary Table.
DED interrupt status register 0.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_PEND | L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_PEND | L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_PEND | L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK15_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK14_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK13_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK12_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
L2_TAG_SPRAM_BANK11_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK10_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK9_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK8_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK7_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK6_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK5_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK4_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
L2_TAG_SPRAM_BANK3_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK2_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | L2_TAG_SPRAM_BANK0_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK7_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK6_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK5_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK4_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
L2_DATA_SPRAM_BANK3_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK2_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK1_ECC_SVBUS_PEND | L2_DATA_SPRAM_BANK0_ECC_SVBUS_PEND | L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_PEND | L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_PEND | L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_incl_plru_spram_bank1_ecc_svbus_pend |
30 | L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_incl_plru_spram_bank0_ecc_svbus_pend |
29 | L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_dirty_spram_bank1_ecc_svbus_pend |
28 | L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_dirty_spram_bank0_ecc_svbus_pend |
27 | L2_TAG_SPRAM_BANK15_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank15_ecc_svbus_pend |
26 | L2_TAG_SPRAM_BANK14_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank14_ecc_svbus_pend |
25 | L2_TAG_SPRAM_BANK13_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank13_ecc_svbus_pend |
24 | L2_TAG_SPRAM_BANK12_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank12_ecc_svbus_pend |
23 | L2_TAG_SPRAM_BANK11_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank11_ecc_svbus_pend |
22 | L2_TAG_SPRAM_BANK10_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank10_ecc_svbus_pend |
21 | L2_TAG_SPRAM_BANK9_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank9_ecc_svbus_pend |
20 | L2_TAG_SPRAM_BANK8_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank8_ecc_svbus_pend |
19 | L2_TAG_SPRAM_BANK7_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank7_ecc_svbus_pend |
18 | L2_TAG_SPRAM_BANK6_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank6_ecc_svbus_pend |
17 | L2_TAG_SPRAM_BANK5_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank5_ecc_svbus_pend |
16 | L2_TAG_SPRAM_BANK4_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank4_ecc_svbus_pend |
15 | L2_TAG_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank3_ecc_svbus_pend |
14 | L2_TAG_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank2_ecc_svbus_pend |
13 | L2_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank1_ecc_svbus_pend |
12 | L2_TAG_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_tag_spram_bank0_ecc_svbus_pend |
11 | L2_DATA_SPRAM_BANK7_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank7_ecc_svbus_pend |
10 | L2_DATA_SPRAM_BANK6_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank6_ecc_svbus_pend |
9 | L2_DATA_SPRAM_BANK5_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank5_ecc_svbus_pend |
8 | L2_DATA_SPRAM_BANK4_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank4_ecc_svbus_pend |
7 | L2_DATA_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank3_ecc_svbus_pend |
6 | L2_DATA_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank2_ecc_svbus_pend |
5 | L2_DATA_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank1_ecc_svbus_pend |
4 | L2_DATA_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_data_spram_bank0_ecc_svbus_pend |
3 | L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_snp_tag_spram_bank3_ecc_svbus_pend |
2 | L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_snp_tag_spram_bank2_ecc_svbus_pend |
1 | L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_snp_tag_spram_bank1_ecc_svbus_pend |
0 | L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_PEND | R/W1S | 0h | Interrupt pending status for l2_snp_tag_spram_bank0_ecc_svbus_pend |
A72SS_CLUSTER_ECC_DED_STATUS_REG1 is shown in Figure 6-30 and described in Table 6-75.
Return to Summary Table.
DED interrupt status register 1.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VBUSP_CFG_DST_M2P_DST_BUSECC_PEND | VBUSP_CFG_M2M_M2M_VBUSS_PEND | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBUSP_CFG_M2M_DST_VBUSS_PEND | VBUSP_CFG_DST_M2P_SRC_BUSECC_PEND | A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_PEND | A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND | A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_PEND | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_PEND | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_PEND | EDC_CTRL_ECCAGGR_COREPAC_PEND |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | VBUSP_CFG_DST_M2P_DST_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for vbusp_cfg_dst_m2p_dst_busecc_pend |
8 | VBUSP_CFG_M2M_M2M_VBUSS_PEND | R/W1S | 0h | Interrupt pending status for vbusp_cfg_m2m_m2m_vbuss_pend |
7 | VBUSP_CFG_M2M_DST_VBUSS_PEND | R/W1S | 0h | Interrupt pending status for vbusp_cfg_m2m_dst_vbuss_pend |
6 | VBUSP_CFG_DST_M2P_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for vbusp_cfg_dst_m2p_src_busecc_pend |
5 | A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend |
4 | A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend |
3 | A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend |
2 | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend |
1 | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_PEND | R/W1S | 0h | Interrupt pending status for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend |
0 | EDC_CTRL_ECCAGGR_COREPAC_PEND | R/W1S | 0h | Interrupt pending status for edc_ctrl_eccaggr_corepac_pend |
A72SS_CLUSTER_ECC_DED_ENABLE_SET_REG0 is shown in Figure 6-31 and described in Table 6-77.
Return to Summary Table.
DED interrupt enable set register 0.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_incl_plru_spram_bank1_ecc_svbus_pend |
30 | L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_incl_plru_spram_bank0_ecc_svbus_pend |
29 | L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_dirty_spram_bank1_ecc_svbus_pend |
28 | L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_dirty_spram_bank0_ecc_svbus_pend |
27 | L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank15_ecc_svbus_pend |
26 | L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank14_ecc_svbus_pend |
25 | L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank13_ecc_svbus_pend |
24 | L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank12_ecc_svbus_pend |
23 | L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank11_ecc_svbus_pend |
22 | L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank10_ecc_svbus_pend |
21 | L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank9_ecc_svbus_pend |
20 | L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank8_ecc_svbus_pend |
19 | L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank7_ecc_svbus_pend |
18 | L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank6_ecc_svbus_pend |
17 | L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank5_ecc_svbus_pend |
16 | L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank4_ecc_svbus_pend |
15 | L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank3_ecc_svbus_pend |
14 | L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank2_ecc_svbus_pend |
13 | L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank1_ecc_svbus_pend |
12 | L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_tag_spram_bank0_ecc_svbus_pend |
11 | L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank7_ecc_svbus_pend |
10 | L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank6_ecc_svbus_pend |
9 | L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank5_ecc_svbus_pend |
8 | L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank4_ecc_svbus_pend |
7 | L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank3_ecc_svbus_pend |
6 | L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank2_ecc_svbus_pend |
5 | L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank1_ecc_svbus_pend |
4 | L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_data_spram_bank0_ecc_svbus_pend |
3 | L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_snp_tag_spram_bank3_ecc_svbus_pend |
2 | L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_snp_tag_spram_bank2_ecc_svbus_pend |
1 | L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_snp_tag_spram_bank1_ecc_svbus_pend |
0 | L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for l2_snp_tag_spram_bank0_ecc_svbus_pend |
A72SS_CLUSTER_ECC_DED_ENABLE_SET_REG1 is shown in Figure 6-32 and described in Table 6-79.
Return to Summary Table.
DED interrupt enable set register 1.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_SET | VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_SET | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBUSP_CFG_M2M_DST_VBUSS_ENABLE_SET | VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_SET | A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_SET | A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET | A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_SET | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_SET | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_SET | EDC_CTRL_ECCAGGR_COREPAC_ENABLE_SET |
R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | |
9 | VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for vbusp_cfg_dst_m2p_dst_busecc_pend |
8 | VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for vbusp_cfg_m2m_m2m_vbuss_pend |
7 | VBUSP_CFG_M2M_DST_VBUSS_ENABLE_SET | R/W1S | 0h | Interrupt enable set for vbusp_cfg_m2m_dst_vbuss_pend |
6 | VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for vbusp_cfg_dst_m2p_src_busecc_pend |
5 | A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend |
4 | A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend |
3 | A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend |
2 | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend |
1 | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend |
0 | EDC_CTRL_ECCAGGR_COREPAC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for edc_ctrl_eccaggr_corepac_pend |
A72SS_CLUSTER_ECC_DED_ENABLE_CLR_REG0 is shown in Figure 6-33 and described in Table 6-81.
Return to Summary Table.
DED interrupt enable clear register 0.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 01C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | L2_INCL_PLRU_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_incl_plru_spram_bank1_ecc_svbus_pend |
30 | L2_INCL_PLRU_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_incl_plru_spram_bank0_ecc_svbus_pend |
29 | L2_DIRTY_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_dirty_spram_bank1_ecc_svbus_pend |
28 | L2_DIRTY_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_dirty_spram_bank0_ecc_svbus_pend |
27 | L2_TAG_SPRAM_BANK15_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank15_ecc_svbus_pend |
26 | L2_TAG_SPRAM_BANK14_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank14_ecc_svbus_pend |
25 | L2_TAG_SPRAM_BANK13_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank13_ecc_svbus_pend |
24 | L2_TAG_SPRAM_BANK12_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank12_ecc_svbus_pend |
23 | L2_TAG_SPRAM_BANK11_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank11_ecc_svbus_pend |
22 | L2_TAG_SPRAM_BANK10_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank10_ecc_svbus_pend |
21 | L2_TAG_SPRAM_BANK9_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank9_ecc_svbus_pend |
20 | L2_TAG_SPRAM_BANK8_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank8_ecc_svbus_pend |
19 | L2_TAG_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank7_ecc_svbus_pend |
18 | L2_TAG_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank6_ecc_svbus_pend |
17 | L2_TAG_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank5_ecc_svbus_pend |
16 | L2_TAG_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank4_ecc_svbus_pend |
15 | L2_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank3_ecc_svbus_pend |
14 | L2_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank2_ecc_svbus_pend |
13 | L2_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank1_ecc_svbus_pend |
12 | L2_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_tag_spram_bank0_ecc_svbus_pend |
11 | L2_DATA_SPRAM_BANK7_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank7_ecc_svbus_pend |
10 | L2_DATA_SPRAM_BANK6_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank6_ecc_svbus_pend |
9 | L2_DATA_SPRAM_BANK5_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank5_ecc_svbus_pend |
8 | L2_DATA_SPRAM_BANK4_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank4_ecc_svbus_pend |
7 | L2_DATA_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank3_ecc_svbus_pend |
6 | L2_DATA_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank2_ecc_svbus_pend |
5 | L2_DATA_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank1_ecc_svbus_pend |
4 | L2_DATA_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_data_spram_bank0_ecc_svbus_pend |
3 | L2_SNP_TAG_SPRAM_BANK3_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_snp_tag_spram_bank3_ecc_svbus_pend |
2 | L2_SNP_TAG_SPRAM_BANK2_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_snp_tag_spram_bank2_ecc_svbus_pend |
1 | L2_SNP_TAG_SPRAM_BANK1_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_snp_tag_spram_bank1_ecc_svbus_pend |
0 | L2_SNP_TAG_SPRAM_BANK0_ECC_SVBUS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for l2_snp_tag_spram_bank0_ecc_svbus_pend |
A72SS_CLUSTER_ECC_DED_ENABLE_CLR_REG1 is shown in Figure 6-34 and described in Table 6-83.
Return to Summary Table.
DED interrupt enable clear register 1.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 01C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_CLR | VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_CLR | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
VBUSP_CFG_M2M_DST_VBUSS_ENABLE_CLR | VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_CLR | A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_CLR | A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_CLR | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_CLR | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_CLR | EDC_CTRL_ECCAGGR_COREPAC_ENABLE_CLR |
R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h |
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R | 0h | Reserved |
9 | VBUSP_CFG_DST_M2P_DST_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for vbusp_cfg_dst_m2p_dst_busecc_pend |
8 | VBUSP_CFG_M2M_M2M_VBUSS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for vbusp_cfg_m2m_m2m_vbuss_pend |
7 | VBUSP_CFG_M2M_DST_VBUSS_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for vbusp_cfg_m2m_dst_vbuss_pend |
6 | VBUSP_CFG_DST_M2P_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for vbusp_cfg_dst_m2p_src_busecc_pend |
5 | A72_J7_COREPAC_CBASS_DIVH_CLK2_CLK_CLK_EDC_CTRL_CBASS_INT_DIVH_CLK2_CLK_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for a72_j7_corepac_cbass_divh_clk2_clk_clk_edc_ctrl_cbass_int_divh_clk2_clk_busecc_pend |
4 | A72_J7_COREPAC_CBASS_SCR1_SCR_A72_J7_COREPAC_CBASS_SCR1_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for a72_j7_corepac_cbass_scr1_scr_a72_j7_corepac_cbass_scr1_scr_edc_ctrl_busecc_pend |
3 | A72_J7_COREPAC_CBASS_VBUSP_ECC_COREPAC_P2P_BRIDGE_VBUSP_ECC_COREPAC_BRIDGE_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for a72_j7_corepac_cbass_vbusp_ecc_corepac_p2p_bridge_vbusp_ecc_corepac_bridge_busecc_pend |
2 | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE1_P2P_BRIDGE_VBUSP_ECC_CORE1_BRIDGE_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for a72_j7_corepac_cbass_vbusp_ecc_core1_p2p_bridge_vbusp_ecc_core1_bridge_busecc_pend |
1 | A72_J7_COREPAC_CBASS_VBUSP_ECC_CORE0_P2P_BRIDGE_VBUSP_ECC_CORE0_BRIDGE_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for a72_j7_corepac_cbass_vbusp_ecc_core0_p2p_bridge_vbusp_ecc_core0_bridge_busecc_pend |
0 | EDC_CTRL_ECCAGGR_COREPAC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear for edc_ctrl_eccaggr_corepac_pend |
A72SS_CLUSTER_ECC_AGGR_ENABLE_SET is shown in Figure 6-35 and described in Table 6-85.
Return to Summary Table.
AGGR interrupt enable set register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | Interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | Interrupt enable set for parity errors |
A72SS_CLUSTER_ECC_AGGR_ENABLE_CLR is shown in Figure 6-36 and described in Table 6-87.
Return to Summary Table.
AGGR interrupt enable clear register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | Interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | Interrupt enable clear for parity errors |
A72SS_CLUSTER_ECC_AGGR_STATUS_SET is shown in Figure 6-37 and described in Table 6-89.
Return to Summary Table.
AGGR interrupt status set register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 0208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | Interrupt status set for svbus timeout errors |
1-0 | PARITY | R/Wincr | 0h | Interrupt status set for parity errors |
A72SS_CLUSTER_ECC_AGGR_STATUS_CLR is shown in Figure 6-38 and described in Table 6-91.
Return to Summary Table.
AGGR interrupt status clear register.
Instance | Physical Address |
---|---|
COMPUTE_CLUSTER0_A72SS0_COMMON_ECC_AGGR | 4D 2001 020Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | Interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/Wdecr | 0h | Interrupt status clear for parity errors |