SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-643 lists the PDMA_USART_PSILSS0 registers. All register offset addresses not listed in Table 10-643 should be considered as reserved locations and the register contents should not be modified.
Memory Region | Base Address |
---|---|
PDMA16_MMRS | 0340 0000h |
Offset | Acronym | Register Name | PDMA16_MMRS Physical Address |
---|---|---|---|
0h | PDMA_USART_PSILSS0_PID | Revision Register | 0340 0000h |
4h | PDMA_USART_PSILSS0_CONFIG | Config Register | 0340 0004h |
10h | PDMA_USART_PSILSS0_EVENT | Event Register | 0340 0010h |
20h | PDMA_USART_PSILSS0_LINK | Link Register | 0340 0020h |
40h | PDMA_USART_PSILSS0_DOWN | Link Down Register | 0340 0040h |
PDMA_USART_PSILSS0_PID is shown in Figure 10-237 and described in Table 10-645.
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The Revision Register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
PDMA16_MMRS | 0340 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66C49100h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66C49100h | TI internal data. Identifies revision of peripheral. |
PDMA_USART_PSILSS0_CONFIG is shown in Figure 10-238 and described in Table 10-647.
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The Config Register shows configured parameters.
Instance | Physical Address |
---|---|
PDMA16_MMRS | 0340 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENDPOINTS | ||||||||||||||||||||||||||||||
R-0h | R-5h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | ENDPOINTS | R | 5h | Number of endpoints supported |
PDMA_USART_PSILSS0_EVENT is shown in Figure 10-239 and described in Table 10-649.
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The Event Register defines the event to produce for a link down event.
Instance | Physical Address |
---|---|
PDMA16_MMRS | 0340 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVT | ||||||||||||||||||||||||||||||
R-0h | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R | 0h | Reserved |
15-0 | EVT | R/W | FFFFh | The event to produce |
PDMA_USART_PSILSS0_LINK is shown in Figure 10-240 and described in Table 10-651.
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The Link Register shows the current status of the endpoint links.
Instance | Physical Address |
---|---|
PDMA16_MMRS | 0340 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATUS | |||||||||||||||||||||||||||||||
R-X | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | STATUS | R | X | The status of the endpoint links Bit [0]: PDMA_STRM Bit [1]: USART_G0_STRM Bit [2]: USART_G1_STRM Bit [3]: USART_G2_STRM Bit [4]: MCAN_STRM |
PDMA_USART_PSILSS0_DOWN is shown in Figure 10-241 and described in Table 10-653.
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The Link Down Register shows which links are down for the endpoints.
Instance | Physical Address |
---|---|
PDMA16_MMRS | 0340 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STATUS | |||||||||||||||||||||||||||||||
R/W1C-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | STATUS | R/W1C | 0h | The down status of the endpoint links Bit [0]: PDMA_STRM Bit [1]: USART_G0_STRM Bit [2]: USART_G1_STRM Bit [3]: USART_G2_STRM Bit [4]: MCAN_STRM |