SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
There is one OSPI module integrated in the device MCU domain - MCU_FSS0_OSPI0. Figure 12-1974 shows its integration in the device.
Table 12-3911 through Table 12-3913 summarize the integration of MCU_FSS0_OSPI0 in device MCU domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
MCU_FSS0_OSPI0 | WKUP_PSC0 | PD0 | LPSC10 | MCU_CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
MCU_FSS0_OSPI0 | OSPI0_HCLK | MCU_SYSCLK0/3 | WKUP_PLLCTRL0 | MCU_FSS0_OSPI0 data transfer clock |
OSPI0_PCLK | MCU_SYSCLK0/3 | WKUP_PLLCTRL0 | MCU_FSS0_OSPI0 configuration clock | |
OSPI0_RCLK | MCU_PLL1_HSDIV4_CLKOUT | MCU_PLL1_HSDIV4 | MCU_FSS0_OSPI0 Reference clock. Mux controlled by CTRLMMR_MCU_OSPI0_CLKSEL[0] CLK_SEL in Control Module (CTRL_MMR) | |
MCU_PLL2_HSDIV4_CLKOUT | MCU_PLL2_HSDIV4 | |||
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
MCU_FSS0_OSPI0 | MCU_FSS0_OSPI0_RST | MOD_G_RST | LPSC10 | MCU_FSS0_OSPI0 reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
MCU_FSS0_OSPI0 | MCU_FSS0_OSPI_0_OSPI_LVL_INTR_0 | WKUP_DMSC0_INTR_IN_48 | WKUP_DMSC0 | MCU_FSS0_OSPI0 interrupt | Level |
GIC500_SPI_IN_872 | COMPUTE_CLUSTER0 | ||||
R5FSS0_CORE0_INTR_IN_470 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_470 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_24 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_24 | MCU_R5FSS0_CORE1 | ||||
MCU_FSS0_OSPI_0_OSPI_ECC_CORR_LVL_INTR_0 | MCU_ESM0_LVL_IN_24 | MCU_ESM0 | MCU_FSS0_OSPI0 ECC Aggregator correctable error interrupt | Level | |
MCU_FSS0_OSPI_0_OSPI_ECC_UNCORR_LVL_INTR_0 | MCU_ESM0_LVL_IN_25 | MCU_ESM0 | MCU_FSS0_OSPI0 ECC Aggregator uncorrectable error interrupt | Level |