SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-255 lists the memory-mapped registers for the UDMASS_UDMAP0_CFG_TCHAN. All register offset addresses not listed in Table 10-255 should be considered as reserved locations and the register contents should not be modified.
The UDMA-P Tx Channel Configuration Registers region is accessed by setting the cdma_cfg_rsel signal to 2 during the access. The address map for this region is as follows:
Instance | Base Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHAN | 30B0 0000h |
MCU_NAVSS0_UDMASS_UDMAP0_TCHAN | 284A 0000h |
Offset | Acronym | Register Name | NAVSS0_UDMASS_UDMAP0_CFG_TCHAN Physical Address | MCU_NAVSS0_UDMASS_UDMAP0_TCHAN Physical Address |
---|---|---|---|---|
0h + formula | UDMA_TCFG_j | Tx Channel Configuration | 30B0 0000h + formula | 284A 0000h + formula |
4h + formula | UDMA_TCREDIT_j | Tx Channel Transfer Request Credit | 30B0 0004h + formula | 284A 0004h + formula |
14h + formula | UDMA_TCQ_j | Tx Channel Completion Queue | 30B0 0014h + formula | 284A 0014h + formula |
20h + formula | UDMA_TOES_j | Tx Channel Output Event Steering 0 | 30B0 0020h + formula | 284A 0020h + formula |
60h + formula | UDMA_TEOES_j | Tx Channel Error Output Event Steering 0 | 30B0 0060h + formula | 284A 0060h + formula |
64h + formula | UDMA_TPRI_CTRL_j | Tx Channel Priority Control | 30B0 0064h + formula | 284A 0064h + formula |
68h + formula | UDMA_THREAD_j | Tx Channel Destination ThreadID Mapping | 30B0 0068h + formula | 284A 0068h + formula |
70h + formula | UDMA_TFIFO_DEPTH_j | Tx Channel FIFO Depth | 30B0 0070h + formula | 284A 0070h + formula |
80h + formula | UDMA_TST_SCHED_j | Tx Channel Static Scheduler Config | 30B0 0080h + formula | 284A 0080h + formula |
UDMA_TCFG_j is shown in Figure 10-80 and described in Table 10-257.
Return to Summary Table.
The Tx Channel Configuration Register is used to initialize static mode settings for the Tx DMA channel. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0).
Offset = 0h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_TCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHAN | 30B0 0000h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_TCHAN | 284A 0000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
PAUSE_ON_ERR | FILT_EINFO | FILT_PSWORDS | RESERVED | ATYPE | |||
R/W-0h | R/W-0h | R/W-0h | R/W-X | R/W-0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | CHAN_TYPE | ||||||
R/W-X | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | BURST_SIZE | TDYPE | NOTDPKT | ||||
R/W-X | R/W-1h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FETCH_SIZE | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | PAUSE_ON_ERR | R/W | 0h | Pause On Error: this field controls what the channel will do if an error or exception occurs during a data transfer. This field is encoded as follows: 0 = Channel will drop current work and move on 1 = Channel will pause and wait for SW to investigate and un-pause the channel. |
30 | FILT_EINFO | R/W | 0h | This field controls whether or not the DMA controller will pass the extended packet information fields (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass extended packet info words if they are present in the descriptor 1=DMA controller will filter extended packet info words. |
29 | FILT_PSWORDS | R/W | 0h | This field controls whether or not the DMA controller will pass the protocol specific words (if present) from the descriptor to the back end application. This field is encoded as follows: 0=DMA controller will pass PS words if present in descriptor 1=DMA controller will filter PS words. |
28-26 | RESERVED | R/W | X | |
25-24 | ATYPE | R/W | 0h | This field controls how pointers will be interpreted for non Ring Accelerator accesses on this channel. The values are encoded as follows: 0 = Pointers are physical addresses 1 = Pointers are intermediate addresses which require intermediate to physical transaction before they can be decoded 2 = Pointers are virtual addresses which require virtual to physical translation before they can be decoded. All transactions from this channel which are not destined to the Ring Accelerator will have the mem*_catype attribute set equal to the value given in this register field. Accesses to the RA will always use physical addresses. |
23-20 | RESERVED | R/W | X | |
19-16 | CHAN_TYPE | R/W | 0h | Tx Channel Type: this field controls and / or indicates the functional channel type for this channel and the work passing mechanism that the channel uses for communicating with the Host. Available channel types are as follows: 0 = RESERVED 1 = RESERVED 2 = Channel performs packet oriented data transfers using pass by reference rings. Channels configured in this mode can only use Host and Monolithic descriptors and the pointers to those descriptors are passed from/to SW using rings in the Ring Accelerator. 3- 9 = RESERVED 10 = Channel performs Third Party DMA transfers using pass by reference rings. Channels configured in this mode can only use TR descriptors and the pointers to those descriptors are passed from/to SW using rings in the Ring Accelerator. 11 = Channel performs Third Party DMA transfers using pass by value rings. Channels configured in this mode will directly pass individual Transfer Request/Transfer Response messages from/to SW using rings in the Ring Accelerator. 12 = Channel performs Third Party Block Copy DMA transfers using pass by reference rings. Channels configured in this mode are linked to the same index Rx channel to form a bonded read/write channel 13 = Channel performs Third Party Block Copy DMA transfers using pass by value rings. Channels configured in this mode are linked to the same index Rx channel to form a bonded read/write channel 14 = Channel performs Third Party DMA transfers using TRs provided via PSI-L (not supported in UDMA-P). 15 = Channel performs Third Party DMA transfers using TRs provided via QDMA channel (not supported in UDMA-P) |
15-12 | RESERVED | R/W | X | |
11-10 | BURST_SIZE | R/W | 1h | Specifies the nominal burst size and alignment for data
transfers on this channel. Transmit Data fetches are not allowed to initiate unless sufficient free space exists in the Tx Per Channel Buffer for that channel. Free space is calculated based on the value programmed into the Tx Channel FIFO Depth register. Care must be taken to ensure that the nominal burst size field (this field) meets the following restrictions: 1. For UTC mode channels: a. The Tx FIFO size must be at least 2 quad words larger than the burst size given in this field b. The Tx FIFO size must be less than or equal to the physically implemented storage for that channel class (UHC/HC/NC) 2. For Packet mode channels: a. The Tx FIFO size must be at least 2 PSI-L data phases larger than the burst size given in this field in order to hold the packet info and extended packet info header which is placed at the front of the data packet in addition to the payload. The Tx FIFO size must be less than or equal to the physically implemented storage for that channel class (UHC/HC/NC) Unless otherwise noted, it should be assumed that only HC/UHC channels can be programmed to use a burst size greater than 64 bytes. |
9 | TDTYPE | R/W | 0h |
Specifies whether
or not the channel should immediately return a teardown
completion response to the default completion queue or wait
until a status message is returned from the remote PSI-L paired
peripheral. |
8 | NOTDPKT | R/W | 0h | Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. 0 = TD packet is sent 1 = Suppress sending TD packet |
7 | RESERVED | R/W | X | |
6-0 | FETCH_SIZE | R/W | 0h | Specifies the # of 32-bit descriptor words to fetch. This must be set to the maximum word count that can pass through the channel for any allowed descriptor type. |
UDMA_TCREDIT_j is shown in Figure 10-81 and described in Table 10-259.
Return to Summary Table.
The Transfer Request Credit Register indicates how many TR sized buffer slots exist in the associated UTC channel to which this channel is associated. This register only exists for external UTC channels. This field should not be changed while the channel is in operation.
Offset = 4h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_TCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHAN | 30B0 0004h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_TCHAN | 284A 0004h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-3 | RESERVED | R/W | X | |
2-0 | COUNT | R/W | 0h | Transfer Request Credit Count: this field specifies how many credits for complete TRs are available. This field should be initialized before the channel is enabled and will then increment/decrement as TRs are submitted and responses are received. |
UDMA_TCQ_j is shown in Figure 10-82 and described in Table 10-261.
Return to Summary Table.
The Tx Channel Completion Queue Register is used to specify which queue the Transfer Responses will be returned to when operating in the pass by value channel mode. This register may only be written when the channel is disabled (tx_enable in realtime control reg is 0).
Offset = 14h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_TCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHAN | 30B0 0014h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_TCHAN | 284A 0014h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TXCQ_QNUM | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | TXCQ_QNUM | R/W | 0h | Specifies the queue number to return pass by value Transfer Responses and teardown completion teardown messages to. |
UDMA_TOES_j is shown in Figure 10-83 and described in Table 10-263.
Return to Summary Table.
The Output Event Steering Registers are used to specify a global event number to generate anytime the required event generation criteria specified in a TR are met. A single event with the event number set equal to the value in the corresponding register will be generated. This register is provided in order to allow security SW to lock down which events in the global space any given channel/ thread is allowed to generate.
Offset = 20h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_TCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHAN | 30B0 0020h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_TCHAN | 284A 0020h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVT_NUM | ||||||||||||||||||||||||||||||
R/W-X | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | EVT_NUM | R/W | FFFFh | This is the global event number to be generated |
UDMA_TEOES_j is shown in Figure 10-84 and described in Table 10-265.
Return to Summary Table.
The Error Output Event Steering Registers are used to specify a global event number to generate anytime an error is encountered on the channel. A single event with the event number set equal to the value in the corresponding register will be generated. This register is provided in order to allow security SW to lock down which events in the global space any given channel/ thread is allowed to generate.
Offset = 60h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_TCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHAN | 30B0 0060h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_TCHAN | 284A 0060h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EVT_NUM | ||||||||||||||||||||||||||||||
R/W-X | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | EVT_NUM | R/W | FFFFh | This is the global event number to be generated |
UDMA_TPRI_CTRL_j is shown in Figure 10-85 and described in Table 10-267.
Return to Summary Table.
The priority control register is used to control the priority of the transactions which the DMA generates on it's master interface.
Offset = 64h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_TCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHAN | 30B0 0064h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_TCHAN | 284A 0064h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | PRIORITY | RESERVED | QOS | ||||||||||||
R/W-X | R/W-0h | R/W-X | R/W-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ORDERID | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | RESERVED | R/W | X | |
30-28 | PRIORITY | R/W | 0h | Tx Priority: This field contains the 3-bit value which will be output on the mem*_cpriority and mem_cepriority outputs during all transactions for this channel. |
27-19 | RESERVED | R/W | X | |
18-16 | QOS | R/W | 0h | Tx Quality of Service Level: This field contains the 3-bit value which will be output on the mem*_cqos output during all transactions for this channel. |
15-4 | RESERVED | R/W | X | |
3-0 | ORDERID | R/W | 0h | Tx Order ID: This field contains the 4-bit value which will be output on the mem*_corderid output during all transactions for this channel. |
UDMA_THREAD_j is shown in Figure 10-86 and described in Table 10-269.
Return to Summary Table.
The thread ID mapping register is used to pair the Tx DMA channel to a specific destination thread. All traffic generated from this channel will be sent with a thread_id on the PSI-L interface with the value from this register.
Offset = 68h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_TCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHAN | 30B0 0068h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_TCHAN | 284A 0068h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ID | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | ID | R/W | 0h | Thread ID: This field contains the 16-bit value which will be output on the strm_o_thread_id output during all transactions for this channel. |
UDMA_TFIFO_DEPTH_j is shown in Figure 10-87 and described in Table 10-271.
Return to Summary Table.
The fifo depth register is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time, the FIFO depth can be artificially reduced in order to control the maximum latency which can be introduced due to buffering effects. This register is only present for internal channels.
Offset = 70h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_TCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHAN | 30B0 0070h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_TCHAN | 284A 0070h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FDEPTH | ||||||||||||||||||||||||||||||
R/W-X | R/W-1000h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-13 | RESERVED | R/W | X | |
12-0 | FDEPTH | R/W | 1000h |
FIFO Depth: This
field contains the number of Tx FIFO bytes which will be allowed
to be stored for the channel. |
UDMA_TST_SCHED_j is shown in Figure 10-88 and described in Table 10-273.
Return to Summary Table.
The Tx Channel N Static Scheduler Configuration Register contains static configuration information which affects the conditions under which each channel will be given an opportunity to use the Tx DMA unit(s). The fields in this register are as follows:
Offset = 80h + (j * 100h); where
j = 0h to 3Bh for NAVSS0_UDMASS_UDMAP0_CFG_TCHAN
j = 0h to 2Fh for MCU_NAVSS0_UDMASS_UDMAP0_TCHAN
Instance | Physical Address |
---|---|
NAVSS0_UDMASS_UDMAP0_CFG_TCHAN | 30B0 0080h + formula |
MCU_NAVSS0_UDMASS_UDMAP0_TCHAN | 284A 0080h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | PRIORITY | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1-0 | PRIORITY | R/W | 0h | Tx Scheduling Priority: These bits select which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. This field is encoded as follows: 0 = High priority 1 = Medium - high priority 2 = Medium - low priority 3 = Low priority Arbitration between bins is performed in a strict priority fashion. High priority channels will always be serviced first. If no high priority channels are requesting then all medium-high priority channels will be serviced next. If no high priority or medium-high priority channels are requesting then all medium-low priority channels will be serviced next. When no other channels are requesting, the low priority channels will be serviced. All channels within a given bin are serviced in a round robin order. Only channels which are enabled and which have sufficient free space in their Per Channel FIFO will be included in the round robin arbitration. |