SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-4727 lists the memory-mapped registers for the MMCSD1 RX RAM ECC Aggregator. All register offset addresses not listed in Table 12-4727 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 6000h |
Offset | Acronym | Register Name | MMCSD1_ECC_AGGR_RXMEM Physical Address |
---|---|---|---|
0h | MMCSD1_RXECC_REV | Aggregator Revision Register | 02A2 6000h |
8h | MMCSD1_RXECC_VECTOR | ECC Vector Register | 02A2 6008h |
Ch | MMCSD1_RXECC_STAT | Misc Status Register | 02A2 600Ch |
3Ch | MMCSD1_RXECC_SEC_EOI_REG | SEC EOI Register | 02A2 603Ch |
40h | MMCSD1_RXECC_SEC_STATUS_REG0 | SEC Interrupt Status Register 0 | 02A2 6040h |
80h | MMCSD1_RXECC_SEC_ENABLE_SET_REG0 | SEC Interrupt Enable Set Register 0 | 02A2 6080h |
C0h | MMCSD1_RXECC_SEC_ENABLE_CLR_REG0 | SEC Interrupt Enable Clear Register 0 | 02A2 60C0h |
13Ch | MMCSD1_RXECC_DED_EOI_REG | DED EOI Register | 02A2 613Ch |
140h | MMCSD1_RXECC_DED_STATUS_REG0 | DED Interrupt Status Register 0 | 02A2 6140h |
180h | MMCSD1_RXECC_DED_ENABLE_SET_REG0 | DED Interrupt Enable Set Register 0 | 02A2 6180h |
1C0h | MMCSD1_RXECC_DED_ENABLE_CLR_REG0 | DED Interrupt Enable Clear Register 0 | 02A2 61C0h |
200h | MMCSD1_RXECC_AGGR_ENABLE_SET | Aggregator Interrupt Enable Set Register | 02A2 6200h |
204h | MMCSD1_RXECC_AGGR_ENABLE_CLR | Aggregator Interrupt Enable Clear Register | 02A2 6204h |
208h | MMCSD1_RXECC_AGGR_STATUS_SET | Aggregator Interrupt Status Set Register | 02A2 6208h |
20Ch | MMCSD1_RXECC_AGGR_STATUS_CLR | Aggregator Interrupt Status Clear Register | 02A2 620Ch |
MMCSD1_RXECC_REV is shown in Figure 12-2436 and described in Table 12-4729.
Return to Summary Table.
Aggregator Revision Register
Revision parameters.
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 6000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | MODULE_ID | |||||||||||||
R-1h | R-2h | R-6A0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REVRTL | REVMAJ | CUSTOM | REVMIN | ||||||||||||
R-1Dh | R-2h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | Business Unit |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 1Dh | RTL Version |
10-8 | REVMAJ | R | 2h | Major Version |
7-6 | CUSTOM | R | 0h | Custom Version |
5-0 | REVMIN | R | 0h | Minor Version |
MMCSD1_RXECC_VECTOR is shown in Figure 12-2437 and described in Table 12-4731.
Return to Summary Table.
ECC Vector Register
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 6008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Read Done Status to indicate if read on the serial ECC interface is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read Address |
15 | RD_SVBUS | R/W1S | 0h | Read Trigger Write 1h to trigger a read on the serial ECC interface. |
14-11 | RESERVED | R | 0h | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | ECC RAM ID Value written to select the corresponding ECC RAM for control or status. |
MMCSD1_RXECC_STAT is shown in Figure 12-2438 and described in Table 12-4733.
Return to Summary Table.
Misc Status Register
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 600Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-1h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-0 | NUM_RAMS | R | 1h | Indicates the number of RAMs serviced by the ECC aggregator. |
MMCSD1_RXECC_SEC_EOI_REG is shown in Figure 12-2439 and described in Table 12-4735.
Return to Summary Table.
SEC EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 603Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | SEC EOI |
MMCSD1_RXECC_SEC_STATUS_REG0 is shown in Figure 12-2440 and described in Table 12-4737.
Return to Summary Table.
SEC Interrupt Status Register 0
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 6040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXMEM_PEND | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RXMEM_PEND | R/W1S | 0h | Interrupt Pending Status for rxmem_pend |
MMCSD1_RXECC_SEC_ENABLE_SET_REG0 is shown in Figure 12-2441 and described in Table 12-4739.
Return to Summary Table.
SEC Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 6080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXMEM_ENABLE_SET | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RXMEM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for rxmem_pend |
MMCSD1_RXECC_SEC_ENABLE_CLR_REG0 is shown in Figure 12-2442 and described in Table 12-4741.
Return to Summary Table.
SEC Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 60C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXMEM_ENABLE_CLR | ||||||
R-0h | R/W1C-0h | ||||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RXMEM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for rxmem_pend |
MMCSD1_RXECC_DED_EOI_REG is shown in Figure 12-2443 and described in Table 12-4743.
Return to Summary Table.
DED EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 613Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | DED EOI |
MMCSD1_RXECC_DED_STATUS_REG0 is shown in Figure 12-2444 and described in Table 12-4745.
Return to Summary Table.
DED Interrupt Status Register 0
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 6140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXMEM_PEND | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RXMEM_PEND | R/W1S | 0h | Interrupt Pending Status for rxmem_pend |
MMCSD1_RXECC_DED_ENABLE_SET_REG0 is shown in Figure 12-2445 and described in Table 12-4747.
Return to Summary Table.
DED Interrupt Enable Set Register 0
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 6180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXMEM_ENABLE_SET | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RXMEM_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set for rxmem_pend |
MMCSD1_RXECC_DED_ENABLE_CLR_REG0 is shown in Figure 12-2446 and described in Table 12-4749.
Return to Summary Table.
DED Interrupt Enable Clear Register 0
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 61C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RXMEM_ENABLE_CLR | ||||||
R-0h | R/W1C-0h | ||||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | RXMEM_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear for rxmem_pend |
MMCSD1_RXECC_AGGR_ENABLE_SET is shown in Figure 12-2447 and described in Table 12-4751.
Return to Summary Table.
Aggregator Interrupt Enable Set Register
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 6200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | Interrupt enable set for serial ECC interface timeout errors |
0 | PARITY | R/W1S | 0h | Interrupt enable set for parity errors |
MMCSD1_RXECC_AGGR_ENABLE_CLR is shown in Figure 12-2448 and described in Table 12-4753.
Return to Summary Table.
Aggregator Interrupt Enable Clear Register
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 6204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | Interrupt enable clear for serial ECC interface timeout errors |
0 | PARITY | R/W1C | 0h | Interrupt enable clear for parity errors |
MMCSD1_RXECC_AGGR_STATUS_SET is shown in Figure 12-2449 and described in Table 12-4755.
Return to Summary Table.
Aggregator Interrupt Status Set Register
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 6208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | Interrupt status set for serial ECC interface timeout errors |
1-0 | PARITY | R/Wincr | 0h | Interrupt status set for parity errors |
MMCSD1_RXECC_AGGR_STATUS_CLR is shown in Figure 12-2450 and described in Table 12-4757.
Return to Summary Table.
Aggregator Interrupt Status Clear Register
Instance | Physical Address |
---|---|
MMCSD1_ECC_AGGR_RXMEM | 02A2 620Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W-0h | R/W-0h | |||||
LEGEND: R = Read Only; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | Interrupt status clear for serial ECC interface timeout errors |
1-0 | PARITY | R/Wdecr | 0h | Interrupt status clear for parity errors |