SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-5397 lists the memory-mapped registers for the GTC0_GTC_CFG0. All register offset addresses not listed in Table 12-5397 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
GTC0_GTC_CFG0 | 00A8 0000h |
Offset | Acronym | Register Name | GTC0_GTC_CFG0 Physical Address |
---|---|---|---|
0h | GTC_PID | Generic control MMR peripheral ID register | 00A8 0000h |
4h | GTC_GTC_PID | GTC peripheral ID register | 00A8 0004h |
8h | GTC_PUSHEVT | Push event select register | 00A8 0008h |
GTC_PID is shown in Figure 12-2826 and described in Table 12-5399.
Return to Summary Table.
This is the standard platform IP revision register which contains the ID and revision information of the MMR generator.
Instance | Physical Address |
---|---|
GTC0_GTC_CFG0 | 00A8 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-61800209h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 61800209h | TI internal data. Identifies revision of peripheral. |
GTC_GTC_PID is shown in Figure 12-2827 and described in Table 12-5401.
Return to Summary Table.
This is the standard platform IP revision register which contains the ID and revision information of the GTC peripheral.
Instance | Physical Address |
---|---|
GTC0_GTC_CFG0 | 00A8 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-X | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | X | TI internal data. Identifies revision of peripheral. |
GTC_PUSHEVT is shown in Figure 12-2828 and described in Table 12-5403.
Return to Summary Table.
Selects which bit of the count value to output as a push event for global timesync.
Instance | Physical Address |
---|---|
GTC0_GTC_CFG0 | 00A8 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EXPBIT_SEL | ||||||||||||||
R-0h | R/W-0h | ||||||||||||||
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R | 0h | Reserved. Always read as 0. |
5-0 | EXPBIT_SEL | R/W | 0h | This field controls the mux that selects which bit [63:0] of the system counter value is exported on the push event output. 0h = Select CNTR[0] 1h = Select CNTR[1] ... 3Fh = Select CNTR]63] |