SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-5425 lists the memory-mapped registers for the GTC0_GTC_CFG3. All register offset addresses not listed in Table 12-5425 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
GTC0_GTC_CFG3 | 00AB 0000h |
Offset | Acronym | Register Name | GTC0_GTC_CFG3 Physical Address |
---|---|---|---|
8h | GTC_CNTTIDR | Counter-timer ID register | 00AB 0000h |
GTC_CNTTIDR is shown in Figure 12-2837 and described in Table 12-5427.
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Indicates the implemented timers in the memory map and their features. Because the platform does not implement memory-mapped timers, this register is set to all 0s.
Instance | Physical Address |
---|---|
GTC_R10_CFG1 | 00AB 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FRAME7 | FRAME6 | FRAME5 | FRAME4 | ||||||||||||
R-0h | R-0h | R-0h | R-0h | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
FRAME3 | FRAME2 | FRAME1 | FRAME0 | ||||||||||||
R-0h | R-0h | R-0h | R-0h | ||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | FRAME7 | R | 0h | Indicates the features of timer frame 7 |
27-24 | FRAME6 | R | 0h | Indicates the features of timer frame 6 |
23-20 | FRAME5 | R | 0h | Indicates the features of timer frame 5 |
19-16 | FRAME4 | R | 0h | Indicates the features of timer frame 4 |
15-12 | FRAME3 | R | 0h | Indicates the features of timer frame 3 |
11-8 | FRAME2 | R | 0h | Indicates the features of timer frame 2 |
7-4 | FRAME1 | R | 0h | Indicates the features of timer frame 1 |
3-0 | FRAME0 | R | 0h | Indicates the features of timer frame 0 |