Packet fill can be enabled (CPSW_PN_EST_CONTROL_REG_k[8] EST_FILL_EN = 1h) to occur in the fetch count time associated with a fetched zero allow. The intention with fill is that a smaller packet on a non-timed priority might be able to be inserted on the wire during the wire clear time which would increase wire utilization. Fill is intended to be used with either only express priorities in the previous non-zero fetched allow, or only prempt priorities in the previous non-zero fetched allow but not both. Fill must be configured to ensure that any fill packet does not conflict with the timed express packet allowed in the next fetch.
- Express fill:
- CPSW_PN_EST_CONTROL_REG_k[8] EST_FILL_EN is set and
- A fetch contains a non-zero fetch count with a zero fetch allow, and
- The previous allow contained only express priorities.
- The fetch count loaded should be at least TBD clocks and the CPSW_PN_EST_CONTROL_REG_k[25-16] EST_FILL_MARGIN should be at least TBD clocks in Gigabit mode to ensure that the wire is cleared for the timed express packet allowed in the next fetch.
- The fetch count loaded should be at least TBD clocks and the CPSW_PN_EST_CONTROL_REG_k[25-16] EST_FILL_MARGIN should be at least TBD clocks in 10/100Mbps mode to ensure that the wire is cleared for the timed express packet allowed in the next fetch.
- Prempt fill:
- CPSW_PN_EST_CONTROL_REG_k[8] EST_FILL_EN is set and
- A fetch contains a non-zero fetch count with a zero fetch allow, and
- The previous allow contained only prempt priorities
- The fetch count loaded should be at least TBD clocks in Gigabit mode to ensure that the wire is cleared for the timed express packet allowed in the next fetch.
- The fetch count loaded should be at least TBD clocks in 10/100Mbps mode to ensure that the wire is cleared for the timed express packet allowed in the next fetch.
- Express non-fill:
- CPSW_PN_EST_CONTROL_REG_k[8] EST_FILL_EN is clear and
- The previous allow contained only express priorities.
- The fetch count loaded should be at least TBD clocks in Gigabit mode to ensure that the wire is cleared for the timed express packet allowed in the next fetch.
- The fetch count loaded should be at least TBD clocks in 10/100Mbps mode to ensure that the wire is cleared for the timed express packet allowed in the next fetch.
- Prempt non-fill:
- CPSW_PN_EST_CONTROL_REG_k[8] EST_FILL_EN is clear and
- The previous allow contained only prempt priorities.
- The fetch count loaded should be at least TBD clocks in Gigabit mode to ensure that the wire is cleared for the timed express packet allowed in the next fetch.
- The fetch count loaded should be at least TBD clocks in 10/100Mbps mode to ensure that the wire is cleared for the timed express packet allowed in the next fetch.