SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The R5FSS is a dual-core implementation of the Arm® Cortex®-R5F processor configured for split/lock operation. It also includes accompanying memories (L1 caches and tightly-coupled memories), standard Arm CoreSight™ debug and trace architecture, integrated vectored interrupt manager (VIM), ECC aggregators, and various other modules for protocol conversion and address translation for easy integration into the SoC.
There are two R5FSS modules in the device. Table 6-156 shows R5FSS modules allocation within device domains.
Module Instance | Domain | ||
---|---|---|---|
WKUP | MCU | MAIN | |
MCU_R5FSS0 | – | ✓ | – |
R5FSS0 | – | – | ✓ |