SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
LSB/MSB accesses cannot be interleaved (that is, the sequence LSB register 1, LSB register 2, MSB register 1, MSB register 2 is not supported).
The TIMER_TCRR is a 32-bit “atomic datum” and its 16-bit capture is done on the 16-bit LSB first to allow atomic LSB16 + MSB16 capture. This capture scheme is also performed for the TIMER_TCAR1 and TIMER_TCAR2 registers as they can be changed due to internal processes too.