SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 9-87 shows the mapping of Compute Cluster internal events to the Compute Cluster SoC event outputs.
Output Input Line | Interrupt ID | Internal Interrupt |
---|---|---|
COMPUTE_CLUSTER0_MSMC_EN_SOC_EVENTS_OUT_LEVEL_0 - COMPUTE_CLUSTER0_MSMC_EN_SOC_EVENTS_OUT_LEVEL_7 | 0-7 | RESERVED |
COMPUTE_CLUSTER0_MSMC_EN_SOC_EVENTS_OUT_LEVEL_8 | 8 | ARM0_DFT_PBIST_CPU_ERROR_INTR |
COMPUTE_CLUSTER0_MSMC_EN_SOC_EVENTS_OUT_LEVEL_9 | 9 | ARM1_DFT_PBIST_CPU_ERROR_INTR |
COMPUTE_CLUSTER0_MSMC_EN_SOC_EVENTS_OUT_LEVEL_10 - COMPUTE_CLUSTER0_MSMC_EN_SOC_EVENTS_OUT_LEVEL_15 | 10-15 | RESERVED |
COMPUTE_CLUSTER0_MSMC_EN_SOC_EVENTS_OUT_LEVEL_16 | 16 | MSMC_CTSET_INTR |
COMPUTE_CLUSTER0_MSMC_EN_SOC_EVENTS_OUT_LEVEL_17 - COMPUTE_CLUSTER0_MSMC_EN_SOC_EVENTS_OUT_LEVEL_23 | 17-23 | RESERVED |
COMPUTE_CLUSTER0_MSMC_EN_SOC_EVENTS_OUT_LEVEL_24 | 24 | MSMC_NULL_SLAVE_ERROR |
COMPUTE_CLUSTER0_MSMC_EN_SOC_EVENTS_OUT_LEVEL_25 - COMPUTE_CLUSTER0_MSMC_EN_SOC_EVENTS_OUT_LEVEL_127 | 25-127 | RESERVED |