SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Data bus inversion is supported in the DDR PHY. The PHY only passes the DBI information between the DDR controller and SDRAM devices. It does not perform DBI generation and decode. If the DDRSS_PHY_102[8] PHY_DBI_MODE_0 bit is set to 0x1 the SDRAM DBI information for slice 0 is passed to the DDR controller. The following bits are associated with the other slices: