SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Two PLL Controllers are implemented in the device - PLLCTRL0 and WKUP_PLL_CTRL0. They are respectively related to PLL0 and MCU_PLL0. The PLL Controllers manage the clock ratios, alignment, and gating for the system clocks.
PLLCTRL_POSTDIV is not supported in this family of devices.
The PLL Controllers registers can be accessed by any master in the device.
A SYSCLK0 clock out of a PLLCTRL is the only synchronous clock in that domain. That means - MCU_SYSCLK0 out of WKUP_PLLCTRL is the synchronous CBASS clock in MCU domain and SYSCLK0 out of Main PLLCTRL is the synchronous CBASS clock in Main domain.