SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
MSMC sets the associated bit in the MSMC_SMIRSTAT register when a software or hardware event occurs. Software can trigger the event by setting the corresponding bit in the MSMC_SMIRWS register. MSMC keeps the MSMC_SMIRSTAT bit asserted until software clears it by setting the corresponding bit in MSMC_SMIRC. Both MSMC_SMIRWS and MSMC_SMIRC are write-only registers and do not implement any actual state.