SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-1757 lists the memory-mapped registers for the CPSW0_NUSS SS registers. All register offset addresses not listed in Table 12-1757 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
CPSW0_NUSS_SS | 0C00 0000h |
Offset | Acronym | Register Name | CPSW0_NUSS_SS Physical Address |
---|---|---|---|
0h | CPSW_SS_CPSW_NUSS_IDVER_REG | ID Version Register | 0C00 0000h |
4h | CPSW_SS_SYNCE_COUNT_REG | SyncE Count Register | 0C00 0004h |
8h | CPSW_SS_SYNCE_MUX_REG | SyncE Mux Select Register | 0C00 0008h |
Ch | CPSW_SS_CONTROL_REG | Subsystem Control Register | 0C00 000Ch |
10h | CPSW_SS_SGMII_NON_FIBER_MODE_REG | SGMII NON FIBER Mode Register | 0C00 0010h |
14h | CPSW_SS_SERDES_RESET_ISO_REG | SyncE Mux Register | 0C00 0014h |
1Ch | CPSW_SS_SUBSSYSTEM_STATUS_REG | Subsystem Status Register | 0C00 001Ch |
20h | CPSW_SS_SUBSYSTEM_CONFIG_REG | Subsystem Configuration Register | 0C00 0020h |
30h | CPSW_SS_RGMII1_STATUS_REG | RGMII Port 1 Status Register | 0C00 0030h |
34h | CPSW_SS_RGMII2_STATUS_REG | RGMII Port 2 Status Register | 0C00 0034h |
38h | CPSW_SS_RGMII3_STATUS_REG | RGMII Port 3 Status Register | 0C00 0038h |
3Ch | CPSW_SS_RGMII4_STATUS_REG | RGMII Port 4 Status Register | 0C00 003Ch |
60h | CPSW_SS_QSGMII_CONTROL_REG | QSGMII Control Register | 0C00 0060h |
64h | CPSW_SS_QSGMII_STATUS_REG | QSGMII Status Register | 0C00 0064h |
74h | CPSW_SS_STATUS_XGMII_LINK_REG | XGMII Link Status Register | 0C00 0074h |
78h | CPSW_SS_STATUS_SGMII_LINK_REG | SGMII Link Status Register | 0C00 0078h |
80h | CPSW_SS_SUBSYSTEM_USXGMII0_CONTROL | USXGMII0 Control Register | 0C00 0080h |
CPSW_SS_CPSW_NUSS_IDVER_REG is shown in Figure 12-920 and described in Table 12-1759.
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ID Version Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
IDENT | |||||||||||||||
R-6BA0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL_VER | MAJOR_VER | MINOR_VER | |||||||||||||
R-4h | R-1h | R-2h | |||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | IDENT | R | 6BA0h | Identification value |
15-11 | RTL_VER | R | 4h | RTL version value |
10-8 | MAJOR_VER | R | 1h | Major version value |
7-0 | MINOR_VER | R | 2h | Minor version value |
CPSW_SS_SYNCE_COUNT_REG is shown in Figure 12-921 and described in Table 12-1761.
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SyncE Count Register
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SYNCE_CNT | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | SYNCE_CNT | R/W | 0h | Sync E Count Value |
CPSW_SS_SYNCE_MUX_REG is shown in Figure 12-922 and described in Table 12-1763.
Return to Summary Table.
SyncE Mux Register
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SYNCE_SEL | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-6 | RESERVED | R/W | X | |
5-0 | SYNCE_SEL | R/W | 0h | Sync E Select Value |
CPSW_SS_CONTROL_REG is shown in Figure 12-923 and described in Table 12-1765.
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Control Register
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EEE_PHY_ONLY | EEE_EN | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R/W | X | |
1 | EEE_PHY_ONLY | R/W | 0h | Energy Efficient Enable Phy Only Mode: |
0 | EEE_EN | R/W | 0h | Energy Efficient Ethernet Enable: |
CPSW_SS_SGMII_NON_FIBER_MODE_REG is shown in Figure 12-924 and described in Table 12-1767.
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SGMII NON FIBER Mode Register
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SGMII_NON_FIBER_MODE | ||||||
R/W-X | R/W-Fh | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-0 | SGMII_NON_FIBER_MODE | R/W | Fh | This register bit goes to the CPSGMII mode input only |
CPSW_SS_SERDES_RESET_ISO_REG is shown in Figure 12-925 and described in Table 12-1769.
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SyncE Mux Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0014h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SERDES_RESET_ISO | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | X | |
3-0 | SERDES_RESET_ISO | R/W | 0h | These bits control whether the SERDES ignores the hard reset for isolation or not |
CPSW_SS_SUBSSYSTEM_STATUS_REG is shown in Figure 12-926 and described in Table 12-1771.
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Subsystem Status Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 001Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EEE_CLKSTOP_ACK | ||||||
R-X | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | X | |
0 | EEE_CLKSTOP_ACK | R | 0h | Energy Efficient Ethernet clockstop acknowledge from CPSW. |
CPSW_SS_SUBSYSTEM_CONFIG_REG is shown in Figure 12-927 and described in Table 12-1773.
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Subsystem Configuration Register
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0020h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | XGMII | ||||||
R-X | R-1h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
XGMII | QSGMII | SGMII | RGMII | RMII | |||
R-1h | R-1h | R-1h | R-1h | R-1h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | NUM_GENF | ||||||
R-X | R-2h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
NUM_PORTS | |||||||
R-5h | |||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-28 | RESERVED | R | X | |
27-20 | XGMII | R | 1h | The Number of XGMII Ports included in the CPSW_NUSS |
19 | QSGMII | R | 1h | QSGMII is included in the CPSW_NUSS |
18 | SGMII | R | 1h | SGMII is included in the CPSW_NUSS |
17 | RGMII | R | 1h | RGMII is included in the CPSW_NUSS |
16 | RMII | R | 1h | RMII is included in the CPSW_NUSS |
15-13 | RESERVED | R | X | |
12-8 | NUM_GENF | R | 2h | The number of CPTS GENF outputs |
7-0 | NUM_PORTS | R | 5h | The total number of ports including the host port 0 |
CPSW_SS_RGMII1_STATUS_REG is shown in Figure 12-928 and described in Table 12-1775.
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RGMII Port 1 Status Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0030h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FULLDUPLEX | SPEED | LINK | ||||
R-X | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | X | |
3 | FULLDUPLEX | R | 0h | RGMII Port 1 full duplex: |
2-1 | SPEED | R | 0h | RGMII Port 1 speed: |
0 | LINK | R | 0h | RGMII Port 1 link indicator: |
CPSW_SS_RGMII2_STATUS_REG is shown in Figure 12-929 and described in Table 12-1777.
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RGMII Port 2 Status Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0034h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FULLDUPLEX | SPEED | LINK | ||||
R-X | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | X | |
3 | FULLDUPLEX | R | 0h | RGMII Port 2 full dulex: |
2-1 | SPEED | R | 0h | RGMII Port 2 speed: |
0 | LINK | R | 0h | RGMII Port 2 link indicator: |
CPSW_SS_RGMII3_STATUS_REG is shown in Figure 12-930 and described in Table 12-1779.
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RGMII 3 Port Status Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0038h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FULLDUPLEX | SPEED | LINK | ||||
R-X | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | X | |
3 | FULLDUPLEX | R | 0h | RGMII Port 3 full dulex: |
2-1 | SPEED | R | 0h | RGMII Port 3 speed: |
0 | LINK | R | 0h | RGMII Port 3 link indicator: |
CPSW_SS_RGMII4_STATUS_REG is shown in Figure 12-931 and described in Table 12-1781.
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RGMII Port 4 Status Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FULLDUPLEX | SPEED | LINK | ||||
R-X | R-0h | R-0h | R-0h | ||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | X | |
3 | FULLDUPLEX | R | 0h | RGMII Port 4 full dulex: |
2-1 | SPEED | R | 0h | RGMII Port 4 speed: |
0 | LINK | R | 0h | RGMII Port 4 link indicator: |
CPSW_SS_QSGMII_CONTROL_REG is shown in Figure 12-932 and described in Table 12-1783.
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QSGMII Control Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0060h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | Q0_RDCD | ||||||
R/W-X | R/W-0h | ||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | Q0_RDCD | R/W | 0h | QSGMII0 Running Disparity Check Disable |
CPSW_SS_QSGMII_STATUS_REG is shown in Figure 12-933 and described in Table 12-1785.
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QSGMII Status Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0064h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | Q0_RX_SYNC | ||||||
R-X | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | X | |
0 | Q0_RX_SYNC | R | 0h | QSGMII0 RX Sync Detected |
CPSW_SS_STATUS_XGMII_LINK_REG is shown in Figure 12-934 and described in Table 12-1787.
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XGMII Link Status Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0074h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | XGMII1_LINK | ||||||
R-X | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | X | |
0 | XGMII1_LINK | R | 0h | Port 1 XGMII Link Indicator |
CPSW_SS_STATUS_SGMII_LINK_REG is shown in Figure 12-935 and described in Table 12-1789.
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SGMII Link Status Register.
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0078h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SGMII1_LINK | ||||||
R-X | R-0h | ||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | X | |
0 | SGMII1_LINK | R | 0h | Port 1 SGMII Link Indicator |
CPSW_SS_SUBSYSTEM_USXGMII0_CONTROL is shown in Figure 12-936 and described in Table 12-1791.
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USXGMII0 Control Register
Instance | Physical Address |
---|---|
CPSW0_NUSS_SS | 0C00 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | USXGMII_HALF_RATE_PCSR | RESERVED | USXGMII_REP_RATE | ||||
R/W-X | R/W-0h | R/W-X | R/W-3h | ||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4 | USXGMII_HALF_RATE_PCSR | R/W | 0h | USXGMII Half Rate PCSR |
3 | RESERVED | R/W | X | |
2-0 | USXGMII_REP_RATE | R/W | 3h | USXGMII Rep Rate |