SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The inter-processor communication (IPC) registers are used for generating interrupts to the device cores. The IPC scheme is same as described in Section 5.1.3.3.1.4. For more details, refer to that section.
Table 5-465 summarizes the IPC registers.
IPC Register | Writing 1h to bit 0 results in: | Writing 1h to one of the bits [31-4] results in: |
---|---|---|
CTRLMMR_MCU_IPC_SET0 |
| setting that bit and the corresponding IPC_SRC_CLR bit to 1h |
CTRLMMR_MCU_IPC_SET1 |
| setting that bit and the corresponding IPC_SRC_CLR bit to 1h |
CTRLMMR_MCU_IPC_SET8 |
| setting that bit and the corresponding IPC_SRC_CLR bit to 1h |
CTRLMMR_MCU_IPC_CLR0 |
| clearing (set to 0h) that bit and the corresponding IPC_SRC_SET bit |
CTRLMMR_MCU_IPC_CLR1 |
| clearing (set to 0h) that bit and the corresponding IPC_SRC_SET bit |
CTRLMMR_MCU_IPC_CLR8 |
| clearing (set to 0h) that bit and the corresponding IPC_SRC_SET bit |
For latency reasons the IPC registers are not write protected by KICK registers which means that they can be written to without a need for performing unlocking procedure as described in Section 5.1.3.3.1.2.