SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
A single MCU_UART0 module is integrated in the device MCU domain. Figure 12-405 shows the integration of MCU_UART0.
Table 12-735 through Table 12-737 summarize the integration of MCU_UART0 in the device MCU domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
MCU_UART0 | WKUP_PSC0 | PD0 | LPSC0 | MCU_CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
MCU_UART0 | MCU_UART0_CLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | MCU_UART0 interface clock |
MCU_UART0_FCLK | MCU_PLL1_HSDIV3_CLKOUT | MCU_PLL1 | MCU_UART0 functional clock. Output of multiplexer, see Figure 12-405, MCU_UART0 Integration. Multiplexer control is provided via CTRLMMR_MCU_USART_CLKSEL[0] CLK_SEL bit field. | |
MAIN_PLL1_HSDIV5_CLKOUT | PLL1 | |||
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
MCU_UART0 | MCU_UART0_RST | MOD_G_RST | LPSC0 | MCU_UART0 reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
MCU_UART0 | MCU_UART0_USART_IRQ_0 | GIC500_SPI_IN_878 | COMPUTE_CLUSTER0 | MCU_UART0 interrupt request | Level |
WKUP_DMSC0_INTR_IN_47 | WKUP_DMSC0 | ||||
R5FSS0_CORE0_INTR_IN_467 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_467 | R5FSS0_CORE1 | ||||
MCU_R5FSS0_CORE0_INTR_IN_30 | MCU_R5FSS0_CORE0 | ||||
MCU_R5FSS0_CORE1_INTR_IN_30 | MCU_R5FSS0_CORE1 | ||||
DMA Events | |||||
Module Instance | Module DMA Event | Destination DMA Event Input | Destination | Description | Type |
MCU_UART0 | MCU_USART0_DMA0 | MCU_USART0_TX | MCU_PDMA0 | MCU_UART0 transmit request line | Level |
MCU_USART0_DMA1 | MCU_USART0_RX | MCU_PDMA0 | MCU_UART0 receive request line | Level |
UART interrupts are further described in Section 12.1.6.4.5, UART Interrupt Requests.
UART DMA events are further described in Section 12.1.6.4.6.4, FIFO DMA Mode Operation.