SPRUIU1C July   2020  – February 2024 DRA821U , DRA821U-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation From Texas Instruments
    3.     Support Resources
    4.     Glossary
    5.     Export Control Notice
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Device Overview
    2. 1.2 Device Block Diagram
    3. 1.3 Device Main Domain
      1. 1.3.1  Arm Cortex-A72 Subsystem
      2. 1.3.2  Arm Cortex-R5F Processor
      3. 1.3.3  Navigator Subsystem
      4. 1.3.4  Region-based Address Translation Module
      5. 1.3.5  Multicore Shared Memory Controller
      6. 1.3.6  DDR Subsystem
      7. 1.3.7  General Purpose Input/Output Interface
      8. 1.3.8  Inter-Integrated Circuit Interface
      9. 1.3.9  Improved Inter-Integrated Circuit Interface
      10. 1.3.10 Multi-channel Serial Peripheral Interface
      11. 1.3.11 Universal Asynchronous Receiver/Transmitter
      12. 1.3.12 Gigabit Ethernet Switch
      13. 1.3.13 Peripheral Component Interconnect Express Subsystem
      14. 1.3.14 Universal Serial Bus (USB) Subsystem
      15. 1.3.15 SerDes
      16. 1.3.16 General Purpose Memory Controller with Error Location Module
      17. 1.3.17 Multimedia Card/Secure Digital Interface
      18. 1.3.18 Enhanced Capture Module
      19. 1.3.19 Enhanced Pulse-Width Modulation Module
      20. 1.3.20 Enhanced Quadrature Encoder Pulse Module
      21. 1.3.21 Controller Area Network
      22. 1.3.22 Audio Tracking Logic
      23. 1.3.23 Multi-channel Audio Serial Port
      24. 1.3.24 Timers
      25. 1.3.25 Internal Diagnostics Modules
    4. 1.4 Device MCU Domain
      1. 1.4.1  MCU Arm Cortex-R5F Processor
      2. 1.4.2  MCU Region-based Address Translation Module
      3. 1.4.3  MCU Navigator Subsystem
      4. 1.4.4  MCU Analog-to-Digital Converter
      5. 1.4.5  MCU Inter-Integrated Circuit Interface
      6. 1.4.6  MCU Improved Inter-Integrated Circuit Interface
      7. 1.4.7  MCU Multi-channel Serial Peripheral Interface
      8. 1.4.8  MCU Universal Asynchronous Receiver/Transmitter
      9. 1.4.9  MCU Gigabit Ethernet Switch
      10. 1.4.10 MCU Octal Serial Peripheral Interface and HyperBus Memory Controller as a Flash Subsystem
      11. 1.4.11 MCU Controller Area Network
      12. 1.4.12 MCU Timers
      13. 1.4.13 MCU Internal Diagnostics Modules
    5. 1.5 Device WKUP Domain
      1. 1.5.1 WKUP Device Management and Security Controller
      2. 1.5.2 WKUP General Purpose Input/Output Interface
      3. 1.5.3 WKUP Inter-Integrated Circuit Interface
      4. 1.5.4 WKUP Universal Asynchronous Receiver/Transmitter
      5. 1.5.5 WKUP Internal Diagnostics Modules
    6. 1.6 Device Identification
  4. 2 Memory Map
    1. 2.1 MAIN Domain Memory Map
    2. 2.2 MCU Domain Memory Map
    3. 2.3 WKUP Domain Memory Map
    4. 2.4 Processors View Memory Map
    5. 2.5 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1 System Interconnect Overview
    2. 3.2 System Interconnect Integration
      1. 3.2.1 Interconnect Integration in WKUP Domain
      2. 3.2.2 Interconnect Integration in MCU Domain
      3. 3.2.3 Interconnect Integration in MAIN Domain
    3. 3.3 System Interconnect Functional Description
      1. 3.3.1 Master-Slave Connections
      2. 3.3.2 Quality of Service (QoS)
      3. 3.3.3 Route ID
      4. 3.3.4 Initiator-Side Security Controls and Firewalls
        1. 3.3.4.1 Initiator-Side Security Controls (ISC)
          1. 3.3.4.1.1 Special System Level Priv-ID
          2. 3.3.4.1.2 Priv ID and ISC Assignment
        2. 3.3.4.2 Firewalls (FW)
          1. 3.3.4.2.1 Peripheral Firewalls (FW)
          2. 3.3.4.2.2 Memory or Region-based Firewalls
            1. 3.3.4.2.2.1 Region Based Firewall Functional Description
          3. 3.3.4.2.3 Channelized Firewalls
            1. 3.3.4.2.3.1 Channelized Firewall Functional Description
      5. 3.3.5 Null Error Reporting
      6. 3.3.6 VBUSM_TIMEOUT_GASKET (MCU_TIMEOUT_64B2)
        1. 3.3.6.1 Overview and Feature List
          1. 3.3.6.1.1 Features Supported
          2. 3.3.6.1.2 Features Not Supported
        2. 3.3.6.2 Functional Description
          1. 3.3.6.2.1 Functional Operation
            1. 3.3.6.2.1.1  Overview
            2. 3.3.6.2.1.2  FIFOs
            3. 3.3.6.2.1.3  ID Allocator
            4. 3.3.6.2.1.4  Timer
            5. 3.3.6.2.1.5  Timeout Queue
            6. 3.3.6.2.1.6  Write Scoreboard
            7. 3.3.6.2.1.7  Read Scoreboard
            8. 3.3.6.2.1.8  Flush Mode
            9. 3.3.6.2.1.9  Flushing
            10. 3.3.6.2.1.10 Timeout Error Reporting
            11. 3.3.6.2.1.11 Command Timeout Error Reporting
            12. 3.3.6.2.1.12 Unexpected Response Reporting
            13. 3.3.6.2.1.13 Latency and Stalls
            14. 3.3.6.2.1.14 Bypass
            15. 3.3.6.2.1.15 Safety
        3. 3.3.6.3 Interrupt Conditions
          1. 3.3.6.3.1 Transaction Error Interrupt
            1. 3.3.6.3.1.1 Transaction Timeout
            2. 3.3.6.3.1.2 Unexpected Response
            3. 3.3.6.3.1.3 Command Timeout
        4. 3.3.6.4 Memory Map
          1. 3.3.6.4.1  Revision Register (Base Address + 0x00)
          2. 3.3.6.4.2  Configuration Register (Base Address + 0x04)
          3. 3.3.6.4.3  Info Register (Base Address + 0x08)
          4. 3.3.6.4.4  Enable Register (Base Address + 0x0C)
          5. 3.3.6.4.5  Flush Register (Base Address + 0x10)
          6. 3.3.6.4.6  Timeout Value Register (Base Address + 0x14)
          7. 3.3.6.4.7  Timer Register (Base Address + 0x18)
          8. 3.3.6.4.8  Error Interrupt Raw Status/Set Register (Base Address + 0x20)
          9. 3.3.6.4.9  Error Interrupt Enabled Status/Clear Register (Base Address + 0x24)
          10. 3.3.6.4.10 Error Interrupt Mask Set Register (Base Address + 0x28)
          11. 3.3.6.4.11 Error Interrupt Mask Clear Register (Base Address + 0x2C)
          12. 3.3.6.4.12 Timeout Error Info Register (Base Address + 0x30)
          13. 3.3.6.4.13 Unexpected Response Info Register (Base Address + 0x34)
          14. 3.3.6.4.14 Error Transaction Valid/Dir/RouteID Register (Base Address + 0x38)
          15. 3.3.6.4.15 Error Transaction Tag/CommandID Register (Base Address + 0x3C)
          16. 3.3.6.4.16 Error Transaction Bytecnt Register (Base Address + 0x40)
          17. 3.3.6.4.17 Error Transaction Upper Address Register (Base Address + 0x44)
          18. 3.3.6.4.18 Error Transaction Lower Address Register (Base Address + 0x48)
        5. 3.3.6.5 Integration Overview
          1. 3.3.6.5.1 Parameterization Requirements
        6. 3.3.6.6 I/O Description
          1. 3.3.6.6.1 Clockstop Idle
          2. 3.3.6.6.2 Flush
          3. 3.3.6.6.3 Module I/O
        7. 3.3.6.7 User’s Guide
          1. 3.3.6.7.1 Programmer’s Guide
            1. 3.3.6.7.1.1 Initialization
            2. 3.3.6.7.1.2 Software Flush
      7. 3.3.7 Timeout Gasket (TOG)
    4. 3.4 System Interconnect Registers
      1. 3.4.1 QoS Registers
      2. 3.4.2 Firewall Exception Registers
      3. 3.4.3 Firewall Region Registers
      4. 3.4.4 Null Error Reporting Registers
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Terminology
    2. 4.2 Boot Process
      1. 4.2.1 MCU ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 DMSC ROM Description
      3. 4.2.3 Boot Process Flow
      4. 4.2.4 MCU Only vs Normal Boot
    3. 4.3 Boot Mode Pins
      1. 4.3.1  MCU_BOOTMODE Pin Mapping
      2. 4.3.2  BOOTMODE Pin Mapping
        1. 4.3.2.1 Primary Boot Mode Selection
        2. 4.3.2.2 Backup Boot Mode Selection When MCU Only = 0
        3. 4.3.2.3 Primary Boot Mode Configuration
        4. 4.3.2.4 Backup Boot Mode Configuration
      3. 4.3.3  No-boot/Dev-boot Configuration
      4. 4.3.4  Hyperflash Boot Device Configuration
      5. 4.3.5  OSPI Boot Device Configuration
      6. 4.3.6  QSPI Boot Device Configuration
      7. 4.3.7  SPI Boot Device Configuration
      8. 4.3.8  xSPI Boot Device Configuration
      9. 4.3.9  I2C Boot Device Configuration
      10. 4.3.10 MMC/SD Card Boot Device Configuration
      11. 4.3.11 eMMC Boot Device Configuration
      12. 4.3.12 Ethernet Boot Device Configuration
      13. 4.3.13 USB Boot Device Configuration
      14. 4.3.14 PCIe Boot Device Configuration
      15. 4.3.15 UART Boot Device Configuration
      16. 4.3.16 PLL Configuration
        1. 4.3.16.1 MCU_PLL0, MCU_PLL2, Main PLL0, and Main PLL3
        2. 4.3.16.2 MCU_PLL1
        3. 4.3.16.3 Main PLL1
        4. 4.3.16.4 Main PLL2
        5. 4.3.16.5 HSDIV Values
        6. 4.3.16.6 190
    4. 4.4 Boot Parameter Tables
      1. 4.4.1  Common Header
      2. 4.4.2  PLL Setup
      3. 4.4.3  PCIe Boot Parameter Table
      4. 4.4.4  I2C Boot Parameter Table
      5. 4.4.5  OSPI/QSPI/SPI Boot Parameter Table
      6. 4.4.6  Ethernet Boot Parameter Table
      7. 4.4.7  USB Boot Parameter Table
      8. 4.4.8  MMCSD Boot Parameter Table
      9. 4.4.9  UART Boot Parameter Table
      10. 4.4.10 Hyperflash Boot Parameter Table
    5. 4.5 Boot Image Format
      1. 4.5.1 Overall Structure
      2. 4.5.2 X.509 Certificate
      3. 4.5.3 Organizational Identifier (OID)
      4. 4.5.4 X.509 Extensions Specific to Boot
        1. 4.5.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.5.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.5.5 Extended Boot Info Extension
        1. 4.5.5.1 Impact on HS Device
        2. 4.5.5.2 Extended Boot Info Details
        3. 4.5.5.3 Certificate / Component Types
        4. 4.5.5.4 Extended Boot Encryption Info
        5. 4.5.5.5 Component Ordering
        6. 4.5.5.6 Memory Load Sections Overlap with Executable Components
        7. 4.5.5.7 Device Type and Extended Boot Extension
      6. 4.5.6 Generating X.509 Certificates
        1. 4.5.6.1 Key Generation
          1. 4.5.6.1.1 Degenerate RSA Keys
        2. 4.5.6.2 Configuration Script
      7. 4.5.7 Image Data
    6. 4.6 Boot Modes
      1. 4.6.1 I2C Bootloader Operation
        1. 4.6.1.1 I2C Initialization Process
          1. 4.6.1.1.1 Block Size
          2. 4.6.1.1.2 226
        2. 4.6.1.2 I2C Loading Process
          1. 4.6.1.2.1 Loading a Boot Image From EEPROM
      2. 4.6.2 SPI Bootloader Operation
        1. 4.6.2.1 SPI Initialization Process
        2. 4.6.2.2 SPI Loading Process
      3. 4.6.3 QSPI Bootloader Operation
        1. 4.6.3.1 QSPI Initialization Process
        2. 4.6.3.2 QSPI Loading Process
      4. 4.6.4 OSPI Bootloader Operation
        1. 4.6.4.1 OSPI Initialization Process
        2. 4.6.4.2 OSPI Loading Process
      5. 4.6.5 PCIe Bootloader Operation
        1. 4.6.5.1 PCIe Initialization Process
        2. 4.6.5.2 PCIe Loading Process
      6. 4.6.6 Ethernet Bootloader Operation
        1. 4.6.6.1 Ethernet Initialization Process
        2. 4.6.6.2 Ethernet Loading Process
          1. 4.6.6.2.1 Ethernet Boot Data Formats
            1. 4.6.6.2.1.1 Limitations
            2. 4.6.6.2.1.2 BOOTP Request
              1. 4.6.6.2.1.2.1 MAC Header (DIX)
              2. 4.6.6.2.1.2.2 IPv4 Header
              3. 4.6.6.2.1.2.3 UDP Header
              4. 4.6.6.2.1.2.4 BOOTP Payload
              5. 4.6.6.2.1.2.5 TFTP
        3. 4.6.6.3 Ethernet Hand Over Process
      7. 4.6.7 USB Bootloader Operation
        1. 4.6.7.1 USB-Specific Attributes
          1. 4.6.7.1.1 DFU Device Mode
      8. 4.6.8 MMCSD Bootloader Operation
      9. 4.6.9 UART Bootloader Operation
        1. 4.6.9.1 Initialization Process
        2. 4.6.9.2 UART Loading Process
          1. 4.6.9.2.1 UART XMODEM
        3. 4.6.9.3 UART Hand-Over Process
    7. 4.7 Boot Memory Maps
      1. 4.7.1 Memory Layout/MPU
      2. 4.7.2 Global Memory Addresses Used by ROM Code
      3. 4.7.3 Memory Reserved by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 WKUP_CTRL_MMR0
        1. 5.1.1.1 WKUP_CTRL_MMR0 Overview
        2. 5.1.1.2 WKUP_CTRL_MMR0 Integration
        3. 5.1.1.3 WKUP_CTRL_MMR0 Functional Description
          1. 5.1.1.3.1 Description for WKUP_CTRL_MMR0 Register Types
            1. 5.1.1.3.1.1  Pad Configuration Registers
            2. 5.1.1.3.1.2  Kick Protection Registers
            3. 5.1.1.3.1.3  WKUP_CTRL_MMR0 Module Interrupts
            4. 5.1.1.3.1.4  Clock Selection Registers
            5. 5.1.1.3.1.5  Device Feature Registers
            6. 5.1.1.3.1.6  POK Module Registers
            7. 5.1.1.3.1.7  Power and Reset Related Registers
            8. 5.1.1.3.1.8  PRG Related Registers
            9. 5.1.1.3.1.9  Voltage Glitch Detect Control and Status Registers
            10. 5.1.1.3.1.10 I/O Debounce Control Registers
        4. 5.1.1.4 WKUP_CTRL_MMR0 Registers
      2. 5.1.2 MCU_CTRL_MMR0
        1. 5.1.2.1 MCU_CTRL_MMR0 Overview
        2. 5.1.2.2 MCU_CTRL_MMR0 Integration
        3. 5.1.2.3 MCU_CTRL_MMR0 Functional Description
          1. 5.1.2.3.1 Description for MCU_CTRL_MMR0 Register Types
            1. 5.1.2.3.1.1 Kick Protection Registers
            2. 5.1.2.3.1.2 MCU_CTRL_MMR0 Module Interrupts
            3. 5.1.2.3.1.3 Inter-processor Communication Registers
            4. 5.1.2.3.1.4 Timer I/O Muxing Control Registers
            5. 5.1.2.3.1.5 Clock Muxing and Division Registers
            6. 5.1.2.3.1.6 MCU_CPSW0 MAC Address Registers
        4. 5.1.2.4 MCU_CTRL_MMR0 Registers
        5. 5.1.2.5 MCU_SEC_MMR0_DBG_CTRL Registers
        6. 5.1.2.6 MCU_SEC_MMR0_BOOT_CTRL Registers
      3. 5.1.3 CTRL_MMR0
        1. 5.1.3.1 CTRL_MMR0 Overview
        2. 5.1.3.2 CTRL_MMR0 Integration
        3. 5.1.3.3 CTRL_MMR0 Functional Description
          1. 5.1.3.3.1 Description for CTRL_MMR0 Register Types
            1. 5.1.3.3.1.1  Pad Configuration Registers
            2. 5.1.3.3.1.2  Kick Protection Registers
            3. 5.1.3.3.1.3  CTRL_MMR0 Module Interrupts
            4. 5.1.3.3.1.4  Inter-processor Communication Registers
            5. 5.1.3.3.1.5  Timer I/O Muxing Control Registers
            6. 5.1.3.3.1.6  EHRPWM/EQEP Control and Status Registers
            7. 5.1.3.3.1.7  Clock Muxing and Division Registers
            8. 5.1.3.3.1.8  Ethernet Port Operation Control Registers
            9. 5.1.3.3.1.9  SERDES Lane Function Control Registers
            10. 5.1.3.3.1.10 DDRSS Dynamic Frequency Change Registers
        4. 5.1.3.4 CTRL_MMR0 Registers
        5. 5.1.3.5 SEC_MMR0_DBG_CTRL Registers
        6. 5.1.3.6 SEC_MMR0_BOOT_CTRL Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 Power Management Subsystems
        1. 5.2.2.1 Power Subsystems Overview
          1. 5.2.2.1.1 POK Overview
          2. 5.2.2.1.2 PRG / PRG_PP Overview
          3. 5.2.2.1.3 POR Overview
          4. 5.2.2.1.4 POK / PRG(_PP) /POR Overview
          5. 5.2.2.1.5 Timing
          6. 5.2.2.1.6 Restrictions
        2. 5.2.2.2 Power System Modules
          1. 5.2.2.2.1 Power OK (POK) Modules
            1. 5.2.2.2.1.1 POK Programming Model
              1. 5.2.2.2.1.1.1 POK Threshold Setting Programming Sequence
          2. 5.2.2.2.2 Power on Reset (POR) Module
            1. 5.2.2.2.2.1 POR Overview
            2. 5.2.2.2.2.2 POR Integration
            3. 5.2.2.2.2.3 POR Programming Model
          3. 5.2.2.2.3 PoR/Reset Generator (PRG_PP) Modules
            1. 5.2.2.2.3.1 PRG_PP Overview
            2. 5.2.2.2.3.2 PRG_PP Integration
            3. 5.2.2.2.3.3 PRG_PP Programming Model
          4. 5.2.2.2.4 Power Glitch Detect (PGD) Modules
          5. 5.2.2.2.5 Voltage and Thermal Manager (VTM)
            1. 5.2.2.2.5.1 VTM Overview
              1. 5.2.2.2.5.1.1 VTM Features
              2. 5.2.2.2.5.1.2 VTM Not Supported Features
            2. 5.2.2.2.5.2 VTM Integration
            3. 5.2.2.2.5.3 VTM Functional Description
              1. 5.2.2.2.5.3.1 VTM Temperature Status and Thermal Management
                1. 5.2.2.2.5.3.1.1 10-bit Temperature Values Versus Temperature
              2. 5.2.2.2.5.3.2 VTM Temperature Driven Alerts and Interrupts
              3. 5.2.2.2.5.3.3 VTM VID Voltage Domains
              4. 5.2.2.2.5.3.4 VTM Clocking
              5. 5.2.2.2.5.3.5 VTM Retention Interface
              6. 5.2.2.2.5.3.6 VTM ECC Aggregator
              7. 5.2.2.2.5.3.7 VTM Programming Model
                1. 5.2.2.2.5.3.7.1 VTM Maximum Temperature Outrange Alert
                2. 5.2.2.2.5.3.7.2 Temperature Monitor during Low Power Modes
                3. 5.2.2.2.5.3.7.3 Sensors Programming Sequences
              8. 5.2.2.2.5.3.8 AVS-Class0
          6. 5.2.2.2.6 Distributed Power Clock and Reset Controller (DPCR)
        3. 5.2.2.3 Power Control Modules
          1. 5.2.2.3.1 Power Sleep Controller and Local Power Sleep Controllers
            1. 5.2.2.3.1.1 PSC Terminology
            2. 5.2.2.3.1.2 PSC Features
            3. 5.2.2.3.1.3 PSC: Device Power-Management Layout
              1. 5.2.2.3.1.3.1 WKUP_PSC0 Device-Specific Information
              2. 5.2.2.3.1.3.2 PSC0 Device-Specific Information
              3. 5.2.2.3.1.3.3 LPSC Dependences Overview
            4. 5.2.2.3.1.4 PSC: Power Domain and Module States
              1. 5.2.2.3.1.4.1 Power Domain States
              2. 5.2.2.3.1.4.2 Module States
              3. 5.2.2.3.1.4.3 Local Reset
            5. 5.2.2.3.1.5 PSC: Executing State Transitions
              1. 5.2.2.3.1.5.1 Power Domain State Transitions
              2. 5.2.2.3.1.5.2 Module State Transitions
              3. 5.2.2.3.1.5.3 Concurrent Power Domain/Module State Transitions
              4. 5.2.2.3.1.5.4 Recommendations for Power Domain/Module Sequencing
            6. 5.2.2.3.1.6 PSC: Emulation Support in the PSC
            7. 5.2.2.3.1.7 PSC: A72SS, MSMC, MCU Cortex-R5F, C71SS0, and C66SS Subsystem Power-Up and Power-Down Sequences
              1. 5.2.2.3.1.7.1 ARMi_COREn Power State Transition
              2. 5.2.2.3.1.7.2 A72SS Power State Transition
              3. 5.2.2.3.1.7.3 GIC0 Sequencing to Support A72SS Power Management
              4. 5.2.2.3.1.7.4 MSMC0 Clkstop/Powerdown/Disconnect Sequencing
              5. 5.2.2.3.1.7.5 MCU Cortex-R5F Power Modes
          2. 5.2.2.3.2 Integrated Power Management (DMSC)
            1. 5.2.2.3.2.1 DMSC Power Management Overview
              1. 5.2.2.3.2.1.1 DMSC Power Management Features
      3. 5.2.3 Device Power States
        1. 5.2.3.1 Overview of Device Low-Power Modes
        2. 5.2.3.2 Voltage Domains
        3. 5.2.3.3 Power Domains
        4. 5.2.3.4 Clock Sources States
        5. 5.2.3.5 Wake-up Sources
        6. 5.2.3.6 Device Power States and Transitions
          1. 5.2.3.6.1 LPM Entry Sequences
          2. 5.2.3.6.2 LPM Exit Sequences
          3. 5.2.3.6.3 IO Retention
          4. 5.2.3.6.4 DDRSS Self-Refresh
      4. 5.2.4 Dynamic Power Management
        1. 5.2.4.1 AVS Support
        2. 5.2.4.2 Dynamic Frequency Scaling (DFS) Operations
      5. 5.2.5 Thermal Management
      6. 5.2.6 Registers
        1. 5.2.6.1 WKUP_VTM0 Registers
        2. 5.2.6.2 PSC Registers
    3. 5.3 Reset
      1. 5.3.1 Reset Overview
      2. 5.3.2 Reset Sources
      3. 5.3.3 Reset Status
      4. 5.3.4 Reset Control
      5. 5.3.5 BOOTMODE Pins
      6. 5.3.6 Reset Sequences
        1. 5.3.6.1 MCU_PORz Overview
        2. 5.3.6.2 MCU_PORz Sequence
        3. 5.3.6.3 MCU_RESETz Sequence
        4. 5.3.6.4 PORz Sequence
        5. 5.3.6.5 RESET_REQz Sequence
      7. 5.3.7 PLL Behavior on Reset
    4. 5.4 Clocking
      1. 5.4.1 Overview
      2. 5.4.2 Clock Inputs
        1. 5.4.2.1 Overview
        2. 5.4.2.2 Mapping of Clock Inputs
      3. 5.4.3 Clock Outputs
        1. 5.4.3.1 Observation Clock Pins
          1. 5.4.3.1.1 MCU_OBSCLK0 Pin
          2. 5.4.3.1.2 424
          3. 5.4.3.1.3 OBSCLK0, OBSCLK1, and OBSCLK2 Pins
        2. 5.4.3.2 System Clock Pins
          1. 5.4.3.2.1 MCU_SYSCLKOUT0
          2. 5.4.3.2.2 SYSCLKOUT0
      4. 5.4.4 Device Oscillators
        1. 5.4.4.1 Device Oscillators Integration
          1. 5.4.4.1.1 Oscillators with External Crystal
          2. 5.4.4.1.2 Internal RC Oscillator
        2. 5.4.4.2 Oscillator Clock Loss Detection
      5. 5.4.5 PLLs
        1. 5.4.5.1 WKUP and MCU Domains PLL Overview
        2. 5.4.5.2 MAIN Domain PLLs Overview
        3. 5.4.5.3 PLL Reference Clocks
          1. 5.4.5.3.1 PLLs in MCU Domain
          2. 5.4.5.3.2 PLLs in MAIN Domain
        4. 5.4.5.4 Generic PLL Overview
          1. 5.4.5.4.1 PLLs Output Clocks Parameters
            1. 5.4.5.4.1.1 PLLs Input Clocks
            2. 5.4.5.4.1.2 PLL Output Clocks
              1. 5.4.5.4.1.2.1 PLLTS16FFCLAFRAC2 Type Output Clocks
              2. 5.4.5.4.1.2.2 PLLTS16FFCLAFRACF Type Output Clocks
              3. 5.4.5.4.1.2.3 PLL Lock
              4. 5.4.5.4.1.2.4 HSDIVIDER
              5. 5.4.5.4.1.2.5 ICG Module
              6. 5.4.5.4.1.2.6 PLL Power Down
              7. 5.4.5.4.1.2.7 PLL Calibration
          2. 5.4.5.4.2 PLL Spread Spectrum Modulation Module
            1. 5.4.5.4.2.1 Definition of SSMOD
            2. 5.4.5.4.2.2 SSMOD Configuration
        5. 5.4.5.5 PLLs Device-Specific Information
          1. 5.4.5.5.1 SSMOD Related Bitfields Table
          2. 5.4.5.5.2 Clock Synthesis Inputs to the PLLs
          3. 5.4.5.5.3 Clock Output Parameter
          4. 5.4.5.5.4 Calibration Related Bitfields
        6. 5.4.5.6 PLL and PLL Controller Connection
        7. 5.4.5.7 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.5.7.1 PLL Initialization
            1. 5.4.5.7.1.1 Kick Protection Mechanism
            2. 5.4.5.7.1.2 PLL Initialization to PLL Mode
            3. 5.4.5.7.1.3 PLL Programming Requirements
          2. 5.4.5.7.2 HSDIV PLL Programming
          3. 5.4.5.7.3 PLL Controllers Programming - Dividers PLLDIVn and GO Operation
            1. 5.4.5.7.3.1 GO Operation
            2. 5.4.5.7.3.2 Software Steps to Modify PLLDIV Ratios
          4. 5.4.5.7.4 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
      6. 5.4.6 Registers
        1. 5.4.6.1 MCU_PLL0_CFG Registers
        2. 5.4.6.2 PLL0_CFG Registers
        3. 5.4.6.3 PLLCTRL0 Registers
  8. 6 Processors and Accelerators
    1. 6.1 Compute Cluster
      1. 6.1.1 Compute Cluster Overview
      2. 6.1.2 Compute Cluster Functional Description
        1. 6.1.2.1 Compute Cluster Memory Regions
        2. 6.1.2.2 Compute Cluster Firewalls
        3. 6.1.2.3 Compute Cluster ECC Aggregators
      3. 6.1.3 Compute Cluster Registers
    2. 6.2 Dual-A72 MPU Subsystem
      1. 6.2.1 A72SS Overview
        1. 6.2.1.1 A72SS Introduction
        2. 6.2.1.2 A72SS Features
      2. 6.2.2 A72SS Integration
      3. 6.2.3 A72SS Functional Description
        1. 6.2.3.1  A72SS Block Diagram
        2. 6.2.3.2  A72SS A72 Cluster
        3. 6.2.3.3  A72SS Interfaces and Async Bridges
        4. 6.2.3.4  A72SS Interrupts
          1. 6.2.3.4.1 A72SS Interrupt Inputs
          2. 6.2.3.4.2 A72SS Interrupt Outputs
        5. 6.2.3.5  A72SS Power Management, Clocking and Reset
          1. 6.2.3.5.1 A72SS Power Management
          2. 6.2.3.5.2 A72SS Clocking
        6. 6.2.3.6  A72SS Debug Support
        7. 6.2.3.7  A72SS Timestamps
        8. 6.2.3.8  A72SS Watchdog
        9. 6.2.3.9  A72SS Internal Diagnostics
          1. 6.2.3.9.1 A72SS ECC Aggregators During Low Power States
          2. 6.2.3.9.2 A72SS CBASS Diagnostics
          3. 6.2.3.9.3 A72SS SRAM Diagnostics
          4. 6.2.3.9.4 A72SS SRAM ECC Aggregator Configurations
        10. 6.2.3.10 A72SS Cache Pre-Warming
        11. 6.2.3.11 A72SS Boot
        12. 6.2.3.12 A72SS IPC with Other CPUs
      4. 6.2.4 A72SS Registers
        1. 6.2.4.1 Arm A72 Cluster Registers
        2. 6.2.4.2 A72SS ECC Aggregator Registers
          1. 6.2.4.2.1 A72SS CLUSTER ECC Registers
          2. 6.2.4.2.2 A72SS CORE0 ECC Registers
          3. 6.2.4.2.3 A72SS CORE1 ECC Registers
    3. 6.3 Dual-R5F MCU Subsystem
      1. 6.3.1 R5FSS Overview
        1. 6.3.1.1 R5FSS Features
        2. 6.3.1.2 R5FSS Not Supported Features
      2. 6.3.2 R5FSS Integration
        1. 6.3.2.1 R5FSS Integration in MCU Domain
        2. 6.3.2.2 R5FSS Integration in MAIN Domain
      3. 6.3.3 R5FSS Functional Description
        1. 6.3.3.1  R5FSS Block Diagram
        2. 6.3.3.2  R5FSS Cortex-R5F Core
          1. 6.3.3.2.1 L1 Caches
          2. 6.3.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.3.3.2.3 R5FSS Special Signals
        3. 6.3.3.3  R5FSS Interfaces
          1. 6.3.3.3.1 R5FSS Master Interfaces
          2. 6.3.3.3.2 R5FSS Slave Interfaces
        4. 6.3.3.4  R5FSS Power, Clocking and Reset
          1. 6.3.3.4.1 R5FSS Power
          2. 6.3.3.4.2 R5FSS Clocking
            1. 6.3.3.4.2.1 Changing MCU_R5FSS0 CPU Clock Frequency
          3. 6.3.3.4.3 R5FSS Reset
        5. 6.3.3.5  R5FSS Lockstep Error Detection Logic
          1. 6.3.3.5.1 CPU Output Compare Block
            1. 6.3.3.5.1.1 Operating Modes
            2. 6.3.3.5.1.2 Compare Block Active Mode
            3. 6.3.3.5.1.3 Self Test Mode
            4. 6.3.3.5.1.4 Compare Match Test
            5. 6.3.3.5.1.5 Compare Mismatch Test
            6. 6.3.3.5.1.6 Error Forcing Mode
            7. 6.3.3.5.1.7 Self Test Error Forcing Mode
          2. 6.3.3.5.2 Inactivity Monitor Block
            1. 6.3.3.5.2.1 Operating Modes
            2. 6.3.3.5.2.2 Compare Block Active Mode
            3. 6.3.3.5.2.3 Self Test Mode
            4. 6.3.3.5.2.4 Compare Match Test
            5. 6.3.3.5.2.5 Compare Mismatch Test
            6. 6.3.3.5.2.6 Error Forcing Mode
            7. 6.3.3.5.2.7 Self Test Error Forcing Mode
          3. 6.3.3.5.3 Polarity Inversion Logic
        6. 6.3.3.6  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.3.3.6.1 VIM Overview
          2. 6.3.3.6.2 VIM Interrupt Inputs
          3. 6.3.3.6.3 VIM Interrupt Outputs
          4. 6.3.3.6.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.3.3.6.5 VIM Interrupt Prioritization
          6. 6.3.3.6.6 VIM ECC Support
          7. 6.3.3.6.7 VIM Lockstep Mode
          8. 6.3.3.6.8 VIM IDLE State
          9. 6.3.3.6.9 VIM Interrupt Handling
            1. 6.3.3.6.9.1 Servicing IRQ Through Vector Interface
            2. 6.3.3.6.9.2 Servicing IRQ Through MMR Interface
            3. 6.3.3.6.9.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.3.3.6.9.4 Servicing FIQ
            5. 6.3.3.6.9.5 Servicing FIQ (Alternative)
        7. 6.3.3.7  R5FSS Region Address Translation (RAT)
          1. 6.3.3.7.1 RAT Overview
          2. 6.3.3.7.2 RAT Operation
          3. 6.3.3.7.3 RAT Error Logging
          4. 6.3.3.7.4 RAT Protection
        8. 6.3.3.8  R5FSS ECC Support
        9. 6.3.3.9  R5FSS Memory View
        10. 6.3.3.10 R5FSS Debug and Trace
        11. 6.3.3.11 R5FSS Boot Options
        12. 6.3.3.12 R5FSS Core Memory ECC Events
      4. 6.3.4 R5FSS Registers
        1. 6.3.4.1 R5FSS_CCMR5 Registers
        2. 6.3.4.2 R5FSS_CPU0_ECC_AGGR_CFG_REGS Registers
        3. 6.3.4.3 R5FSS_CPU1_ECC_AGGR_CFG_REGS Registers
        4. 6.3.4.4 R5FSS_VIM Registers
        5. 6.3.4.5 R5FSS_RAT Registers
        6. 6.3.4.6 R5FSS_EVNT_BUS_VBUSP_MMRS Registers
  9. 7 Interprocessor Communication
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
        3. 7.1.1.3 Mailbox Not Supported Features
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
        1. 7.2.1.1 Spinlock Not Supported Features
      2. 7.2.2 Spinlock Integration
      3. 7.2.3 Spinlock Functional Description
        1. 7.2.3.1 Spinlock Software Reset
        2. 7.2.3.2 Spinlock Power Management
        3. 7.2.3.3 About Spinlocks
        4. 7.2.3.4 Spinlock Functional Operation
      4. 7.2.4 Spinlock Programming Guide
        1. 7.2.4.1 Spinlock Low-level Programming Models
          1. 7.2.4.1.1 Surrounding Modules Global Initialization
          2. 7.2.4.1.2 Basic Spinlock Operations
            1. 7.2.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.4.1.2.2 Take and Release Spinlock
  10. 8 Memory Controllers
    1. 8.1 Multicore Shared Memory Controller (MSMC)
      1. 8.1.1 MSMC Overview
        1. 8.1.1.1 MSMC Not Supported Features
      2. 8.1.2 MSMC Integration
        1. 8.1.2.1 MSMC Integration in MAIN Domain
        2. 8.1.2.2 639
      3. 8.1.3 MSMC Functional Description
        1. 8.1.3.1  MSMC Block Diagram
        2. 8.1.3.2  MSMC On-Chip Memory Banking
        3. 8.1.3.3  MSMC Snoop Filter and Data Cache
          1. 8.1.3.3.1 Way Partitioning
          2. 8.1.3.3.2 Cache Size Configuration and Associativity
        4. 8.1.3.4  MSMC Access Protection Checks
        5. 8.1.3.5  MSMC Null Slave
        6. 8.1.3.6  MSMC Resource Arbitration
        7. 8.1.3.7  MSMC Error Detection and Correction
          1. 8.1.3.7.1 On-chip SRAM and Pipeline Data Protection
          2. 8.1.3.7.2 On-chip SRAM L3 Cache Tag and Snoop Filter Protection
          3. 8.1.3.7.3 On-chip SRAM Memory Mapped SRAM Snoop Filter Protection
          4. 8.1.3.7.4 Background Parity Refresh (Scrubbing)
        8. 8.1.3.8  MSMC Interrupts
          1. 8.1.3.8.1 Raw Interrupt Registers
          2. 8.1.3.8.2 Interrupt Enable Registers
          3. 8.1.3.8.3 Triggered and Enabled Interrupts
        9. 8.1.3.9  MSMC Memory Regions
        10. 8.1.3.10 MSMC Hardware Coherence
          1. 8.1.3.10.1 Snoop Filter Broadcast Mode
        11. 8.1.3.11 MSMC Quality-of-Service
        12. 8.1.3.12 MSMC Memory Regions Protection
        13. 8.1.3.13 MSMC Cache Tag View
      4. 8.1.4 MSMC Registers
    2. 8.2 DDR Subsystem (DDRSS)
      1. 8.2.1 DDRSS Overview
        1. 8.2.1.1 DDRSS Not Supported Features
      2. 8.2.2 DDRSS Environment
      3. 8.2.3 DDRSS Integration
        1. 8.2.3.1 DDRSS Integration in MAIN Domain
      4. 8.2.4 DDRSS Functional Description
        1. 8.2.4.1 DDRSS MSMC2DDR Bridge
          1. 8.2.4.1.1 VBUSM.C Threads
          2. 8.2.4.1.2 Class of Service (CoS)
          3. 8.2.4.1.3 AXI Write Data All-Strobes
          4. 8.2.4.1.4 Inline ECC for SDRAM Data
            1. 8.2.4.1.4.1 ECC Cache
            2. 8.2.4.1.4.2 ECC Statistics
          5. 8.2.4.1.5 Opcode Checking
          6. 8.2.4.1.6 Address Alias Prevention
          7. 8.2.4.1.7 Data Error Detection and Correction
          8. 8.2.4.1.8 AXI Bus Timeout
        2. 8.2.4.2 DDRSS Interrupts
        3. 8.2.4.3 DDRSS Memory Regions
        4. 8.2.4.4 DDRSS ECC Support
        5. 8.2.4.5 DDRSS Dynamic Frequency Change Interface
        6. 8.2.4.6 DDR Controller Functional Description
          1. 8.2.4.6.1  DDR PHY Interface (DFI)
          2. 8.2.4.6.2  Command Queue
            1. 8.2.4.6.2.1 Placement Logic
            2. 8.2.4.6.2.2 Command Selection Logic
          3. 8.2.4.6.3  Low Power Control
          4. 8.2.4.6.4  Transaction Processing
          5. 8.2.4.6.5  BIST Engine
          6. 8.2.4.6.6  ECC Engine
          7. 8.2.4.6.7  Address Mapping
          8. 8.2.4.6.8  Paging Policy
          9. 8.2.4.6.9  DDR Controller Initialization
          10. 8.2.4.6.10 Programming LPDDR4 Memories
            1. 8.2.4.6.10.1 Frequency Set Point (FSP)
              1. 8.2.4.6.10.1.1 FSP Mode Register Programming During Initialization
              2. 8.2.4.6.10.1.2 FSP Mode Register Programming During Normal Operation
              3. 8.2.4.6.10.1.3 FSP Mode Register Programming During Dynamic Frequency Scaling
            2. 8.2.4.6.10.2 Data Bus Inversion (DBI)
            3. 8.2.4.6.10.3 On-Die Termination
              1. 8.2.4.6.10.3.1 LPDDR4 DQ ODT
              2. 8.2.4.6.10.3.2 LPDDR4 CA ODT
            4. 8.2.4.6.10.4 Byte Lane Swapping
            5. 8.2.4.6.10.5 DQS Interval Oscillator
              1. 8.2.4.6.10.5.1 Oscillator State Machine
            6. 8.2.4.6.10.6 Per-Bank Refresh (PBR)
              1. 8.2.4.6.10.6.1 Normal Operation
              2. 8.2.4.6.10.6.2 Continuous Refresh Request Mode
        7. 8.2.4.7 DDR PHY Functional Description
          1. 8.2.4.7.1  Data Slice
          2. 8.2.4.7.2  Address Slice
            1. 8.2.4.7.2.1 Address Swapping
          3. 8.2.4.7.3  Address/Control Slice
          4. 8.2.4.7.4  Clock Slice
          5. 8.2.4.7.5  DDR PHY Initialization
          6. 8.2.4.7.6  DDR PHY Dynamic Frequency Scaling (DFS)
          7. 8.2.4.7.7  Chip Select and Frequency Based Register Settings
          8. 8.2.4.7.8  Low-Power Modes
          9. 8.2.4.7.9  Training Support
            1. 8.2.4.7.9.1 Write Leveling
            2. 8.2.4.7.9.2 Read Gate Training
            3. 8.2.4.7.9.3 Read Data Eye Training
            4. 8.2.4.7.9.4 Write DQ Training
            5. 8.2.4.7.9.5 CA Training
            6. 8.2.4.7.9.6 CS Training
          10. 8.2.4.7.10 Data Bus Inversion (DBI)
          11. 8.2.4.7.11 I/O Pad Calibration
          12. 8.2.4.7.12 DQS Error
        8. 8.2.4.8 PI Functional Description
          1. 8.2.4.8.1 PI Initialization
      5. 8.2.5 DDRSS Registers
        1. 8.2.5.1 DDR Subsystem Registers
        2. 8.2.5.2 DDR Controller Registers
        3. 8.2.5.3 PI Registers
        4. 8.2.5.4 DDR PHY Registers
        5. 8.2.5.5 DDRSS0_ECC_AGGR_CTL Registers
        6. 8.2.5.6 DDRSS0_ECC_AGGR_VBUS Registers
        7. 8.2.5.7 DDRSS0_ECC_AGGR_CFG Registers
    3. 8.3 Peripheral Virtualization Unit (PVU)
      1. 8.3.1 PVU Overview
        1. 8.3.1.1 PVU Features
        2. 8.3.1.2 PVU Parameters
        3. 8.3.1.3 PVU Not Supported Features
      2. 8.3.2 PVU Integration
      3. 8.3.3 PVU Functional Description
        1. 8.3.3.1  Functional Operation Overview
        2. 8.3.3.2  PVU Channels
        3. 8.3.3.3  TLB
        4. 8.3.3.4  TLB Entry
        5. 8.3.3.5  TLB Selection
        6. 8.3.3.6  DMA Classes
        7. 8.3.3.7  General virtIDs
        8. 8.3.3.8  TLB Lookup
        9. 8.3.3.9  TLB Miss
        10. 8.3.3.10 Multiple Matching Entries
        11. 8.3.3.11 TLB Disable
        12. 8.3.3.12 TLB Chaining
        13. 8.3.3.13 TLB Permissions
        14. 8.3.3.14 Translation
        15. 8.3.3.15 Memory Attributes
        16. 8.3.3.16 Faulted Transactions
        17. 8.3.3.17 Non-Virtual Transactions
        18. 8.3.3.18 Allowed virtIDs
        19. 8.3.3.19 Software Control
        20. 8.3.3.20 Fault Logging
        21. 8.3.3.21 Alignment Restrictions
      4. 8.3.4 PVU Registers
        1. 8.3.4.1 NAVSS_PVU_CFG Registers
        2. 8.3.4.2 NAVSS0_PVU_CFG_TLBIF Registers
    4. 8.4 Region-based Address Translation (RAT) Module
      1. 8.4.1 RAT Functional Description
        1. 8.4.1.1 RAT Availability
        2. 8.4.1.2 RAT Operation
        3. 8.4.1.3 RAT Error Logging
      2. 8.4.2 RAT Registers
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GIC)
        1. 9.2.1.1 GIC Overview
          1. 9.2.1.1.1 GIC Features
          2. 9.2.1.1.2 GIC Not Supported Features
        2. 9.2.1.2 GIC Integration
        3. 9.2.1.3 GIC Functional Description
          1. 9.2.1.3.1 GIC Block Diagram
          2. 9.2.1.3.2 Arm GIC-500
          3. 9.2.1.3.3 GIC Interrupt Types
          4. 9.2.1.3.4 GIC Interfaces
          5. 9.2.1.3.5 GIC Interrupt Outputs
          6. 9.2.1.3.6 GIC ECC Support
          7. 9.2.1.3.7 GIC AXI2VBUSM and VBUSM2AXI Bridges
        4. 9.2.1.4 GIC Registers
          1. 9.2.1.4.1 Arm GIC-500 Registers
          2. 9.2.1.4.2 GIC_ECC_AGGR Registers
      2. 9.2.2 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Integration
        1. 9.3.2.1 WKUP_GPIOMUX_INTRTR0 Integration
        2. 9.3.2.2 GPIOMUX_INTRTR0 Integration
        3. 9.3.2.3 MAIN2MCU_LVL_INTRTR0 Integration
        4. 9.3.2.4 MAIN2MCU_PLS_INTRTR0 Integration
      3. 9.3.3 INTRTR Registers
        1. 9.3.3.1 WKUP_GPIOMUX_INTRTR0 Registers
        2. 9.3.3.2 GPIOMUX_INTRTR0 Registers
        3. 9.3.3.3 MAIN2MCU_LVL_INTRTR0 Registers
        4. 9.3.3.4 MAIN2MCU_PLS_INTRTR0 Registers
    4. 9.4 Interrupt Sources
      1. 9.4.1 WKUP Domain Interrupt Maps
        1. 9.4.1.1 WKUP_DMSC0 Interrupt Map
        2. 9.4.1.2 WKUP_GPIOMUX_INTRTR0 Interrupt Map
        3. 9.4.1.3 WKUP_GPIO0_VIRT Interrupt Map
        4. 9.4.1.4 WKUP_ESM0 Interrupt Map
      2. 9.4.2 MCU Domain Interrupt Maps
        1. 9.4.2.1 MCU_R5FSS0_CORE0 Interrupt Map
        2. 9.4.2.2 MCU_R5FSS0_CORE1 Interrupt Map
        3. 9.4.2.3 MCU_ESM0 Interrupt Map
      3. 9.4.3 MAIN Domain Interrupt Maps
        1. 9.4.3.1 COMPUTE_CLUSTER0 Interrupt Map
          1. 9.4.3.1.1 GIC500 PPI Interrupt Map
          2. 9.4.3.1.2 GIC500 SPI Interrupt Map
          3. 9.4.3.1.3 SoC Event Output Interrupt Map
        2. 9.4.3.2 R5FSS0_CORE0 Interrupt Map
        3. 9.4.3.3 R5FSS0_CORE1 Interrupt Map
        4. 9.4.3.4 MAIN2MCU_LVL_INTRTR0 Interrupt Map
        5. 9.4.3.5 MAIN2MCU_PLS_INTRTR0 Interrupt Map
        6. 9.4.3.6 GPIOMUX_INTRTR0 Interrupt Map
        7. 9.4.3.7 GPIO0_VIRT Interrupt Map
        8. 9.4.3.8 ESM0 Interrupt Map
  12. 10Data Movement Architecture (DMA)
    1. 10.1 DMA Architecture
      1. 10.1.1 Overview
        1. 10.1.1.1  Navigator Subsystem
        2. 10.1.1.2  Ring Accelerator (RA)
        3. 10.1.1.3  Proxy
        4. 10.1.1.4  Secure Proxy
        5. 10.1.1.5  Interrupt Aggregator (INTA)
        6. 10.1.1.6  Interrupt Router (IR)
        7. 10.1.1.7  Unified DMA – Third Party Channel Controller (UDMA-C)
        8. 10.1.1.8  Unified Transfer Controller (UTC)
        9. 10.1.1.9  Data Routing Unit (DRU)
        10. 10.1.1.10 Unified DMA – Peripheral Root Complex (UDMA-P)
          1. 10.1.1.10.1 Channel Classes
        11. 10.1.1.11 Peripheral DMA (PDMA)
        12. 10.1.1.12 Embedded DMA
        13. 10.1.1.13 Definition of Terms
      2. 10.1.2 UDMA Hardware/Software Interface
        1. 10.1.2.1 Data Buffers
        2. 10.1.2.2 Descriptors
          1. 10.1.2.2.1 Host Packet Descriptor
          2. 10.1.2.2.2 Host Buffer Descriptor
          3. 10.1.2.2.3 Monolithic Packet Descriptor
          4. 10.1.2.2.4 Transfer Request Descriptor
        3. 10.1.2.3 Transfer Request Record
          1. 10.1.2.3.1 Overview
          2. 10.1.2.3.2 Addressing Algorithm
            1. 10.1.2.3.2.1 Linear Addressing (Forward)
          3. 10.1.2.3.3 Transfer Request Formats
          4. 10.1.2.3.4 Flags Field Definition
            1. 10.1.2.3.4.1 Type: TR Type Field
            2. 10.1.2.3.4.2 STATIC: Static Field Definition
            3. 10.1.2.3.4.3 EVENT_SIZE: Event Generation Definition
            4. 10.1.2.3.4.4 TRIGGER INFO: TR Triggers
            5. 10.1.2.3.4.5 TRIGGERX_TYPE: Trigger Type
            6. 10.1.2.3.4.6 TRIGGERX: Trigger Selection
            7. 10.1.2.3.4.7 CMD ID: Command ID Field Definition
            8. 10.1.2.3.4.8 Configuration Specific Flags Definition
          5. 10.1.2.3.5 TR Address and Size Attributes
            1. 10.1.2.3.5.1  ICNT0
            2. 10.1.2.3.5.2  ICNT1
            3. 10.1.2.3.5.3  ADDR
            4. 10.1.2.3.5.4  DIM1
            5. 10.1.2.3.5.5  ICNT2
            6. 10.1.2.3.5.6  ICNT3
            7. 10.1.2.3.5.7  DIM2
            8. 10.1.2.3.5.8  DIM3
            9. 10.1.2.3.5.9  DDIM1
            10. 10.1.2.3.5.10 DADDR
            11. 10.1.2.3.5.11 DDIM2
            12. 10.1.2.3.5.12 DDIM3
            13. 10.1.2.3.5.13 DICNT0
            14. 10.1.2.3.5.14 DICNT1
            15. 10.1.2.3.5.15 DICNT2
            16. 10.1.2.3.5.16 DICNT3
          6. 10.1.2.3.6 FMTFLAGS
            1. 10.1.2.3.6.1 AMODE: Addressing Mode Definition
              1. 10.1.2.3.6.1.1 Linear Addressing
              2. 10.1.2.3.6.1.2 Circular Addressing
            2. 10.1.2.3.6.2 DIR: Addressing Mode Direction Definition
            3. 10.1.2.3.6.3 ELTYPE: Element Type Definition
            4. 10.1.2.3.6.4 DFMT: Data Formatting Algorithm Definition
            5. 10.1.2.3.6.5 SECTR: Secondary Transfer Request Definition
              1. 10.1.2.3.6.5.1 Secondary TR Formats
              2. 10.1.2.3.6.5.2 Secondary TR FLAGS
                1. 10.1.2.3.6.5.2.1 SEC_TR_TYPE: Secondary TR Type Field
                2. 10.1.2.3.6.5.2.2 Multiple Buffer Interleave
            6. 10.1.2.3.6.6 AMODE SPECIFIC: Addressing Mode Field
              1. 10.1.2.3.6.6.1 Circular Address Mode Specific Flags
                1. 10.1.2.3.6.6.1.1 CBK0 and CBK1: Circular Block Size Selection
                2. 10.1.2.3.6.6.1.2 Amx: Addressing Mode Selection
            7. 10.1.2.3.6.7 Cache Flags
        4. 10.1.2.4 Transfer Response Record
          1. 10.1.2.4.1 STATUS Field Definition
            1. 10.1.2.4.1.1 STATUS_TYPE Definition
              1. 10.1.2.4.1.1.1 Transfer Error
              2. 10.1.2.4.1.1.2 Aborted Error
              3. 10.1.2.4.1.1.3 Submission Error
              4. 10.1.2.4.1.1.4 Unsupported Feature
              5. 10.1.2.4.1.1.5 Transfer Exception
              6. 10.1.2.4.1.1.6 Teardown Flush
        5. 10.1.2.5 Queues
          1. 10.1.2.5.1 Queue Types
            1. 10.1.2.5.1.1 Transmit Queues (Pass By Reference)
            2. 10.1.2.5.1.2 Transmit Queues (Pass By Value)
            3. 10.1.2.5.1.3 Transmit Completion Queues (Pass By Reference)
            4. 10.1.2.5.1.4 Transmit Completion Queues (Pass By Value)
            5. 10.1.2.5.1.5 Receive Queues
            6. 10.1.2.5.1.6 Free Descriptor Queues
            7. 10.1.2.5.1.7 Free Descriptor/Buffer Queues
          2. 10.1.2.5.2 Ring Accelerator Queues Implementation
      3. 10.1.3 Operational Description
        1. 10.1.3.1  Resource Allocation
        2. 10.1.3.2  Ring Accelerator Operation
          1. 10.1.3.2.1 Queue Initialization
          2. 10.1.3.2.2 Queuing packets (Exposed Ring Mode)
          3. 10.1.3.2.3 De-queuing packets (Exposed Ring Mode)
          4. 10.1.3.2.4 Queuing packets (Queue Mode)
          5. 10.1.3.2.5 De-queuing packets (Queue Mode)
        3. 10.1.3.3  UDMA Internal Transmit Channel Setup (All Packet Types)
        4. 10.1.3.4  UDMA Internal Transmit Channel Teardown (All Packet Types)
        5. 10.1.3.5  UDMA External Transmit Channel Setup
        6. 10.1.3.6  UDMA Transmit External Channel Teardown
        7. 10.1.3.7  UDMA-P Transmit Channel Pause
        8. 10.1.3.8  UDMA-P Transmit Operation (Host Packet Type)
        9. 10.1.3.9  UDMA-P Transmit Operation (Monolithic Packet)
        10. 10.1.3.10 UDMA Transmit Operation (TR Packet)
        11. 10.1.3.11 UDMA Transmit Operation (Direct TR)
        12. 10.1.3.12 UDMA Transmit Error/Exception Handling
          1. 10.1.3.12.1 Null Icnt0 Error
          2. 10.1.3.12.2 Unsupported TR Type
          3. 10.1.3.12.3 Bus Errors
        13. 10.1.3.13 UDMA Receive Channel Setup (All Packet Types)
        14. 10.1.3.14 UDMA Receive Channel Teardown
        15. 10.1.3.15 UDMA-P Receive Channel Pause
        16. 10.1.3.16 UDMA-P Receive Free Descriptor/Buffer Queue Setup (Host Packets)
        17. 10.1.3.17 UDMA-P Receive FlowID Firewall Operation
        18. 10.1.3.18 UDMA-P Receive Operation (Host Packet)
        19. 10.1.3.19 UDMA-P Receive Operation (Monolithic Packet)
        20. 10.1.3.20 UDMA Receive Operation (TR Packet)
        21. 10.1.3.21 UDMA Receive Operation (Direct TR)
        22. 10.1.3.22 UDMA Receive Error/Exception Handling
          1. 10.1.3.22.1 Error Conditions
            1. 10.1.3.22.1.1 Bus Errors
            2. 10.1.3.22.1.2 Null Icnt0 Error
            3. 10.1.3.22.1.3 Unsupported TR Type
          2. 10.1.3.22.2 Exception Conditions Exception Conditions
            1. 10.1.3.22.2.1 Descriptor Starvation
            2. 10.1.3.22.2.2 Protocol Errors
            3. 10.1.3.22.2.3 Dropped Packets
            4. 10.1.3.22.2.4 Reception of EOL Delimiter
            5. 10.1.3.22.2.5 EOP Asserted Prematurely (Short Packet)
            6. 10.1.3.22.2.6 EOP Asserted Late (Long Packets)
        23. 10.1.3.23 UTC Operation
        24. 10.1.3.24 UTC Receive Error/Exception Handling
          1. 10.1.3.24.1 Error Handling
            1. 10.1.3.24.1.1 Null Icnt0 Error
            2. 10.1.3.24.1.2 Unsupported TR Type
          2. 10.1.3.24.2 Exception Conditions
            1. 10.1.3.24.2.1 Reception of EOL Delimiter
            2. 10.1.3.24.2.2 EOP Asserted Prematurely (Short Packet)
            3. 10.1.3.24.2.3 EOP Asserted Late (Long Packets)
    2. 10.2 Navigator Subsystem (NAVSS)
      1. 10.2.1  Main Navigator Subsystem (NAVSS)
        1. 10.2.1.1 NAVSS Overview
        2. 10.2.1.2 NAVSS Integration
          1. 10.2.1.2.1 NAVSS Interrupt Router Configuration
          2. 10.2.1.2.2 Global Event Map
          3. 10.2.1.2.3 PSI-L System Thread Map (All NAVSS)
          4. 10.2.1.2.4 NAVSS VBUSM Route ID Table
        3. 10.2.1.3 NAVSS Functional Description
        4. 10.2.1.4 NAVSS Interrupt Configuration
          1. 10.2.1.4.1 NAVSS Event and Interrupt Flow
            1. 10.2.1.4.1.1 NAVSS Interrupts Description
            2. 10.2.1.4.1.2 Application Example
        5. 10.2.1.5 NAVSS Top-level Registers
          1. 10.2.1.5.1 NAVSS0_CFG Registers
          2. 10.2.1.5.2 INTR0_INTR_ROUTER_CFG Registers
          3. 10.2.1.5.3 VIRTID_CFG_MMRS Registers
      2. 10.2.2  MCU Navigator Subsystem (MCU NAVSS)
        1. 10.2.2.1 MCU NAVSS Overview
        2. 10.2.2.2 MCU NAVSS Integration
          1. 10.2.2.2.1  MCU NAVSS Interrupt Router Configuration
          2. 10.2.2.2.2  MCU NAVSS UDMASS Interrupt Aggregator Configuration
          3. 10.2.2.2.3  MCU NAVSS UDMA Configuration
          4. 10.2.2.2.4  MCU NAVSS Ring Accelerator Configuration
          5. 10.2.2.2.5  MCU NAVSS Proxy Configuration
          6. 10.2.2.2.6  MCU NAVSS Secure Proxy Configuration
          7. 10.2.2.2.7  Global Event Map
          8. 10.2.2.2.8  PSI-L System Thread Map (All NAVSS)
          9. 10.2.2.2.9  MCU NAVSS VBUSM Route ID Table
          10. 10.2.2.2.10 1006
        3. 10.2.2.3 MCU NAVSS Functional Description
        4. 10.2.2.4 MCU NAVSS Top-Level Registers
          1. 10.2.2.4.1 MCU_NAVSS0_CFG Registers
          2. 10.2.2.4.2 MCU_NAVSS0_UDMASS_ECCAGGR0 Registers
      3. 10.2.3  Unified DMA Controller (UDMA)
        1. 10.2.3.1 UDMA Overview
          1. 10.2.3.1.1 UDMA Features
          2. 10.2.3.1.2 UDMA Parameters
        2. 10.2.3.2 UDMA Integration
        3. 10.2.3.3 UDMA Functional Description
          1. 10.2.3.3.1 Block Diagram
          2. 10.2.3.3.2 General Functionality
            1. 10.2.3.3.2.1  Operational States
            2. 10.2.3.3.2.2  Tx Channel Allocation
            3. 10.2.3.3.2.3  Rx Channel Allocation
            4. 10.2.3.3.2.4  Tx Teardown
            5. 10.2.3.3.2.5  Rx Teardown
            6. 10.2.3.3.2.6  Tx Clock Stop
            7. 10.2.3.3.2.7  Rx Clock Stop
            8. 10.2.3.3.2.8  Rx Thread Enables
            9. 10.2.3.3.2.9  Events
              1. 10.2.3.3.2.9.1 Local Event Inputs
              2. 10.2.3.3.2.9.2 Inbound Tx PSI-L Events
              3. 10.2.3.3.2.9.3 Outbound Rx PSI-L Events
            10. 10.2.3.3.2.10 Emulation Control
          3. 10.2.3.3.3 Packet Oriented Transmit Operation
            1. 10.2.3.3.3.1 Packet Mode VBUSM Master Interface Command ID Selection
          4. 10.2.3.3.4 Packet Oriented Receive Operation
            1. 10.2.3.3.4.1 Rx Packet Drop
            2. 10.2.3.3.4.2 Rx Starvation and the Starvation Timer
          5. 10.2.3.3.5 Third Party Mode Operation
            1. 10.2.3.3.5.1 Events and Flow Control
              1. 10.2.3.3.5.1.1 Channel Triggering
              2. 10.2.3.3.5.1.2 Internal TR Completion Events
            2. 10.2.3.3.5.2 Transmit Operation
              1. 10.2.3.3.5.2.1 Transfer Request
              2. 10.2.3.3.5.2.2 Transfer Response
              3. 10.2.3.3.5.2.3 Data Transfer
              4. 10.2.3.3.5.2.4 Memory Interface Transactions
              5. 10.2.3.3.5.2.5 Error Handling
            3. 10.2.3.3.5.3 Receive Operation
              1. 10.2.3.3.5.3.1 Transfer Request
              2. 10.2.3.3.5.3.2 Transfer Response
              3. 10.2.3.3.5.3.3 Error Handling
            4. 10.2.3.3.5.4 Data Transfer
              1. 10.2.3.3.5.4.1 Memory Interface Transactions
              2. 10.2.3.3.5.4.2 Rx Packet Drop
        4. 10.2.3.4 UDMA Registers
          1. 10.2.3.4.1 UDMASS_UDMAP0_CFG Registers
          2. 10.2.3.4.2 UDMASS_UDMAP0_CFG_TCHAN Registers
          3. 10.2.3.4.3 UDMASS_UDMAP0_CFG_RCHAN Registers
          4. 10.2.3.4.4 UDMASS_UDMAP0_CFG_RFLOW Registers
          5. 10.2.3.4.5 UDMASS_UDMAP0_CFG_RCHANRT Registers
          6. 10.2.3.4.6 UDMASS_UDMAP0_CFG_TCHANRT Registers
      4. 10.2.4  Ring Accelerator (RINGACC)
        1. 10.2.4.1 RINGACC Overview
          1. 10.2.4.1.1 RINGACC Features
          2. 10.2.4.1.2 RINGACC Not Supported Features
          3. 10.2.4.1.3 RINGACC Parameters
        2. 10.2.4.2 RINGACC Integration
        3. 10.2.4.3 RINGACC Functional Description
          1. 10.2.4.3.1 Block Diagram
            1. 10.2.4.3.1.1  Configuration Registers
            2. 10.2.4.3.1.2  Source Command FIFO
            3. 10.2.4.3.1.3  Source Write Data FIFO
            4. 10.2.4.3.1.4  Source Read Data FIFO
            5. 10.2.4.3.1.5  Source Write Status FIFO
            6. 10.2.4.3.1.6  Main State Machine
            7. 10.2.4.3.1.7  Destination Command FIFO
            8. 10.2.4.3.1.8  Destination Write Data FIFO
            9. 10.2.4.3.1.9  Destination Read Data FIFO
            10. 10.2.4.3.1.10 Destination Write Status FIFO
          2. 10.2.4.3.2 RINGACC Functional Operation
            1. 10.2.4.3.2.1 Queue Modes
              1. 10.2.4.3.2.1.1 Ring Mode
              2. 10.2.4.3.2.1.2 Messaging Mode
              3. 10.2.4.3.2.1.3 Credentials Mode
              4. 10.2.4.3.2.1.4 Queue Manager Mode
              5. 10.2.4.3.2.1.5 Peek Support
              6. 10.2.4.3.2.1.6 Index Register Operation
            2. 10.2.4.3.2.2 VBUSM Slave Ring Operations
            3. 10.2.4.3.2.3 VBUSM Master Interface Command ID Selection
            4. 10.2.4.3.2.4 Ring Push Operation (VBUSM Write to Source Interface)
            5. 10.2.4.3.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
            6. 10.2.4.3.2.6 Host Doorbell Access
            7. 10.2.4.3.2.7 Queue Push Operation (VBUSM Write to Source Interface)
            8. 10.2.4.3.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
            9. 10.2.4.3.2.9 Mismatched Element Size Handling
          3. 10.2.4.3.3 Events
          4. 10.2.4.3.4 Bus Error Handling
          5. 10.2.4.3.5 Monitors
            1. 10.2.4.3.5.1 Threshold Monitor
            2. 10.2.4.3.5.2 Watermark Monitor
            3. 10.2.4.3.5.3 Starvation Monitor
            4. 10.2.4.3.5.4 Statistics Monitor
            5. 10.2.4.3.5.5 Overflow
            6. 10.2.4.3.5.6 Ring Update Port
            7. 10.2.4.3.5.7 Tracing
        4. 10.2.4.4 RINGACC Registers
          1. 10.2.4.4.1 NAVSS0_UDMASS_RINGACC0_CFG Registers
          2. 10.2.4.4.2 NAVSS0_UDMASS_RINGACC0_GCFG Registers
          3. 10.2.4.4.3 NAVSS0_UDMASS_RINGACC0_CFG_MON Registers
          4. 10.2.4.4.4 NAVSS0_UDMASS_RINGACC0_CFG_RT Registers
          5. 10.2.4.4.5 NAVSS0_UDMASS_RINGACC0_SRC_FIFOS Registers
      5. 10.2.5  Proxy
        1. 10.2.5.1 Proxy Overview
          1. 10.2.5.1.1 Proxy Features
          2. 10.2.5.1.2 Proxy Parameters
          3. 10.2.5.1.3 Proxy Not Supported Features
        2. 10.2.5.2 Proxy Integration
        3. 10.2.5.3 Proxy Functional Description
          1. 10.2.5.3.1  Targets
            1. 10.2.5.3.1.1 Ring Accelerator
          2. 10.2.5.3.2  Proxy Sizes
          3. 10.2.5.3.3  Proxy Interleaving
          4. 10.2.5.3.4  Proxy Host States
          5. 10.2.5.3.5  Proxy Host Channel Selection
          6. 10.2.5.3.6  Proxy Host Access
            1. 10.2.5.3.6.1 Proxy Host Writes
            2. 10.2.5.3.6.2 Proxy Host Reads
          7. 10.2.5.3.7  Permission Inheritance
          8. 10.2.5.3.8  Buffer Size
          9. 10.2.5.3.9  Error Events
          10. 10.2.5.3.10 Debug Reads
        4. 10.2.5.4 Proxy Registers
          1. 10.2.5.4.1 NAVSS0_PROXY0_CFG_BUF_CFG Registers
          2. 10.2.5.4.2 NAVSS0_PROXY0_BUF_CFG Registers
          3. 10.2.5.4.3 NAVSS0_PROXY_BUF Registers
          4. 10.2.5.4.4 NAVSS0_PROXY_TARGET0_DATA Registers
      6. 10.2.6  Secure Proxy
        1. 10.2.6.1 Secure Proxy Overview
          1. 10.2.6.1.1 Secure Proxy Features
          2. 10.2.6.1.2 Secure Proxy Parameters
          3. 10.2.6.1.3 Secure Proxy Not Supported Features
        2. 10.2.6.2 Secure Proxy Integration
        3. 10.2.6.3 Secure Proxy Functional Description
          1. 10.2.6.3.1  Targets
            1. 10.2.6.3.1.1 Ring Accelerator
          2. 10.2.6.3.2  Buffers
            1. 10.2.6.3.2.1 Proxy Credits
            2. 10.2.6.3.2.2 Proxy Private Word
            3. 10.2.6.3.2.3 Completion Byte
          3. 10.2.6.3.3  Proxy Thread Sizes
          4. 10.2.6.3.4  Proxy Thread Interleaving
          5. 10.2.6.3.5  Proxy States
          6. 10.2.6.3.6  Proxy Host Access
            1. 10.2.6.3.6.1 Proxy Host Writes
            2. 10.2.6.3.6.2 Proxy Host Reads
            3. 10.2.6.3.6.3 Buffer Accesses
            4. 10.2.6.3.6.4 Target Access
            5. 10.2.6.3.6.5 Error State
          7. 10.2.6.3.7  Permission Inheritance
          8. 10.2.6.3.8  Resource Association
          9. 10.2.6.3.9  Direction
          10. 10.2.6.3.10 Threshold Events
          11. 10.2.6.3.11 Error Events
          12. 10.2.6.3.12 Bus Errors and Credits
          13. 10.2.6.3.13 Debug
        4. 10.2.6.4 Secure Proxy Registers
          1. 10.2.6.4.1 NAVSS0_SEC_PROXY0_CFG_MMRS Registers
          2. 10.2.6.4.2 NAVSS0_SEC_PROXY0_CFG_RT Registers
          3. 10.2.6.4.3 NAVSS0_SEC_PROXY0_CFG_SCFG Registers
          4. 10.2.6.4.4 NAVSS0_SEC_PROXY0_SRC_TARGET_DATA Registers
      7. 10.2.7  Interrupt Aggregator (INTR_AGGR)
        1. 10.2.7.1 INTR_AGGR Overview
          1. 10.2.7.1.1 INTR_AGGR Features
          2. 10.2.7.1.2 INTR_AGGR Parameters
        2. 10.2.7.2 INTR_AGGR Integration
        3. 10.2.7.3 INTR_AGGR Functional Description
          1. 10.2.7.3.1 Submodule Descriptions
            1. 10.2.7.3.1.1 Status/Mask Registers
            2. 10.2.7.3.1.2 Interrupt Mapping Block
            3. 10.2.7.3.1.3 Global Event Input (GEVI) Counters
            4. 10.2.7.3.1.4 Local Event Input (LEVI) to Global Event Conversion
            5. 10.2.7.3.1.5 Global Event Multicast
          2. 10.2.7.3.2 General Functionality
            1. 10.2.7.3.2.1 Event to Interrupt Bit Steering
            2. 10.2.7.3.2.2 Interrupt Status
            3. 10.2.7.3.2.3 Interrupt Masked Status
            4. 10.2.7.3.2.4 Enabling/Disabling Individual Interrupt Source Bits
            5. 10.2.7.3.2.5 Interrupt Output Generation
            6. 10.2.7.3.2.6 Global Event Counting
            7. 10.2.7.3.2.7 Local Event to Global Event Conversion
            8. 10.2.7.3.2.8 Global Event Multicast
        4. 10.2.7.4 INTR_AGGR Registers
          1. 10.2.7.4.1  MODSS_INTA_CFG Registers
          2. 10.2.7.4.2  MODSS_INTA_CFG_IMAP Registers
          3. 10.2.7.4.3  MODSS_INTA_CFG_INTR Registers
          4. 10.2.7.4.4  UDMASS_INTA0_CFG Registers
          5. 10.2.7.4.5  UDMASS_INTA0_CFG_INTR Registers
          6. 10.2.7.4.6  UDMASS_INTA0_CFG_IMAP Registers
          7. 10.2.7.4.7  UDMASS_INTA0_CFG_L2G Registers
          8. 10.2.7.4.8  UDMASS_INTA0_CFG_MCAST Registers
          9. 10.2.7.4.9  UDMASS_INTA0_CFG_GCNTCFG Registers
          10. 10.2.7.4.10 UDMASS_INTA0_CFG_GCNTRTI Registers
      8. 10.2.8  Packet Streaming Interface Link (PSI-L)
        1. 10.2.8.1 PSI-L Overview
        2. 10.2.8.2 PSI-L Functional Description
          1. 10.2.8.2.1 PSI-L Introduction
          2. 10.2.8.2.2 PSI-L Operation
            1. 10.2.8.2.2.1 Event Transport
            2. 10.2.8.2.2.2 Threads
            3. 10.2.8.2.2.3 Arbitration Protocol
            4. 10.2.8.2.2.4 Thread Configuration
              1. 10.2.8.2.2.4.1 Thread Pairing
                1. 10.2.8.2.2.4.1.1 Configuration Transaction Pairing
              2. 10.2.8.2.2.4.2 Configuration Registers Region
        3. 10.2.8.3 PSI-L Configuration Registers
        4. 10.2.8.4 PSI-L CFG_PROXY Registers
      9. 10.2.9  PSIL Subsystem (PSILSS)
        1. 10.2.9.1 PSILSS Overview
          1. 10.2.9.1.1 PSILSS Features
        2. 10.2.9.2 PSILSS Functional Description
          1. 10.2.9.2.1 PSILSS Basic Operation
          2. 10.2.9.2.2 PSILSS Event Routing
          3. 10.2.9.2.3 PSILSS Link Down Detection
          4. 10.2.9.2.4 PSILSS Configuration
        3. 10.2.9.3 PSILSS Registers
          1. 10.2.9.3.1 PDMA_USART_PSILSS0 Registers
          2. 10.2.9.3.2 PDMA_SPI_PSILSS0 Registers
      10. 10.2.10 NAVSS North Bridge (NB)
        1. 10.2.10.1 NB Overview
          1. 10.2.10.1.1 Features Supported
          2. 10.2.10.1.2 NB Parameters
            1. 10.2.10.1.2.1 Compliance to Standards
            2. 10.2.10.1.2.2 Features Not Supported
        2. 10.2.10.2 NB Functional Description
          1. 10.2.10.2.1  VBUSM Slave Interfaces
          2. 10.2.10.2.2  VBUSM Master Interface
          3. 10.2.10.2.3  VBUSM.C Interfaces
            1. 10.2.10.2.3.1 Multi-Threading
            2. 10.2.10.2.3.2 Write Command Crediting
            3. 10.2.10.2.3.3 Early Credit Response
            4. 10.2.10.2.3.4 Priority Escalation
          4. 10.2.10.2.4  Source M2M Bridges
          5. 10.2.10.2.5  Destination M2M Bridge
          6. 10.2.10.2.6  M2C Bridge
          7. 10.2.10.2.7  Memory Attribute Tables
          8. 10.2.10.2.8  Outstanding Read Data Limiter
          9. 10.2.10.2.9  Ordering
          10. 10.2.10.2.10 Quality of Service
          11. 10.2.10.2.11 IDLE Behavior
          12. 10.2.10.2.12 Clock Power Management
        3. 10.2.10.3 NB Registers
          1. 10.2.10.3.1 NAVSS0_NBSS_CFG_REGS0_MMRS Registers
          2. 10.2.10.3.2 NAVSS0_NBSS_NB_CFG_MMRS Registers
    3. 10.3 Peripheral DMA (PDMA)
      1. 10.3.1 PDMA Controller
        1. 10.3.1.1 PDMA Overview
          1. 10.3.1.1.1 PDMA Features
            1. 10.3.1.1.1.1  MCU_PDMA0 (MCU_PDMA_MISC_G0) Features
            2. 10.3.1.1.1.2  MCU_PDMA1 (MCU_PDMA_MISC_G1) Features
            3. 10.3.1.1.1.3  MCU_PDMA2 (MCU_PDMA_MISC_G2) Features
            4. 10.3.1.1.1.4  MCU_PDMA3 (MCU_PDMA_ADC) Features
            5. 10.3.1.1.1.5  PDMA2 (PDMA_DEBUG_CCMCU) Features
            6. 10.3.1.1.1.6  PDMA5 (PDMA_MCAN) Features
            7. 10.3.1.1.1.7  PDMA6 (PDMA_MCASP_G0) Features
            8. 10.3.1.1.1.8  PDMA9 (PDMA_SPI_G0) Features
            9. 10.3.1.1.1.9  PDMA10 (PDMA_SPI_G1) Features
            10. 10.3.1.1.1.10 PDMA13 (PDMA_USART_G0) Features
            11. 10.3.1.1.1.11 PDMA14 (PDMA_USART_G1) Features
            12. 10.3.1.1.1.12 PDMA15 (PDMA_USART_G2) Features
        2. 10.3.1.2 PDMA Integration
          1. 10.3.1.2.1 PDMA Integration in MCU Domain
          2. 10.3.1.2.2 PDMA Integration in MAIN Domain
        3. 10.3.1.3 PDMA Functional Description
          1. 10.3.1.3.1 PDMA Functional Blocks
            1. 10.3.1.3.1.1 Scheduler
            2. 10.3.1.3.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 10.3.1.3.1.3 Tx DMA Unit (Tx Engine)
            4. 10.3.1.3.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 10.3.1.3.1.5 Rx DMA Unit (Rx Engine)
          2. 10.3.1.3.2 PDMA General Functionality
            1. 10.3.1.3.2.1 Operational States
            2. 10.3.1.3.2.2 Clock Stop
            3. 10.3.1.3.2.3 Emulation Control
          3. 10.3.1.3.3 PDMA Events and Flow Control
            1. 10.3.1.3.3.1 Channel Types
              1. 10.3.1.3.3.1.1 X-Y FIFO Mode
              2. 10.3.1.3.3.1.2 MCAN Mode
              3. 10.3.1.3.3.1.3 AASRC Mode
              4. 10.3.1.3.3.1.4 1288
            2. 10.3.1.3.3.2 Channel Triggering
            3. 10.3.1.3.3.3 Completion Events
          4. 10.3.1.3.4 PDMA Transmit Operation
            1. 10.3.1.3.4.1 Destination (Tx) Channel Allocation
            2. 10.3.1.3.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 10.3.1.3.4.3 Destination Channel Initialization
              1. 10.3.1.3.4.3.1 PSI-L Destination Thread Pairing
              2. 10.3.1.3.4.3.2 Static Transfer Request Setup
              3. 10.3.1.3.4.3.3 1297
              4. 10.3.1.3.4.3.4 PSI-L Destination Thread Enables
            4. 10.3.1.3.4.4 Data Transfer
              1. 10.3.1.3.4.4.1 X-Y FIFO Mode Channel
                1. 10.3.1.3.4.4.1.1 X-Y FIFO Burst Mode
              2. 10.3.1.3.4.4.2 MCAN Mode Channel
                1. 10.3.1.3.4.4.2.1 MCAN Burst Mode
              3. 10.3.1.3.4.4.3 AASRC Mode Channel
            5. 10.3.1.3.4.5 Tx Pause
            6. 10.3.1.3.4.6 Tx Teardown
            7. 10.3.1.3.4.7 Tx Channel Reset
            8. 10.3.1.3.4.8 Tx Debug/State Registers
          5. 10.3.1.3.5 PDMA Receive Operation
            1. 10.3.1.3.5.1 Source (Rx) Channel Allocation
            2. 10.3.1.3.5.2 Source Channel Initialization
              1. 10.3.1.3.5.2.1 PSI-L Source Thread Pairing
              2. 10.3.1.3.5.2.2 Static Transfer Request Setup
              3. 10.3.1.3.5.2.3 PSI-L Source Thread Enables
            3. 10.3.1.3.5.3 Data Transfer
              1. 10.3.1.3.5.3.1 X-Y FIFO Mode Channel
              2. 10.3.1.3.5.3.2 MCAN Mode Channel
                1. 10.3.1.3.5.3.2.1 MCAN Burst Mode
              3. 10.3.1.3.5.3.3 AASRC Mode Channel
            4. 10.3.1.3.5.4 Rx Pause
            5. 10.3.1.3.5.5 Rx Teardown
            6. 10.3.1.3.5.6 Rx Channel Reset
            7. 10.3.1.3.5.7 Rx Debug/State Register
          6. 10.3.1.3.6 PDMA ECC Support
        4. 10.3.1.4 PDMA Registers
          1. 10.3.1.4.1 PDMA5 ECC Registers
          2. 10.3.1.4.2 PDMA9 ECC Registers
          3. 10.3.1.4.3 PDMA10 ECC Registers
          4. 10.3.1.4.4 PDMA PSI-L TX Configuration Registers
          5. 10.3.1.4.5 PDMA PSI-L RX Configuration Registers
      2. 10.3.2 PDMA Sources
        1. 10.3.2.1 MCU Domain PDMA Event Maps
          1. 10.3.2.1.1 MCU_PDMA_MISC_G0 Event Map
          2. 10.3.2.1.2 MCU_PDMA_MISC_G1 Event Map
          3. 10.3.2.1.3 MCU_PDMA_MISC_G2 Event Map
          4. 10.3.2.1.4 MCU_PDMA_ADC Event Map
        2. 10.3.2.2 MAIN Domain PDMA Event Maps
          1. 10.3.2.2.1 PDMA_DEBUG_CCMCU Event Map
          2. 10.3.2.2.2 PDMA_MCAN Event Map
          3. 10.3.2.2.3 PDMA_MCASP_G0 Event Map
          4. 10.3.2.2.4 PDMA_SPI_G0 Event Map
          5. 10.3.2.2.5 PDMA_SPI_G1 Event Map
          6. 10.3.2.2.6 PDMA_USART_G0 Event Map
          7. 10.3.2.2.7 PDMA_USART_G1 Event Map
          8. 10.3.2.2.8 PDMA_USART_G2 Event Map
  13. 11Time Sync
    1. 11.1 Time Sync Module (CPTS)
      1. 11.1.1 CPTS Overview
        1. 11.1.1.1 CPTS Features
        2. 11.1.1.2 CPTS Not Supported Features
      2. 11.1.2 CPTS Integration
      3. 11.1.3 CPTS Functional Description
        1. 11.1.3.1  CPTS Architecture
        2. 11.1.3.2  CPTS Initialization
        3. 11.1.3.3  32-bit Time Stamp Value
        4. 11.1.3.4  64-bit Time Stamp Value
          1. 11.1.3.4.1 64-Bit Timestamp Nudge
          2. 11.1.3.4.2 64-bit Timestamp PPM
        5. 11.1.3.5  Event FIFO
        6. 11.1.3.6  Timestamp Compare Output
          1. 11.1.3.6.1 Non-Toggle Mode
          2. 11.1.3.6.2 Toggle Mode
        7. 11.1.3.7  Timestamp Sync Output
        8. 11.1.3.8  Timestamp GENF Output
          1. 11.1.3.8.1 GENFn Nudge
          2. 11.1.3.8.2 GENFn PPM
        9. 11.1.3.9  Time Sync Events
          1. 11.1.3.9.1 Time Stamp Push Event
          2. 11.1.3.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 11.1.3.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 11.1.3.9.4 Hardware Time Stamp Push Event
        10. 11.1.3.10 Timestamp Compare Event
        11. 11.1.3.11 CPTS Interrupt Handling
      4. 11.1.4 CPTS Registers
    2. 11.2 Timer Manager
      1. 11.2.1 Timer Manager Overview
        1. 11.2.1.1 Timer Manager Features
        2. 11.2.1.2 Timer Manager Not Supported Features
      2. 11.2.2 Timer Manager Integration
      3. 11.2.3 Timer Manager Functional Description
        1. 11.2.3.1 Timer Manager Function Overview
        2. 11.2.3.2 Timer Counter
          1. 11.2.3.2.1 Timer Counter Rollover
        3. 11.2.3.3 Timer Control Module (FSM)
        4. 11.2.3.4 Timer Reprogramming
          1. 11.2.3.4.1 Periodic Hardware Timers
        5. 11.2.3.5 Event FIFO
        6. 11.2.3.6 Output Event Lookup (OES RAM)
      4. 11.2.4 Timer Manager Programming Guide
        1. 11.2.4.1 Timer Manager Low-level Programming Models
          1. 11.2.4.1.1 Surrounding Modules Global Initialization
          2. 11.2.4.1.2 Initialization Sequence
          3. 11.2.4.1.3 Real-time Operating Requirements
            1. 11.2.4.1.3.1 Timer Touch
            2. 11.2.4.1.3.2 Timer Disable
            3. 11.2.4.1.3.3 Timer Enable
          4. 11.2.4.1.4 Power Up/Power Down Sequence
      5. 11.2.5 Timer Manager Registers
        1. 11.2.5.1 TIMERMGR_CFG_CFG Registers
        2. 11.2.5.2 TIMERMGR_CFG_OES Registers
        3. 11.2.5.3 TIMERMGR_CFG_TIMERS Registers
    3. 11.3 Time Sync and Compare Events
      1. 11.3.1 Time Sync Architecture
        1. 11.3.1.1 Time Sync Architecture Overview
      2. 11.3.2 Time Sync Routers
        1. 11.3.2.1 Time Sync Routers Overview
        2. 11.3.2.2 Time Sync Routers Integration
          1. 11.3.2.2.1 TIMESYNC_INTRTR0 Integration
          2. 11.3.2.2.2 CMPEVT_INTRTR0 Integration
        3. 11.3.2.3 Time Sync Routers Registers
          1. 11.3.2.3.1 TIMESYNC_INTRTR0 Registers
          2. 11.3.2.3.2 CMPEVT_INTRTR0 Registers
      3. 11.3.3 Time Sync Event Sources
        1. 11.3.3.1 CMPEVT_INTRTR0 Event Map
        2. 11.3.3.2 TIMESYNC_INTRTR0 Event Map
        3. 11.3.3.3 DMSS0 Sync Event Map
        4. 11.3.3.4 PCIE1 Sync Event Map
        5. 11.3.3.5 MCU_CPSW0 Sync Event Map
        6. 11.3.3.6 CPSW0 Sync Event Map
        7. 11.3.3.7 I/O Sync Event Map
  14. 12Peripherals
    1. 12.1 General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Not Supported Features
        2. 12.1.1.2 ADC Environment
          1. 12.1.1.2.1 ADC Interface Signals
        3. 12.1.1.3 ADC Integration
          1. 12.1.1.3.1 ADC Integration in MCU Domain
        4. 12.1.1.4 ADC Functional Description
          1. 12.1.1.4.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.4.1.1 Step Enable
            2. 12.1.1.4.1.2 Step Configuration
              1. 12.1.1.4.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.4.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.4.1.2.3 Averaging of Samples
              4. 12.1.1.4.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.4.1.2.5 Differential Control
              6. 12.1.1.4.1.2.6 FIFO Select
              7. 12.1.1.4.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.4.1.3 Open Delay and Sample Delay
              1. 12.1.1.4.1.3.1 Open Delay
              2. 12.1.1.4.1.3.2 Sample Delay
            4. 12.1.1.4.1.4 Interrupts
            5. 12.1.1.4.1.5 Power Management
            6. 12.1.1.4.1.6 DMA Requests
          2. 12.1.1.4.2 ADC AFE Functional Description
            1. 12.1.1.4.2.1 AFE Functional Block Diagram
            2. 12.1.1.4.2.2 ADC GPI Integration
          3. 12.1.1.4.3 ADC FIFOs and DMA
            1. 12.1.1.4.3.1 FIFOs
            2. 12.1.1.4.3.2 DMA
          4. 12.1.1.4.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.4.4.1 Testing ECC Error Injection
          5. 12.1.1.4.5 ADC Functional Internal Diagnostic Debug Mode
        5. 12.1.1.5 ADC Programming Guide
          1. 12.1.1.5.1 ADC Low-Level Programming Models
            1. 12.1.1.5.1.1 Global Initialization
              1. 12.1.1.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.1.5.1.1.2 General Programming Model
            2. 12.1.1.5.1.2 During Operation
        6. 12.1.1.6 ADC Registers
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Not Supported Features
        2. 12.1.2.2 GPIO Environment
          1. 12.1.2.2.1 GPIO Interface Signals
        3. 12.1.2.3 GPIO Integration
          1. 12.1.2.3.1 GPIO Integration in WKUP Domain
          2. 12.1.2.3.2 GPIO Integration in MAIN Domain
        4. 12.1.2.4 GPIO Functional Description
          1. 12.1.2.4.1 GPIO Block Diagram
          2. 12.1.2.4.2 GPIO Function
          3. 12.1.2.4.3 GPIO Interrupt and Event Generation
            1. 12.1.2.4.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.4.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.4.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.4.4 GPIO Interrupt Connectivity
          5. 12.1.2.4.5 GPIO DeepSleep Mode
          6. 12.1.2.4.6 GPIO Emulation Halt Operation
        5. 12.1.2.5 GPIO Programming Guide
          1. 12.1.2.5.1 GPIO Low-Level Programming Models
            1. 12.1.2.5.1.1 Global Initialization
              1. 12.1.2.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.2.5.1.1.2 GPIO Module Global Initialization
            2. 12.1.2.5.1.2 GPIO Operational Modes Configuration
              1. 12.1.2.5.1.2.1 GPIO Read Input Register
              2. 12.1.2.5.1.2.2 GPIO Set Bit Function
              3. 12.1.2.5.1.2.3 GPIO Clear Bit Function
        6. 12.1.2.6 GPIO Registers
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Not Supported Features
        2. 12.1.3.2 I2C Environment
          1. 12.1.3.2.1 I2C Typical Application
            1. 12.1.3.2.1.1 I2C Pins for Typical Connections in I2C Mode
            2. 12.1.3.2.1.2 I2C Interface Typical Connections
            3. 12.1.3.2.1.3 1501
          2. 12.1.3.2.2 I2C Typical Connection Protocol and Data Format
            1. 12.1.3.2.2.1  I2C Serial Data Format
            2. 12.1.3.2.2.2  I2C Data Validity
            3. 12.1.3.2.2.3  I2C Start and Stop Conditions
            4. 12.1.3.2.2.4  I2C Addressing
              1. 12.1.3.2.2.4.1 Data Transfer Formats in F/S Mode
              2. 12.1.3.2.2.4.2 Data Transfer Format in HS Mode
            5. 12.1.3.2.2.5  I2C Controller Transmitter
            6. 12.1.3.2.2.6  I2C Controller Receiver
            7. 12.1.3.2.2.7  I2C Target Transmitter
            8. 12.1.3.2.2.8  I2C Target Receiver
            9. 12.1.3.2.2.9  I2C Bus Arbitration
            10. 12.1.3.2.2.10 I2C Clock Generation and Synchronization
        3. 12.1.3.3 I2C Integration
          1. 12.1.3.3.1 I2C Integration in WKUP Domain
          2. 12.1.3.3.2 I2C Integration in MCU Domain
          3. 12.1.3.3.3 I2C Integration in MAIN Domain
        4. 12.1.3.4 I2C Functional Description
          1. 12.1.3.4.1 I2C Block Diagram
          2. 12.1.3.4.2 I2C Clocks
            1. 12.1.3.4.2.1 I2C Clocking
            2. 12.1.3.4.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.4.3 I2C Software Reset
          4. 12.1.3.4.4 I2C Power Management
          5. 12.1.3.4.5 I2C Interrupt Requests
          6. 12.1.3.4.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.4.7 I2C FIFO Management
            1. 12.1.3.4.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.4.7.2 I2C FIFO Polling Mode
            3. 12.1.3.4.7.3 I2C Draining Feature
          8. 12.1.3.4.8 I2C Noise Filter
          9. 12.1.3.4.9 I2C System Test Mode
        5. 12.1.3.5 I2C Programming Guide
          1. 12.1.3.5.1 I2C Low-Level Programming Models
            1. 12.1.3.5.1.1 I2C Programming Model
              1. 12.1.3.5.1.1.1 Main Program
                1. 12.1.3.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.5.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.5.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.5.1.1.1.4 Initiate a Transfer
                5. 12.1.3.5.1.1.1.5 Receive Data
                6. 12.1.3.5.1.1.1.6 Transmit Data
              2. 12.1.3.5.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.5.1.1.3 Programming Flow-Diagrams
        6. 12.1.3.6 I2C Registers
      4. 12.1.4 Improved Inter-Integrated Circuit (I3C) Interface
        1. 12.1.4.1 I3C Overview
          1. 12.1.4.1.1 I3C Features
          2. 12.1.4.1.2 I3C Not Supported Features
        2. 12.1.4.2 I3C Environment
          1. 12.1.4.2.1 I3C Typical Application
            1. 12.1.4.2.1.1 I3C Pins for Typical Connections
            2. 12.1.4.2.1.2 I3C Interface Typical Connections
            3. 12.1.4.2.1.3 1555
        3. 12.1.4.3 I3C Integration
          1. 12.1.4.3.1 I3C Integration in MCU Domain
          2. 12.1.4.3.2 I3C Integration in MAIN Domain
        4. 12.1.4.4 I3C Functional Description
          1. 12.1.4.4.1  I3C Block Diagram
          2. 12.1.4.4.2  I3C Clock Configuration
            1. 12.1.4.4.2.1 Setting Base Frequencies
            2. 12.1.4.4.2.2 Asymmetric Push-Pull SCL Timing
            3. 12.1.4.4.2.3 Open-Drain SCL Timing
            4. 12.1.4.4.2.4 Changing Programmed Frequencies
          3. 12.1.4.4.3  I3C Interrupt Requests
          4. 12.1.4.4.4  I3C Power Configuration
          5. 12.1.4.4.5  I3C Dynamic Address Management
          6. 12.1.4.4.6  I3C Retaining Registers Space
          7. 12.1.4.4.7  I3C Dynamic Address Assignment Procedure
          8. 12.1.4.4.8  I3C Sending CCC Messages
          9. 12.1.4.4.9  I3C In-Band Interrupt
            1. 12.1.4.4.9.1 Regular I3C Slave In-Band Interrupt
            2. 12.1.4.4.9.2 Current Master Takeover In-Band Interrupt
          10. 12.1.4.4.10 I3C Hot-Join Request
          11. 12.1.4.4.11 I3C Immediate Commands
          12. 12.1.4.4.12 I3C Host Commands
          13. 12.1.4.4.13 I3C Sending Private Data in SDR Messages
            1. 12.1.4.4.13.1 SDR Private Write Message
            2. 12.1.4.4.13.2 SDR Private Read Message
            3. 12.1.4.4.13.3 SDR Payload Length Adjustment
        5. 12.1.4.5 I3C Programming Guide
          1. 12.1.4.5.1 I3C Power-On Programming Model
          2. 12.1.4.5.2 I3C Static Devices Programming
          3. 12.1.4.5.3 I3C DAA Procedure Initiation
          4. 12.1.4.5.4 I3C SDR Write Message Programming Model
          5. 12.1.4.5.5 I3C SDR Read Message Programming Model
          6. 12.1.4.5.6 I3C DDR Write Message Programming Model
          7. 12.1.4.5.7 I3C DDR Read Message Programming Model
        6. 12.1.4.6 I3C Registers
      5. 12.1.5 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.5.1 MCSPI Overview
          1. 12.1.5.1.1 SPI Features
          2. 12.1.5.1.2 MCSPI Not Supported Features
        2. 12.1.5.2 MCSPI Environment
          1. 12.1.5.2.1 Basic MCSPI Pins for Master Mode
          2. 12.1.5.2.2 Basic MCSPI Pins for Slave Mode
          3. 12.1.5.2.3 MCSPI Internal Connectivity
          4. 12.1.5.2.4 MCSPI Protocol and Data Format
            1. 12.1.5.2.4.1 Transfer Format
          5. 12.1.5.2.5 MCSPI in Controller Mode
          6. 12.1.5.2.6 MCSPI in Peripheral Mode
        3. 12.1.5.3 MCSPI Integration
          1. 12.1.5.3.1 MCSPI Integration in MCU Domain
          2. 12.1.5.3.2 MCSPI Integration in MAIN Domain
        4. 12.1.5.4 MCSPI Functional Description
          1. 12.1.5.4.1 SPI Block Diagram
          2. 12.1.5.4.2 MCSPI Reset
          3. 12.1.5.4.3 MCSPI Controller Mode
            1. 12.1.5.4.3.1 Controller Mode Features
            2. 12.1.5.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.5.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.5.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.5.4.3.5 Single-Channel Controller Mode
              1. 12.1.5.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.5.4.3.5.2 Force SPIEN[i] Mode
              3. 12.1.5.4.3.5.3 Turbo Mode
            6. 12.1.5.4.3.6 Start-Bit Mode
            7. 12.1.5.4.3.7 Chip-Select Timing Control
            8. 12.1.5.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.5.4.3.8.1 Clock Ratio Granularity
          4. 12.1.5.4.4 MCSPI Peripheral Mode
            1. 12.1.5.4.4.1 Dedicated Resources
            2. 12.1.5.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.5.4.4.3 Peripheral Transmit-Only Mode
            4. 12.1.5.4.4.4 Peripheral Receive-Only Mode
          5. 12.1.5.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.5.4.6 MCSPI FIFO Buffer Management
            1. 12.1.5.4.6.1 Buffer Almost Full
            2. 12.1.5.4.6.2 Buffer Almost Empty
            3. 12.1.5.4.6.3 End of Transfer Management
            4. 12.1.5.4.6.4 Multiple MCSPI Word Access
            5. 12.1.5.4.6.5 First MCSPI Word Delay
          7. 12.1.5.4.7 MCSPI Interrupts
            1. 12.1.5.4.7.1 Interrupt Events in Controller Mode
              1. 12.1.5.4.7.1.1 TXx_EMPTY
              2. 12.1.5.4.7.1.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.1.3 RXx_ FULL
              4. 12.1.5.4.7.1.4 End Of Word Count
            2. 12.1.5.4.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.5.4.7.2.1 TXx_EMPTY
              2. 12.1.5.4.7.2.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.2.3 RXx_FULL
              4. 12.1.5.4.7.2.4 RX0_OVERFLOW
              5. 12.1.5.4.7.2.5 End Of Word Count
            3. 12.1.5.4.7.3 Interrupt-Driven Operation
            4. 12.1.5.4.7.4 Polling
          8. 12.1.5.4.8 MCSPI DMA Requests
          9. 12.1.5.4.9 MCSPI Power Saving Management
            1. 12.1.5.4.9.1 Normal Mode
            2. 12.1.5.4.9.2 Idle Mode
              1. 12.1.5.4.9.2.1 Force-Idle Mode
        5. 12.1.5.5 MCSPI Programming Guide
          1. 12.1.5.5.1 MCSPI Global Initialization
            1. 12.1.5.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.5.5.1.2 MCSPI Global Initialization
              1. 12.1.5.5.1.2.1 Main Sequence – MCSPI Global Initialization
          2. 12.1.5.5.2 MCSPI Operational Mode Configuration
            1. 12.1.5.5.2.1 MCSPI Operational Modes
              1. 12.1.5.5.2.1.1 Common Transfer Sequence
              2. 12.1.5.5.2.1.2 End of Transfer Sequences
              3. 12.1.5.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.5.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.5.5.2.1.4.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.4.2 Based on DMA Write Requests
              5. 12.1.5.5.2.1.5 Controller Normal Receive-Only
                1. 12.1.5.5.2.1.5.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.5.2 Based on DMA Read Requests
              6. 12.1.5.5.2.1.6 Controller Turbo Receive-Only
                1. 12.1.5.5.2.1.6.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.6.2 Based on DMA Read Requests
              7. 12.1.5.5.2.1.7 Peripheral Receive-Only
              8. 12.1.5.5.2.1.8 Transfer Procedures With FIFO
                1. 12.1.5.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.5.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.5.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.5.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.5.5.2.1.8.5 Transmit-Only
                6. 12.1.5.5.2.1.8.6 Receive-Only With Word Count
                7. 12.1.5.5.2.1.8.7 Receive-Only Without Word Count
              9. 12.1.5.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.5.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.5.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.5.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.5.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
        6. 12.1.5.6 MCSPI Registers
      6. 12.1.6 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.6.1 UART Overview
          1. 12.1.6.1.1 UART Features
          2. 12.1.6.1.2 IrDA Features
          3. 12.1.6.1.3 CIR Features
          4. 12.1.6.1.4 UART Not Supported Features
        2. 12.1.6.2 UART Environment
          1. 12.1.6.2.1 UART Functional Interfaces
            1. 12.1.6.2.1.1 System Using UART Communication With Hardware Handshake
            2. 12.1.6.2.1.2 UART Interface Description
            3. 12.1.6.2.1.3 UART Protocol and Data Format
            4. 12.1.6.2.1.4 UART 9-bit Mode Data Format
          2. 12.1.6.2.2 RS-485 Functional Interfaces
            1. 12.1.6.2.2.1 System Using RS-485 Communication
            2. 12.1.6.2.2.2 RS-485 Interface Description
          3. 12.1.6.2.3 IrDA Functional Interfaces
            1. 12.1.6.2.3.1 System Using IrDA Communication Protocol
            2. 12.1.6.2.3.2 IrDA Interface Description
            3. 12.1.6.2.3.3 IrDA Protocol and Data Format
              1. 12.1.6.2.3.3.1 SIR Mode
                1. 12.1.6.2.3.3.1.1 Frame Format
                2. 12.1.6.2.3.3.1.2 Asynchronous Transparency
                3. 12.1.6.2.3.3.1.3 Abort Sequence
                4. 12.1.6.2.3.3.1.4 Pulse Shaping
                5. 12.1.6.2.3.3.1.5 Encoder
                6. 12.1.6.2.3.3.1.6 Decoder
                7. 12.1.6.2.3.3.1.7 IR Address Checking
              2. 12.1.6.2.3.3.2 SIR Free-Format Mode
              3. 12.1.6.2.3.3.3 MIR Mode
                1. 12.1.6.2.3.3.3.1 MIR Encoder/Decoder
                2. 12.1.6.2.3.3.3.2 SIP Generation
              4. 12.1.6.2.3.3.4 FIR Mode
          4. 12.1.6.2.4 CIR Functional Interfaces
            1. 12.1.6.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 12.1.6.2.4.2 CIR Interface Description
            3. 12.1.6.2.4.3 CIR Protocol and Data Format
              1. 12.1.6.2.4.3.1 Carrier Modulation
              2. 12.1.6.2.4.3.2 Pulse Duty Cycle
              3. 12.1.6.2.4.3.3 Consumer IR Encoding/Decoding
        3. 12.1.6.3 UART Integration
          1. 12.1.6.3.1 UART Integration in WKUP Domain
          2. 12.1.6.3.2 UART Integration in MCU Domain
          3. 12.1.6.3.3 UART Integration in MAIN Domain
        4. 12.1.6.4 UART Functional Description
          1. 12.1.6.4.1 UART Block Diagram
          2. 12.1.6.4.2 UART Clock Configuration
          3. 12.1.6.4.3 UART Software Reset
            1. 12.1.6.4.3.1 Independent TX/RX
          4. 12.1.6.4.4 UART Power Management
            1. 12.1.6.4.4.1 UART Mode Power Management
              1. 12.1.6.4.4.1.1 Module Power Saving
              2. 12.1.6.4.4.1.2 System Power Saving
            2. 12.1.6.4.4.2 IrDA Mode Power Management
              1. 12.1.6.4.4.2.1 Module Power Saving
              2. 12.1.6.4.4.2.2 System Power Saving
            3. 12.1.6.4.4.3 CIR Mode Power Management
              1. 12.1.6.4.4.3.1 Module Power Saving
              2. 12.1.6.4.4.3.2 System Power Saving
            4. 12.1.6.4.4.4 Local Power Management
          5. 12.1.6.4.5 UART Interrupt Requests
            1. 12.1.6.4.5.1 UART Mode Interrupt Management
              1. 12.1.6.4.5.1.1 UART Interrupts
              2. 12.1.6.4.5.1.2 Wake-Up Interrupt
            2. 12.1.6.4.5.2 IrDA Mode Interrupt Management
              1. 12.1.6.4.5.2.1 IrDA Interrupts
              2. 12.1.6.4.5.2.2 Wake-Up Interrupts
            3. 12.1.6.4.5.3 CIR Mode Interrupt Management
              1. 12.1.6.4.5.3.1 CIR Interrupts
              2. 12.1.6.4.5.3.2 Wake-Up Interrupts
          6. 12.1.6.4.6 UART FIFO Management
            1. 12.1.6.4.6.1 FIFO Trigger
              1. 12.1.6.4.6.1.1 Transmit FIFO Trigger
              2. 12.1.6.4.6.1.2 Receive FIFO Trigger
            2. 12.1.6.4.6.2 FIFO Interrupt Mode
            3. 12.1.6.4.6.3 FIFO Polled Mode Operation
            4. 12.1.6.4.6.4 FIFO DMA Mode Operation
              1. 12.1.6.4.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.6.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.6.4.6.4.3 DMA Transmission
              4. 12.1.6.4.6.4.4 DMA Reception
          7. 12.1.6.4.7 UART Mode Selection
            1. 12.1.6.4.7.1 Register Access Modes
              1. 12.1.6.4.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.6.4.7.1.2 Register Access Submode
              3. 12.1.6.4.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.6.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.6.4.7.2.1 Registers Available for the UART Function
              2. 12.1.6.4.7.2.2 Registers Available for the IrDA Function
              3. 12.1.6.4.7.2.3 Registers Available for the CIR Function
          8. 12.1.6.4.8 UART Protocol Formatting
            1. 12.1.6.4.8.1 UART Mode
              1. 12.1.6.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.6.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.1.3 UART Data Formatting
                1. 12.1.6.4.8.1.3.1 Frame Formatting
                2. 12.1.6.4.8.1.3.2 Hardware Flow Control
                3. 12.1.6.4.8.1.3.3 Software Flow Control
                  1. 1.6.4.8.1.3.3.1 Receive (RX)
                  2. 1.6.4.8.1.3.3.2 Transmit (TX)
                4. 12.1.6.4.8.1.3.4 Autobauding Modes
                5. 12.1.6.4.8.1.3.5 Error Detection
                6. 12.1.6.4.8.1.3.6 Overrun During Receive
                7. 12.1.6.4.8.1.3.7 Time-Out and Break Conditions
                  1. 1.6.4.8.1.3.7.1 Time-Out Counter
                  2. 1.6.4.8.1.3.7.2 Break Condition
            2. 12.1.6.4.8.2 RS-485 Mode
              1. 12.1.6.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.6.4.8.3 IrDA Mode
              1. 12.1.6.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.6.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.3.3 IrDA Data Formatting
                1. 12.1.6.4.8.3.3.1  IR RX Polarity Control
                2. 12.1.6.4.8.3.3.2  IrDA Reception Control
                3. 12.1.6.4.8.3.3.3  IR Address Checking
                4. 12.1.6.4.8.3.3.4  Frame Closing
                5. 12.1.6.4.8.3.3.5  Store and Controlled Transmission
                6. 12.1.6.4.8.3.3.6  Error Detection
                7. 12.1.6.4.8.3.3.7  Underrun During Transmission
                8. 12.1.6.4.8.3.3.8  Overrun During Receive
                9. 12.1.6.4.8.3.3.9  Status FIFO
                10. 12.1.6.4.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.6.4.8.3.3.11 Time-guard
              4. 12.1.6.4.8.3.4 SIR Mode Data Formatting
                1. 12.1.6.4.8.3.4.1 Abort Sequence
                2. 12.1.6.4.8.3.4.2 Pulse Shaping
                3. 12.1.6.4.8.3.4.3 SIR Free Format Programming
              5. 12.1.6.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.6.4.8.4 CIR Mode
              1. 12.1.6.4.8.4.1 CIR Mode Clock Generation
              2. 12.1.6.4.8.4.2 CIR Data Formatting
                1. 12.1.6.4.8.4.2.1 IR RX Polarity Control
                2. 12.1.6.4.8.4.2.2 CIR Transmission
                3. 12.1.6.4.8.4.2.3 CIR Reception
        5. 12.1.6.5 UART Programming Guide
          1. 12.1.6.5.1 UART Global Initialization
            1. 12.1.6.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.6.5.1.2 UART Module Global Initialization
          2. 12.1.6.5.2 UART Mode selection
          3. 12.1.6.5.3 UART Submode selection
          4. 12.1.6.5.4 UART Load FIFO trigger and DMA mode settings
            1. 12.1.6.5.4.1 DMA mode Settings
            2. 12.1.6.5.4.2 FIFO Trigger Settings
          5. 12.1.6.5.5 UART Protocol, Baud rate and interrupt settings
            1. 12.1.6.5.5.1 Baud rate settings
            2. 12.1.6.5.5.2 Interrupt settings
            3. 12.1.6.5.5.3 Protocol settings
            4. 12.1.6.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.6.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 12.1.6.5.6 UART Hardware and Software Flow Control Configuration
            1. 12.1.6.5.6.1 Hardware Flow Control Configuration
            2. 12.1.6.5.6.2 Software Flow Control Configuration
          7. 12.1.6.5.7 IrDA Programming Model
            1. 12.1.6.5.7.1 SIR mode
              1. 12.1.6.5.7.1.1 Receive
              2. 12.1.6.5.7.1.2 Transmit
            2. 12.1.6.5.7.2 MIR mode
              1. 12.1.6.5.7.2.1 Receive
              2. 12.1.6.5.7.2.2 Transmit
            3. 12.1.6.5.7.3 FIR mode
              1. 12.1.6.5.7.3.1 Receive
              2. 12.1.6.5.7.3.2 Transmit
        6. 12.1.6.6 UART Registers
    2. 12.2 High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet MAC (MCU_CPSW0)
        1. 12.2.1.1 MCU_CPSW0 Overview
          1. 12.2.1.1.1 MCU_CPSW0 Features
          2. 12.2.1.1.2 MCU_CPSW0 Not Supported Features
          3. 12.2.1.1.3 Terminology
        2. 12.2.1.2 MCU_CPSW0 Environment
          1. 12.2.1.2.1 MCU_CPSW0 RMII Interface
          2. 12.2.1.2.2 MCU_CPSW0 RGMII Interface
        3. 12.2.1.3 MCU_CPSW0 Integration
        4. 12.2.1.4 MCU_CPSW0 Functional Description
          1. 12.2.1.4.1 Functional Block Diagram
          2. 12.2.1.4.2 CPSW Ports
            1. 12.2.1.4.2.1 Interface Mode Selection
          3. 12.2.1.4.3 Clocking
            1. 12.2.1.4.3.1 Subsystem Clocking
            2. 12.2.1.4.3.2 Interface Clocking
              1. 12.2.1.4.3.2.1 RGMII Interface Clocking
              2. 12.2.1.4.3.2.2 RMII Interface Clocking
              3. 12.2.1.4.3.2.3 MDIO Clocking
          4. 12.2.1.4.4 Software IDLE
          5. 12.2.1.4.5 Interrupt Functionality
            1. 12.2.1.4.5.1 EVNT_PEND Interrupt
            2. 12.2.1.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.1.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.1.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.1.4.5.5 MDIO Interrupts
          6. 12.2.1.4.6 CPSW_2G
            1. 12.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.1.4.6.1.1  Error Handling
              2. 12.2.1.4.6.1.2  Bypass Operations
              3. 12.2.1.4.6.1.3  OUI Deny or Accept
              4. 12.2.1.4.6.1.4  Statistics Counting
              5. 12.2.1.4.6.1.5  Automotive Security Features
              6. 12.2.1.4.6.1.6  CPSW Switching Solutions
                1. 12.2.1.4.6.1.6.1 Basics of 2-port Switch Type
              7. 12.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.1.4.6.1.7.1 InterVLAN Routing
                2. 12.2.1.4.6.1.7.2 OAM Operations
              8. 12.2.1.4.6.1.8  Supervisory packets
              9. 12.2.1.4.6.1.9  Address Table Entry
                1. 12.2.1.4.6.1.9.1 Free Table Entry
                2. 12.2.1.4.6.1.9.2 Multicast Address Table Entry
                3. 12.2.1.4.6.1.9.3 VLAN/Multicast Address Table Entry
                4. 12.2.1.4.6.1.9.4 Unicast Address Table Entry
                5. 12.2.1.4.6.1.9.5 OUI Unicast Address Table Entry
                6. 12.2.1.4.6.1.9.6 VLAN/Unicast Address Table Entry
                7. 12.2.1.4.6.1.9.7 VLAN Table Entry
              10. 12.2.1.4.6.1.10 ALE Policing and Classification
                1. 12.2.1.4.6.1.10.1 ALE Classification
                  1. 2.1.4.6.1.10.1.1 Classifier to CPPI Transmit Flow ID Mapping
              11. 12.2.1.4.6.1.11 DSCP
              12. 12.2.1.4.6.1.12 Packet Forwarding Processes
                1. 12.2.1.4.6.1.12.1 Ingress Filtering Process
                2. 12.2.1.4.6.1.12.2 VLAN_Aware Lookup Process
                3. 12.2.1.4.6.1.12.3 Egress Process
                4. 12.2.1.4.6.1.12.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.12.4.1 Learning Process
                  2. 2.1.4.6.1.12.4.2 Updating Process
                  3. 2.1.4.6.1.12.4.3 Touching Process
              13. 12.2.1.4.6.1.13 VLAN Aware Mode
              14. 12.2.1.4.6.1.14 VLAN Unaware Mode
            2. 12.2.1.4.6.2  Packet Priority Handling
              1. 12.2.1.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.1.4.6.3  CPPI Port Ingress
            4. 12.2.1.4.6.4  Packet CRC Handling
              1. 12.2.1.4.6.4.1 Transmit VLAN Processing
                1. 12.2.1.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.1.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.1.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.1.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.1.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.1.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.1.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.1.4.6.5  FIFO Memory Control
            6. 12.2.1.4.6.6  FIFO Transmit Queue Control
              1. 12.2.1.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.1.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.1.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.1.4.6.7.1 IET Configuration
            8. 12.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
              7. 12.2.1.4.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
            9. 12.2.1.4.6.9  Audio Video Bridging
              1. 12.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.1.4.6.10 Ethernet MAC Sliver
              1. 12.2.1.4.6.10.1 1945
                1. 12.2.1.4.6.10.1.1 1946
                  1. 2.1.4.6.10.1.1.1 CRC Insertion
                  2. 2.1.4.6.10.1.1.2 MTXER
                  3. 2.1.4.6.10.1.1.3 Adaptive Performance Optimization (APO)
                  4. 2.1.4.6.10.1.1.4 Inter-Packet-Gap Enforcement
                  5. 2.1.4.6.10.1.1.5 Back Off
                  6. 2.1.4.6.10.1.1.6 Programmable Transmit Inter-Packet Gap
                  7. 2.1.4.6.10.1.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 12.2.1.4.6.10.2 RMII Interface
                1. 12.2.1.4.6.10.2.1 Features
                2. 12.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 12.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 12.2.1.4.6.10.3 RGMII Interface
                1. 12.2.1.4.6.10.3.1 Features
                2. 12.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 12.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 12.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 12.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 12.2.1.4.6.10.4 Frame Classification
              5. 12.2.1.4.6.10.5 Receive FIFO Architecture
            11. 12.2.1.4.6.11 Embedded Memories
            12. 12.2.1.4.6.12 Memory Error Detection and Correction
              1. 12.2.1.4.6.12.1 Packet Header ECC
              2. 12.2.1.4.6.12.2 Packet Protect CRC
              3. 12.2.1.4.6.12.3 Aggregator RAM Control
            13. 12.2.1.4.6.13 Ethernet Port Flow Control
              1. 12.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.1.4.6.13.2 Flow Control Trigger
              3. 12.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 12.2.1.4.6.15 Ethernet Switch Latency
            16. 12.2.1.4.6.16 MAC Emulation Control
            17. 12.2.1.4.6.17 MAC Command IDLE
            18. 12.2.1.4.6.18 CPSW Network Statistics
              1. 12.2.1.4.6.18.1  Rx-only Statistics Descriptions
                1. 12.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h - Port 0 or Offset = 3A200h - Port 1)
                2. 12.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h - Port 0 or Offset = 3A204h - Port 1)
                3. 12.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h - Port 0 or Offset = 3A208h - Port 1)
                4. 12.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A20Ch - Port 1)
                5. 12.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h - Port 0 or Offset = 3A210h - Port 1)
                6. 12.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A214h - Port 1)
                7. 12.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h - Port 0 or Offset = 3A218h - Port 1)
                8. 12.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A21Ch - Port 1)
                9. 12.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h- Port 0 or Offset = 3A220h - Port 1)
                10. 12.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h - Port 0 or Offset = 3A224h - Port 1)
                11. 12.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A25Ch - Port 1)
                12. 12.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h - Port 0 or Offset = 3A228h - Port 1)
                13. 12.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch - Port 0 or Offset = 3A22Ch - Port 1)
                14. 12.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h - Port 0 or Offset = 3A230h - Port 1)
                15. 12.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h - Port 0 or Offset = 3A284h - Port 1)
                16. 12.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h - Port 0 or Offset = 3A288h - Port 1)
                17. 12.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch - Port 0 or Offset = 3A28Ch - Port 1)
                18. 12.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h - Port 0 or Offset = 3A290h - Port 1)
                19. 12.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h - Port 0 or Offset = 3A294h - Port 1)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h - Port 0 or Offset = 3A298h - Port 1)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch - Port 0 or Offset = 3A29Ch - Port 1)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h - Port 0 or Offset = 3A2A0h - Port 1)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h - Port 0 or Offset = 3A2A4h - Port 1)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h - Port 0 or Offset = 3A2A8h - Port 1)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh - Port 0 or Offset = 3A2ACh - Port 1)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h - Port 0 or Offset = 3A2B0h - Port 1)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h - Port 0 or Offset = 3A2B4h - Port 1)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h - Port 0 or Offset = 3A2B8h - Port 1)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh - Port 0 or Offset = 3A2BCh - Port 1)
                  11. 2.1.4.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h - Port 0 or Offset = 3A2C0h - Port 1)
              2. 12.2.1.4.6.18.2  ALE Policer Match Red (Offset = 3A0C4h - Port 0 or Offset = 3A2C4h - Port 1)
              3. 12.2.1.4.6.18.3  ALE Policer Match Yellow (Offset = 3A0C8h - Port 0 or Offset = 3A2C8h - Port 1)
              4. 12.2.1.4.6.18.4  IET Receive Assembly Error (Offset = 3A140h - Port 0 or Offset = 3A340h - Port 1)
              5. 12.2.1.4.6.18.5  IET Receive Assembly OK (Offset = 3A144h - Port 0 or Offset = 3A344h - Port 1)
              6. 12.2.1.4.6.18.6  IET Receive SMD Error (Offset = 3A148h - Port 0 or Offset = 3A348h - Port 1)
              7. 12.2.1.4.6.18.7  IET Receive Merge Fragment Count (Offset = 3A14Ch - Port 0 or Offset = 3A34Ch - Port 1)
              8. 12.2.1.4.6.18.8  Tx-only Statistics Descriptions
                1. 12.2.1.4.6.18.8.1  Good Tx Frames (Offset = 3A034h - Port 0 or Offset = 3A234h - Port 1)
                2. 12.2.1.4.6.18.8.2  Broadcast Tx Frames (Offset = 3A038h - Port 0 or Offset = 3A238h - Port 1)
                3. 12.2.1.4.6.18.8.3  Multicast Tx Frames (Offset = 3A03Ch - Port 0 or Offset = 3A23Ch - Port 1)
                4. 12.2.1.4.6.18.8.4  Pause Tx Frames (Offset = 3A240h - Port 1)
                5. 12.2.1.4.6.18.8.5  Deferred Tx Frames (Offset = 3A244h - Port 1)
                6. 12.2.1.4.6.18.8.6  Collisions (Offset = 3A248h - Port 1)
                7. 12.2.1.4.6.18.8.7  Single Collision Tx Frames (Offset = 3A24Ch - Port 1)
                8. 12.2.1.4.6.18.8.8  Multiple Collision Tx Frames (Offset = 3A250h - Port 1)
                9. 12.2.1.4.6.18.8.9  Excessive Collisions (Offset = 3A254h - Port 1)
                10. 12.2.1.4.6.18.8.10 Late Collisions (Offset = 3A258h - Port 1)
                11. 12.2.1.4.6.18.8.11 Carrier Sense Errors (Offset = 3A260h - Port 1)
                12. 12.2.1.4.6.18.8.12 Tx Octets (Offset = 3A064h - Port 0 or Offset = 3A264h - Port 1 )
                13. 12.2.1.4.6.18.8.13 Transmit Priority 0-7 (Offset = 3A380h to 3A3A8h - Port 1)
                14. 12.2.1.4.6.18.8.14 Transmit Priority 0-7 Drop (Offset = 3A3C0h to 3A3E8 - Port 1)
                15. 12.2.1.4.6.18.8.15 Tx Memory Protect Errors (Offset = 3A17Ch - Port 0 or Offset = 3A37Ch - Port 1)
                16. 12.2.1.4.6.18.8.16 IET Transmit Merge Hold Count (Offset = 3A350h - Port 1)
                17. 12.2.1.4.6.18.8.17 IET Transmit Merge Fragment Count (Offset = 3A154h - Port 0 or Offset = 3A354h - Port 1)
              9. 12.2.1.4.6.18.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.1.4.6.18.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h - Port 0 or Offset = 3A268h - Port 1)
                2. 12.2.1.4.6.18.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch - Port 0 or Offset = 3A26Ch - Port 1)
                3. 12.2.1.4.6.18.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h - Port 0 or Offset = 3A270h - Port 1)
                4. 12.2.1.4.6.18.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h - Port 0 or Offset = 3A274h - Port 1)
                5. 12.2.1.4.6.18.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h - Port 0 or Offset = 3A278h - Port 1)
                6. 12.2.1.4.6.18.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch - Port 0 or Offset = 3A27Ch - Port 1)
                7. 12.2.1.4.6.18.9.7 Net Octets (Offset = 3A080h - Port 0 or Offset = 3A280h - Port 1)
              10. 12.2.1.4.6.18.10 2045
          7. 12.2.1.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.1.4.7.1  MCU_CPSW0 CPTS Integration
            2. 12.2.1.4.7.2  CPTS Architecture
            3. 12.2.1.4.7.3  CPTS Initialization
            4. 12.2.1.4.7.4  32-bit Time Stamp Value
            5. 12.2.1.4.7.5  64-bit Time Stamp Value
            6. 12.2.1.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.1.4.7.7  64-bit Timestamp PPM
            8. 12.2.1.4.7.8  Event FIFO
            9. 12.2.1.4.7.9  Timestamp Compare Output
              1. 12.2.1.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.1.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.1.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.1.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.1.4.7.10 Timestamp Sync Output
            11. 12.2.1.4.7.11 Timestamp GENFn Output
              1. 12.2.1.4.7.11.1 GENFn Nudge
              2. 12.2.1.4.7.11.2 GENFn PPM
            12. 12.2.1.4.7.12 Timestamp ESTFn
            13. 12.2.1.4.7.13 Time Sync Events
              1. 12.2.1.4.7.13.1 Time Stamp Push Event
              2. 12.2.1.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.1.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.1.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.1.4.7.13.5 Ethernet Port Events
                1. 12.2.1.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.1.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.1.4.7.13.5.3 2073
            14. 12.2.1.4.7.14 Timestamp Compare Event
              1. 12.2.1.4.7.14.1 32-Bit Mode
              2. 12.2.1.4.7.14.2 64-Bit Mode
            15. 12.2.1.4.7.15 Host Transmit Event
            16. 12.2.1.4.7.16 CPTS Interrupt Handling
          8. 12.2.1.4.8 CPPI Streaming Packet Interface
            1. 12.2.1.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_2G Egress)
            2. 12.2.1.4.8.2 Port 0 CPPI Receive Packet Streaming Interface (CPSW_2G Ingress)
            3. 12.2.1.4.8.3 CPPI Checksum Offload
              1. 12.2.1.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.1.4.8.3.1.1 IPV4 UDP
                2. 12.2.1.4.8.3.1.2 IPV4 TCP
                3. 12.2.1.4.8.3.1.3 IPV6 UDP
                4. 12.2.1.4.8.3.1.4 IPV6 TCP
            4. 12.2.1.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.1.4.8.5 Egress Packet Operations
          9. 12.2.1.4.9 MII Management Interface (MDIO)
            1. 12.2.1.4.9.1 MDIO Frame Formats
            2. 12.2.1.4.9.2 MDIO Functional Description
        5. 12.2.1.5 MCU_CPSW0 Programming Guide
          1. 12.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.5.2 CPSW Reset
          3. 12.2.1.5.3 MDIO Software Interface
            1. 12.2.1.5.3.1 Initializing the MDIO Module
            2. 12.2.1.5.3.2 Writing Data To a PHY Register
            3. 12.2.1.5.3.3 Reading Data From a PHY Register
        6. 12.2.1.6 MCU_CPSW0 Registers
          1. 12.2.1.6.1  MCU_CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.1.6.2  MCU_CPSW0_SGMII Registers
          3. 12.2.1.6.3  MCU_CPSW0_MDIO Registers
          4. 12.2.1.6.4  MCU_CPSW0_CPTS Registers
          5. 12.2.1.6.5  MCU_CPSW0_CONTROL Registers
          6. 12.2.1.6.6  MCU_CPSW0_CPINT Registers
          7. 12.2.1.6.7  MCU_CPSW0_RAM Registers
          8. 12.2.1.6.8  MCU_CPSW0_STAT0 Registers
          9. 12.2.1.6.9  MCU_CPSW0_STAT1 Registers
          10. 12.2.1.6.10 MCU_CPSW0_ALE Registers
          11. 12.2.1.6.11 MCU_CPSW0_ECC Registers
      2. 12.2.2 Gigabit Ethernet Switch (CPSW0)
        1. 12.2.2.1 CPSW0 Overview
          1. 12.2.2.1.1 CPSW0 Features
          2. 12.2.2.1.2 CPSW0 Not Supported Features
          3. 12.2.2.1.3 Terminology
        2. 12.2.2.2 CPSW0 Environment
          1. 12.2.2.2.1 CPSW0 RMII Interface
          2. 12.2.2.2.2 CPSW0 RGMII Interface
        3. 12.2.2.3 CPSW0 Integration
        4. 12.2.2.4 CPSW0 Functional Description
          1. 12.2.2.4.1 Functional Block Diagram
          2. 12.2.2.4.2 CPSW Ports
            1. 12.2.2.4.2.1 Interface Mode Selection
          3. 12.2.2.4.3 Clocking
            1. 12.2.2.4.3.1 Subsystem Clocking
            2. 12.2.2.4.3.2 Interface Clocking
              1. 12.2.2.4.3.2.1 RGMII Interface Clocking
              2. 12.2.2.4.3.2.2 RMII Interface Clocking
              3. 12.2.2.4.3.2.3 MDIO Clocking
          4. 12.2.2.4.4 Software IDLE
          5. 12.2.2.4.5 Interrupt Functionality
            1. 12.2.2.4.5.1 EVNT_PEND Interrupt
            2. 12.2.2.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.2.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.2.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.2.4.5.5 MDIO Interrupts
          6. 12.2.2.4.6 CPSW_5X
            1. 12.2.2.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.2.4.6.1.1  Error Handling
              2. 12.2.2.4.6.1.2  Bypass Operations
              3. 12.2.2.4.6.1.3  OUI Deny or Accept
              4. 12.2.2.4.6.1.4  Statistics Counting
              5. 12.2.2.4.6.1.5  Automotive Security Features
              6. 12.2.2.4.6.1.6  CPSW Switching Solutions
                1. 12.2.2.4.6.1.6.1 Basics of 5-port Switch Type
              7. 12.2.2.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.2.4.6.1.7.1 InterVLAN Routing
                2. 12.2.2.4.6.1.7.2 OAM Operations
              8. 12.2.2.4.6.1.8  Supervisory packets
              9. 12.2.2.4.6.1.9  Address Table Entry
                1. 12.2.2.4.6.1.9.1  Free Table Entry
                2. 12.2.2.4.6.1.9.2  Multicast Address Table Entry (Bit 40 == 0)
                3. 12.2.2.4.6.1.9.3  Multicast Address Table Entry (Bit 40 == 1)
                4. 12.2.2.4.6.1.9.4  VLAN Unicast Address Table Entry (Bit 40 == 0)
                5. 12.2.2.4.6.1.9.5  OUI Unicast Address Table Entry
                6. 12.2.2.4.6.1.9.6  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                7. 12.2.2.4.6.1.9.7  VLAN/ Multicast Address Table Entry (Bit 40 == 1)
                8. 12.2.2.4.6.1.9.8  Inner VLAN Table Entry
                9. 12.2.2.4.6.1.9.9  Outer VLAN Table Entry
                10. 12.2.2.4.6.1.9.10 EtherType Table Entry
                11. 12.2.2.4.6.1.9.11 IPv4 Table Entry
                12. 12.2.2.4.6.1.9.12 IPv6 Table Entry High
                13. 12.2.2.4.6.1.9.13 IPv6 Table Entry Low
              10. 12.2.2.4.6.1.10 Multicast Address
                1. 12.2.2.4.6.1.10.1 Multicast Ranges
              11. 12.2.2.4.6.1.11 Supervisory Packets
              12. 12.2.2.4.6.1.12 Aging and Auto Aging
              13. 12.2.2.4.6.1.13 ALE Policing and Classification
                1. 12.2.2.4.6.1.13.1 ALE Policing
                2. 12.2.2.4.6.1.13.2 Classifier to Host Thread Mapping
                3. 12.2.2.4.6.1.13.3 ALE Classification
                  1. 2.2.4.6.1.13.3.1 Classifier to CPPI Transmit Flow ID Mapping
              14. 12.2.2.4.6.1.14 Mirroring
              15. 12.2.2.4.6.1.15 Trunking
              16. 12.2.2.4.6.1.16 DSCP
              17. 12.2.2.4.6.1.17 Packet Forwarding Processes
                1. 12.2.2.4.6.1.17.1 Ingress Filtering Process
                2. 12.2.2.4.6.1.17.2 VLAN_Aware Lookup Process
                3. 12.2.2.4.6.1.17.3 Egress Process
                4. 12.2.2.4.6.1.17.4 Learning/Updating/Touching Processes
                  1. 2.2.4.6.1.17.4.1 Learning Process
                  2. 2.2.4.6.1.17.4.2 Updating Process
                  3. 2.2.4.6.1.17.4.3 Touching Process
              18. 12.2.2.4.6.1.18 VLAN Aware Mode
              19. 12.2.2.4.6.1.19 VLAN Unaware Mode
            2. 12.2.2.4.6.2  Packet Priority Handling
              1. 12.2.2.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.2.4.6.3  CPPI Port Ingress
            4. 12.2.2.4.6.4  Packet CRC Handling
              1. 12.2.2.4.6.4.1 Transmit VLAN Processing
                1. 12.2.2.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.2.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.2.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.2.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.2.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.2.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.2.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.2.4.6.5  FIFO Memory Control
            6. 12.2.2.4.6.6  FIFO Transmit Queue Control
              1. 12.2.2.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.2.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.2.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.2.4.6.7.1 IET Configuration
            8. 12.2.2.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.2.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.2.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.2.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.2.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.2.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.2.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
            9. 12.2.2.4.6.9  Audio Video Bridging
              1. 12.2.2.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.2.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.2.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.2.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.2.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.2.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.2.4.6.10 Ethernet MAC Sliver
              1. 12.2.2.4.6.10.1  CRC Insertion
              2. 12.2.2.4.6.10.2  MTXER
              3. 12.2.2.4.6.10.3  Adaptive Performance Optimization (APO)
              4. 12.2.2.4.6.10.4  Inter-Packet-Gap Enforcement
              5. 12.2.2.4.6.10.5  Back Off
              6. 12.2.2.4.6.10.6  Programmable Transmit Inter-Packet Gap
              7. 12.2.2.4.6.10.7  Speed, Duplex and Pause Frame Support Negotiation
              8. 12.2.2.4.6.10.8  RMII Interface
                1. 12.2.2.4.6.10.8.1 Features
                2. 12.2.2.4.6.10.8.2 RMII Receive (RX)
                3. 12.2.2.4.6.10.8.3 RMII Transmit (TX)
              9. 12.2.2.4.6.10.9  RGMII Interface
                1. 12.2.2.4.6.10.9.1 Features
                2. 12.2.2.4.6.10.9.2 RGMII Receive (RX)
                3. 12.2.2.4.6.10.9.3 In-Band Mode of Operation
                4. 12.2.2.4.6.10.9.4 Forced Mode of Operation
                5. 12.2.2.4.6.10.9.5 RGMII Transmit (TX)
              10. 12.2.2.4.6.10.10 Frame Classification
              11. 12.2.2.4.6.10.11 Receive FIFO Architecture
            11. 12.2.2.4.6.11 Embedded Memories
            12. 12.2.2.4.6.12 Memory Error Detection and Correction
              1. 12.2.2.4.6.12.1 Packet Header ECC
              2. 12.2.2.4.6.12.2 Packet Protect CRC
              3. 12.2.2.4.6.12.3 Aggregator RAM Control
            13. 12.2.2.4.6.13 Ethernet Port Flow Control
              1. 12.2.2.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.2.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.2.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.2.4.6.13.2 Qbb (10/100/1G/10G) Receive Priority Based Flow Control (PFC)
              3. 12.2.2.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.2.4.6.14 PFC Trigger Rules
              1. 12.2.2.4.6.14.1 Destination Based Rule
              2. 12.2.2.4.6.14.2 Sum of Outflows Rule
              3. 12.2.2.4.6.14.3 Sum of Blocks Per Port Rule
              4. 12.2.2.4.6.14.4 Sum of Blocks Total Rule
              5. 12.2.2.4.6.14.5 Top of Receive FIFO Rule
            15. 12.2.2.4.6.15 Energy Efficient Ethernet Support (802.3az)
            16. 12.2.2.4.6.16 Ethernet Switch Latency
            17. 12.2.2.4.6.17 MAC Emulation Control
            18. 12.2.2.4.6.18 MAC Command IDLE
            19. 12.2.2.4.6.19 CPSW Network Statistics
              1. 12.2.2.4.6.19.1  Rx-only Statistics Descriptions
                1. 12.2.2.4.6.19.1.1  Good Rx Frames (Offset = 3A000h)
                2. 12.2.2.4.6.19.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 12.2.2.4.6.19.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 12.2.2.4.6.19.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 12.2.2.4.6.19.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 12.2.2.4.6.19.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 12.2.2.4.6.19.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 12.2.2.4.6.19.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 12.2.2.4.6.19.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 12.2.2.4.6.19.1.10 Rx Fragments (Offset = 3A024h)
                11. 12.2.2.4.6.19.1.11 RX IPG Error
                12. 12.2.2.4.6.19.1.12 ALE Drop (Offset = 3A028h)
                13. 12.2.2.4.6.19.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 12.2.2.4.6.19.1.14 Rx Octets (Offset = 3A030h)
                15. 12.2.2.4.6.19.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 12.2.2.4.6.19.1.16 Portmask Drop (Offset = 3A088h)
                17. 12.2.2.4.6.19.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 12.2.2.4.6.19.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 12.2.2.4.6.19.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.2.4.6.19.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.2.4.6.19.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.2.4.6.19.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.2.4.6.19.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.2.4.6.19.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.2.4.6.19.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.2.4.6.19.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.2.4.6.19.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.2.4.6.19.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.2.4.6.19.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.2.4.6.19.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
              2. 12.2.2.4.6.19.2  ALE Policer Match Red (Offset = 3A0C4h)
              3. 12.2.2.4.6.19.3  ALE Policer Match Yellow (Offset = 3A0C8h)
              4. 12.2.2.4.6.19.4  IET Receive Assembly Error (Offset = 3A140h)
              5. 12.2.2.4.6.19.5  IET Receive Assembly OK (Offset = 3A144h)
              6. 12.2.2.4.6.19.6  IET Receive SMD Error (Offset = 3A148h)
              7. 12.2.2.4.6.19.7  IET Receive Merge Fragment Count (Offset = 3A14Ch)
              8. 12.2.2.4.6.19.8  Tx-only Statistics Descriptions
                1. 12.2.2.4.6.19.8.1  Good Tx Frames (Offset = 3A034h)
                2. 12.2.2.4.6.19.8.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 12.2.2.4.6.19.8.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 12.2.2.4.6.19.8.4  Pause Tx Frames (Offset = 3A040h)
                5. 12.2.2.4.6.19.8.5  Deferred Tx Frames (Offset = 3A044h)
                6. 12.2.2.4.6.19.8.6  Collisions (Offset = 3A048h)
                7. 12.2.2.4.6.19.8.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 12.2.2.4.6.19.8.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 12.2.2.4.6.19.8.9  Excessive Collisions (Offset = 3A054h)
                10. 12.2.2.4.6.19.8.10 Late Collisions (Offset = 3A058h)
                11. 12.2.2.4.6.19.8.11 Carrier Sense Errors (Offset = 3A060h)
                12. 12.2.2.4.6.19.8.12 Tx Octets (Offset = 3A064h)
                13. 12.2.2.4.6.19.8.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 12.2.2.4.6.19.8.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8h)
                15. 12.2.2.4.6.19.8.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 12.2.2.4.6.19.8.16 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
                17. 12.2.2.4.6.19.8.17 IET Transmit Merge Hold Count (Offset = 3A150h)
              9. 12.2.2.4.6.19.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.2.4.6.19.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 12.2.2.4.6.19.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 12.2.2.4.6.19.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 12.2.2.4.6.19.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 12.2.2.4.6.19.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 12.2.2.4.6.19.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 12.2.2.4.6.19.9.7 Net Octets (Offset = 3A080h)
              10. 12.2.2.4.6.19.10 2324
          7. 12.2.2.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.2.4.7.1  CPSW0 CPTS Integration
            2. 12.2.2.4.7.2  CPTS Architecture
            3. 12.2.2.4.7.3  CPTS Initialization
            4. 12.2.2.4.7.4  32-bit Time Stamp Value
            5. 12.2.2.4.7.5  64-bit Time Stamp Value
            6. 12.2.2.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.2.4.7.7  64-bit Timestamp PPM
            8. 12.2.2.4.7.8  Event FIFO
            9. 12.2.2.4.7.9  Timestamp Compare Output
              1. 12.2.2.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.2.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.2.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.2.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.2.4.7.10 Timestamp Sync Output
            11. 12.2.2.4.7.11 Timestamp GENFn Output
              1. 12.2.2.4.7.11.1 GENFn Nudge
              2. 12.2.2.4.7.11.2 GENFn PPM
            12. 12.2.2.4.7.12 Timestamp ESTFn
            13. 12.2.2.4.7.13 Time Sync Events
              1. 12.2.2.4.7.13.1 Time Stamp Push Event
              2. 12.2.2.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.2.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.2.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.2.4.7.13.5 Ethernet Port Events
                1. 12.2.2.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.2.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.2.4.7.13.5.3 2352
            14. 12.2.2.4.7.14 Timestamp Compare Event
              1. 12.2.2.4.7.14.1 32-Bit Mode
              2. 12.2.2.4.7.14.2 64-Bit Mode
            15. 12.2.2.4.7.15 Host Transmit Event
            16. 12.2.2.4.7.16 CPTS Interrupt Handling
          8. 12.2.2.4.8 CPPI Streaming Packet Interface
            1. 12.2.2.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_5X Egress)
            2. 12.2.2.4.8.2 CPPI Receive Packet Streaming Interface (CPSW Ingress)
            3. 12.2.2.4.8.3 CPPI Checksum Offload
              1. 12.2.2.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.2.4.8.3.1.1 IPV4 UDP
                2. 12.2.2.4.8.3.1.2 IPV4 TCP
                3. 12.2.2.4.8.3.1.3 IPV6 UDP
                4. 12.2.2.4.8.3.1.4 IPV6 TCP
            4. 12.2.2.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.2.4.8.5 Egress Packet Operations
          9. 12.2.2.4.9 MII Management Interface (MDIO)
            1. 12.2.2.4.9.1 MDIO Frame Formats
            2. 12.2.2.4.9.2 MDIO Functional Description
        5. 12.2.2.5 CPSW0 Programming Guide
          1. 12.2.2.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.2.5.2 Ethernet MAC Reset or XGMII/GMII Mode Change Configuration
          3. 12.2.2.5.3 MDIO Software Interface
            1. 12.2.2.5.3.1 Initializing the MDIO Module
            2. 12.2.2.5.3.2 Writing Data To a PHY Register
            3. 12.2.2.5.3.3 Reading Data From a PHY Register
        6. 12.2.2.6 CPSW0 Registers
          1. 12.2.2.6.1  CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.2.6.2  CPSW0_SGMII Registers
          3. 12.2.2.6.3  CPSW0_MDIO Registers
          4. 12.2.2.6.4  CPSW0_CPTS Registers
          5. 12.2.2.6.5  CPSW0_CONTROL Registers
          6. 12.2.2.6.6  CPSW0_CPINT Registers
          7. 12.2.2.6.7  CPSW0_RAM Registers
          8. 12.2.2.6.8  CPSW0_STAT Registers
          9. 12.2.2.6.9  CPSW0_ALE Registers
          10. 12.2.2.6.10 CPSW0_PCSR Registers
          11. 12.2.2.6.11 CPSW0_ECC Registers
      3. 12.2.3 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.3.1 PCIe Subsystem Overview
          1. 12.2.3.1.1 PCIe Subsystem Features
          2. 12.2.3.1.2 PCIe Subsystem Not Supported Features
        2. 12.2.3.2 PCIe Subsystem Environment
        3. 12.2.3.3 PCIe Subsystem Integration
        4. 12.2.3.4 PCIe Subsystem Functional Description
          1. 12.2.3.4.1  PCIe Subsystem Block Diagram
            1. 12.2.3.4.1.1 PCIe Core Module
            2. 12.2.3.4.1.2 PCIe PHY Interface
            3. 12.2.3.4.1.3 CBA Infrastructure
            4. 12.2.3.4.1.4 VBUSM to AXI Bridges
            5. 12.2.3.4.1.5 AXI to VBUSM Bridges
            6. 12.2.3.4.1.6 VBUSP to APB Bridge
            7. 12.2.3.4.1.7 Custom Logic
          2. 12.2.3.4.2  PCIe Subsystem Reset Schemes
            1. 12.2.3.4.2.1 PCIe Conventional Reset
            2. 12.2.3.4.2.2 PCIe Function Level Reset
            3. 12.2.3.4.2.3 PCIe Reset Isolation
              1. 12.2.3.4.2.3.1 Root Port Reset with Device Not Reset
              2. 12.2.3.4.2.3.2 Device Reset with Root Port Not Reset
              3. 12.2.3.4.2.3.3 End Point Device Reset with Root Port Not Reset
              4. 12.2.3.4.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.3.4.2.4 PCIe Reset Limitations
            5. 12.2.3.4.2.5 PCIe Reset Requirements
          3. 12.2.3.4.3  PCIe Subsystem Power Management
            1. 12.2.3.4.3.1 CBA Power Management
          4. 12.2.3.4.4  PCIe Subsystem Interrupts
            1. 12.2.3.4.4.1 Interrupts Aggregation
            2. 12.2.3.4.4.2 Interrupt Generation in EP Mode
              1. 12.2.3.4.4.2.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.3.4.4.2.2 MSI and MSI-X Interrupt Generation
            3. 12.2.3.4.4.3 Interrupt Reception in EP Mode
              1. 12.2.3.4.4.3.1 PCIe Core Downstream Interrupts
              2. 12.2.3.4.4.3.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.3.4.4.3.3 PCIe Core Power Management Event Interrupts
              4. 12.2.3.4.4.3.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.3.4.4.3.5 PTM Valid Interrupt
            4. 12.2.3.4.4.4 Interrupt Generation in RP Mode
            5. 12.2.3.4.4.5 Interrupt Reception in RP Mode
              1. 12.2.3.4.4.5.1 PCIe Legacy Interrupt Reception in RP Mode
              2. 12.2.3.4.4.5.2 MSI/MSI-X Interrupt Reception in RP Mode
              3. 12.2.3.4.4.5.3 Advanced Error Reporting Interrupt
            6. 12.2.3.4.4.6 Common Interrupt Reception in RP and EP Modes
              1. 12.2.3.4.4.6.1 PCIe Local Interrupt
              2. 12.2.3.4.4.6.2 PHY Interrupt
              3. 12.2.3.4.4.6.3 Link down Interrupt
              4. 12.2.3.4.4.6.4 Transaction Error Interrupts
              5. 12.2.3.4.4.6.5 Power Management Event Interrupt
              6. 12.2.3.4.4.6.6 Active Internal Diagnostics Interrupts
            7. 12.2.3.4.4.7 ECC Aggregator Interrupts
            8. 12.2.3.4.4.8 CPTS Interrupt
          5. 12.2.3.4.5  PCIe Subsystem DMA Support
            1. 12.2.3.4.5.1 PCIe DMA Support in RP Mode
            2. 12.2.3.4.5.2 PCIe DMA Support in EP Mode
          6. 12.2.3.4.6  PCIe Subsystem Transactions
            1. 12.2.3.4.6.1 PCIe Supported Transactions
            2. 12.2.3.4.6.2 PCIe Transaction Limitations
          7. 12.2.3.4.7  PCIe Subsystem Address Translation
            1. 12.2.3.4.7.1 PCIe Inbound Address Translation
              1. 12.2.3.4.7.1.1 Root Port Inbound PCIe to AXI Address Translation
              2. 12.2.3.4.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.3.4.7.2 PCIe Outbound Address Translation
              1. 12.2.3.4.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.3.4.8  PCIe Subsystem Virtualization Support
            1. 12.2.3.4.8.1 End Point SR-IOV Support
            2. 12.2.3.4.8.2 Root Port ATS Support
            3. 12.2.3.4.8.3 VirtID Mapping
          9. 12.2.3.4.9  PCIe Subsystem Quality-of-Service (QoS)
          10. 12.2.3.4.10 PCIe Subsystem Precision Time Measurement (PTM)
          11. 12.2.3.4.11 PCIe Subsystem Loopback
            1. 12.2.3.4.11.1 PCIe PIPE Loopback
              1. 12.2.3.4.11.1.1 PIPE Loopback Master Mode
              2. 12.2.3.4.11.1.2 PIPE Loopback Slave Mode
          12. 12.2.3.4.12 PCIe Subsystem Error Handling
            1. 12.2.3.4.12.1 PCIe AXI to/from VBUSM Bus Error Mapping
          13. 12.2.3.4.13 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.3.4.13.1 PCIe Parity
            2. 12.2.3.4.13.2 ECC Aggregators
            3. 12.2.3.4.13.3 RAM ECC Inversion
          14. 12.2.3.4.14 LTSSM State Encoding
        5. 12.2.3.5 PCIe Subsystem Registers
          1. 12.2.3.5.1  PCIE_CORE_EP_PF Registers
          2. 12.2.3.5.2  PCIE_CORE_EP_VF Registers
          3. 12.2.3.5.3  PCIE_CORE_RP Registers
          4. 12.2.3.5.4  PCIE_CORE_LM Registers
          5. 12.2.3.5.5  PCIE_CORE_AXI Registers
          6. 12.2.3.5.6  PCIE_INTD Registers
          7. 12.2.3.5.7  PCIE_VMAP Registers
          8. 12.2.3.5.8  PCIE_CPTS Registers
          9. 12.2.3.5.9  PCIE_USER_CFG Registers
          10. 12.2.3.5.10 PCIE_ECC_AGGR0 Registers
          11. 12.2.3.5.11 PCIE_ECC_AGGR1 Registers
          12. 12.2.3.5.12 PCIE_DAT0 Registers
          13. 12.2.3.5.13 PCIE_DAT1 Registers
      4. 12.2.4 Universal Serial Bus (USB) Subsystem
        1. 12.2.4.1 USB Overview
          1. 12.2.4.1.1 USB Features
          2. 12.2.4.1.2 USB Not Supported Features
          3. 12.2.4.1.3 USB Terminology
        2. 12.2.4.2 USB Environment
        3. 12.2.4.3 USB Integration
        4. 12.2.4.4 USB Functional Description
          1. 12.2.4.4.1 USB Type-C Connector Support
          2. 12.2.4.4.2 USB Controller Reset
          3. 12.2.4.4.3 Overcurrent Detection
          4. 12.2.4.4.4 Top-Level Initialization Sequence
        5. 12.2.4.5 USB Registers
          1. 12.2.4.5.1 USB3P0SS_MMR_MMRVBP_USBSS_CMN Registers
          2. 12.2.4.5.2 USB_ECC_AGGR_CFG Registers
          3. 12.2.4.5.3 USB_RAMS_INJ_CFG Registers
      5. 12.2.5 Serializer/Deserializer (SerDes)
        1. 12.2.5.1 SerDes Overview
          1. 12.2.5.1.1 SerDes Features
          2. 12.2.5.1.2 Industry Standards Compatibility
        2. 12.2.5.2 SerDes Environment
          1. 12.2.5.2.1 SerDes I/Os
        3. 12.2.5.3 SerDes Integration
          1. 12.2.5.3.1 WIZ Settings
            1. 12.2.5.3.1.1 Interface Selection
            2. 12.2.5.3.1.2 Reference Clock Distribution
            3. 12.2.5.3.1.3 Internal Reference Clock Selection
        4. 12.2.5.4 SerDes Functional Description
          1. 12.2.5.4.1 SerDes Block Diagram
          2. 12.2.5.4.2 SerDes Programming Guide
    3. 12.3 Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 FSS Not Supported Features
        2. 12.3.1.2 FSS Environment
          1. 12.3.1.2.1 FSS Typical Application
        3. 12.3.1.3 FSS Integration
          1. 12.3.1.3.1 FSS Integration in MCU Domain
        4. 12.3.1.4 FSS Functional Description
          1. 12.3.1.4.1 FSS Block Diagram
          2. 12.3.1.4.2 FSS ECC Support
            1. 12.3.1.4.2.1 FSS ECC Calculation
          3. 12.3.1.4.3 FSS Modes of Operation
          4. 12.3.1.4.4 FSS Regions
            1. 12.3.1.4.4.1 FSS Regions Boot Size Configuration
          5. 12.3.1.4.5 FSS Memory Regions
        5. 12.3.1.5 FSS Programming Guide
          1. 12.3.1.5.1 FSS Initialization Sequence
          2. 12.3.1.5.2 FSS Real-Time Operation
          3. 12.3.1.5.3 FSS Power Up/Down Sequence
        6. 12.3.1.6 FSS Registers
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Not Supported Features
        2. 12.3.2.2 OSPI Environment
        3. 12.3.2.3 OSPI Integration
          1. 12.3.2.3.1 OSPI Integration in MCU Domain
        4. 12.3.2.4 OSPI Functional Description
          1. 12.3.2.4.1  OSPI Block Diagram
            1. 12.3.2.4.1.1 Data Target Interface
            2. 12.3.2.4.1.2 Configuration Target Interface
            3. 12.3.2.4.1.3 OSPI Clock Domains
          2. 12.3.2.4.2  OSPI Modes
            1. 12.3.2.4.2.1 Read Data Capture
              1. 12.3.2.4.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.4.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.4.2.1.3 Data Capturing Mechanism Using PHY Module
            2. 12.3.2.4.2.2 External Pull Down on DQS
          3. 12.3.2.4.3  OSPI Power Management
          4. 12.3.2.4.4  Auto HW Polling
          5. 12.3.2.4.5  Flash Reset
          6. 12.3.2.4.6  OSPI Memory Regions
          7. 12.3.2.4.7  OSPI Interrupt Requests
          8. 12.3.2.4.8  OSPI Data Interface
            1. 12.3.2.4.8.1 Data Interface Address Remapping
            2. 12.3.2.4.8.2 Write Protection
            3. 12.3.2.4.8.3 Access Forwarding
          9. 12.3.2.4.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.4.10.1 Indirect Read Controller
              1. 12.3.2.4.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.4.10.2 Indirect Write Controller
              1. 12.3.2.4.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.4.10.3 Indirect Access Queuing
            4. 12.3.2.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.4.10.5 Accessing the SRAM
          11. 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.4.11.1 Servicing a STIG Request
            2. 12.3.2.4.11.2 2576
          12. 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.4.13 OSPI Command Translation
          14. 12.3.2.4.14 Selecting the Flash Instruction Type
          15. 12.3.2.4.15 OSPI Data Integrity
          16. 12.3.2.4.16 OSPI PHY Module
            1. 12.3.2.4.16.1 PHY Pipeline Mode
            2. 12.3.2.4.16.2 Read Data Capturing by the PHY Module
        5. 12.3.2.5 OSPI Programming Guide
          1. 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.5.4 Using SPI Legacy Mode
          5. 12.3.2.5.5 Entering XIP Mode from POR
          6. 12.3.2.5.6 Entering XIP Mode Otherwise
          7. 12.3.2.5.7 Exiting XIP Mode
        6. 12.3.2.6 OSPI Registers
      3. 12.3.3 HyperBus Interface
        1. 12.3.3.1 HyperBus Overview
          1. 12.3.3.1.1 HyperBus Features
          2. 12.3.3.1.2 HyperBus Not Supported Features
        2. 12.3.3.2 HyperBus Environment
        3. 12.3.3.3 HyperBus Integration
          1. 12.3.3.3.1 HyperBus Integration in MCU Domain
        4. 12.3.3.4 HyperBus Functional Description
          1. 12.3.3.4.1 HyperBus Interrupts
          2. 12.3.3.4.2 HyperBus ECC Support
            1. 12.3.3.4.2.1 ECC Aggregator
          3. 12.3.3.4.3 HyperBus Internal FIFOs
          4. 12.3.3.4.4 HyperBus Data Regions
          5. 12.3.3.4.5 HyperBus True Continuous Read (TCR) Mode
        5. 12.3.3.5 HyperBus Programming Guide
          1. 12.3.3.5.1 HyperBus Initialization Sequence
            1. 12.3.3.5.1.1 HyperFlash Access
            2. 12.3.3.5.1.2 HyperRAM Access
          2. 12.3.3.5.2 HyperBus Real-time Operating Requirements
          3. 12.3.3.5.3 HyperBus Power Up/Down Sequence
        6. 12.3.3.6 HyperBus Registers
      4. 12.3.4 General-Purpose Memory Controller (GPMC)
        1. 12.3.4.1 GPMC Overview
          1. 12.3.4.1.1 GPMC Features
          2. 12.3.4.1.2 GPMC Not Supported Features
        2. 12.3.4.2 GPMC Environment
          1. 12.3.4.2.1 GPMC Modes
          2. 12.3.4.2.2 GPMC I/O Signals
        3. 12.3.4.3 GPMC Integration
          1. 12.3.4.3.1 GPMC Integration in MAIN Domain
        4. 12.3.4.4 GPMC Functional Description
          1. 12.3.4.4.1  GPMC Block Diagram
          2. 12.3.4.4.2  GPMC Clock Configuration
          3. 12.3.4.4.3  GPMC Power Management
          4. 12.3.4.4.4  GPMC Interrupt Requests
          5. 12.3.4.4.5  GPMC Interconnect Port Interface
          6. 12.3.4.4.6  GPMC Address and Data Bus
            1. 12.3.4.4.6.1 GPMC I/O Configuration Setting
          7. 12.3.4.4.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.4.4.7.1 Chip-Select Base Address and Region Size
            2. 12.3.4.4.7.2 Access Protocol
              1. 12.3.4.4.7.2.1 Supported Devices
              2. 12.3.4.4.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.4.4.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.4.4.7.3 External Signals
              1. 12.3.4.4.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.4.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.4.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.4.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.4.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.4.4.7.3.1.5 Wait With NAND Device
                6. 12.3.4.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.4.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.4.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.4.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.4.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.4.4.7.3.2 DIR Pin
              3. 12.3.4.4.7.3.3 Reset
              4. 12.3.4.4.7.3.4 Write Protect Signal (nWP)
              5. 12.3.4.4.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.4.4.7.4 Error Handling
          8. 12.3.4.4.8  GPMC Timing Setting
            1. 12.3.4.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.4.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.4.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.4.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.4.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.4.4.8.6  GPMC_CLKOUT
            7. 12.3.4.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.4.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.4.4.8.8.1 Access Time on Read Access
              2. 12.3.4.4.8.8.2 Access Time on Write Access
            9. 12.3.4.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.4.4.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.4.4.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.4.4.8.10 Bus Keeping Support
          9. 12.3.4.4.9  GPMC NOR Access Description
            1. 12.3.4.4.9.1 Asynchronous Access Description
              1. 12.3.4.4.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.4.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.4.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.4.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.4.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.4.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.4.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.4.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.4.4.9.2 Synchronous Access Description
              1. 12.3.4.4.9.2.1 Synchronous Single Read
              2. 12.3.4.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.4.4.9.2.3 Synchronous Single Write
              4. 12.3.4.4.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.4.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.4.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.4.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.4.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.4.4.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.4.4.9.4 Page and Burst Support
            5. 12.3.4.4.9.5 System Burst vs External Device Burst Support
          10. 12.3.4.4.10 GPMC pSRAM Access Specificities
          11. 12.3.4.4.11 GPMC NAND Access Description
            1. 12.3.4.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.4.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.4.4.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.4.4.11.1.3 Command Latch Cycle
              4. 12.3.4.4.11.1.4 Address Latch Cycle
              5. 12.3.4.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.4.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.4.4.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.4.4.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.4.4.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.4.4.11.2 NAND Device-Ready Pin
              1. 12.3.4.4.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.4.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.4.4.11.3 ECC Calculator
              1. 12.3.4.4.11.3.1 Hamming Code
                1. 12.3.4.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.4.4.11.3.1.2 ECC Enabling
                3. 12.3.4.4.11.3.1.3 ECC Computation
                4. 12.3.4.4.11.3.1.4 ECC Comparison and Correction
                5. 12.3.4.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.4.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.4.4.11.3.2 BCH Code
                1. 12.3.4.4.11.3.2.1 Requirements
                2. 12.3.4.4.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.4.4.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.4.4.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.4.4.11.3.2.2.3 Wrapping Modes
                    1. 4.4.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 4.4.11.3.2.2.3.2  Mode 0x1
                    3. 4.4.11.3.2.2.3.3  Mode 0xA (10)
                    4. 4.4.11.3.2.2.3.4  Mode 0x2
                    5. 4.4.11.3.2.2.3.5  Mode 0x3
                    6. 4.4.11.3.2.2.3.6  Mode 0x7
                    7. 4.4.11.3.2.2.3.7  Mode 0x8
                    8. 4.4.11.3.2.2.3.8  Mode 0x4
                    9. 4.4.11.3.2.2.3.9  Mode 0x9
                    10. 4.4.11.3.2.2.3.10 Mode 0x5
                    11. 4.4.11.3.2.2.3.11 Mode 0xB (11)
                    12. 4.4.11.3.2.2.3.12 Mode 0x6
                3. 12.3.4.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.4.4.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.4.4.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.4.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.4.4.11.4 Prefetch and Write-Posting Engine
              1. 12.3.4.4.11.4.1 General Facts About the Engine Configuration
              2. 12.3.4.4.11.4.2 Prefetch Mode
              3. 12.3.4.4.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.4.4.11.4.4 Write-Posting Mode
              5. 12.3.4.4.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.4.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.4.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.4.4.12 GPMC Use Cases and Tips
            1. 12.3.4.4.12.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.4.4.12.1.1 External Memory Attached to the GPMC Module
              2. 12.3.4.4.12.1.2 Typical GPMC Setup
                1. 12.3.4.4.12.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.4.4.12.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.4.4.12.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.4.4.12.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.4.4.12.2.1 Supported Memories or Devices
                1. 12.3.4.4.12.2.1.1 Memory Pin Multiplexing
                2. 12.3.4.4.12.2.1.2 NAND Interface Protocol
                3. 12.3.4.4.12.2.1.3 NOR Interface Protocol
                4. 12.3.4.4.12.2.1.4 Other Technologies
        5. 12.3.4.5 GPMC Basic Programming Model
          1. 12.3.4.5.1 GPMC High-Level Programming Model Overview
          2. 12.3.4.5.2 GPMC Initialization
          3. 12.3.4.5.3 GPMC Configuration in NOR Mode
          4. 12.3.4.5.4 GPMC Configuration in NAND Mode
          5. 12.3.4.5.5 Set Memory Access
          6. 12.3.4.5.6 GPMC Timing Parameters
            1. 12.3.4.5.6.1 GPMC Timing Parameters Formulas
              1. 12.3.4.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.4.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.4.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
        6. 12.3.4.6 GPMC Registers
      5. 12.3.5 Error Location Module (ELM)
        1. 12.3.5.1 ELM Overview
          1. 12.3.5.1.1 ELM Features
          2. 12.3.5.1.2 ELM Not Supported Features
        2. 12.3.5.2 ELM Integration
          1. 12.3.5.2.1 ELM Integration in MAIN Domain
        3. 12.3.5.3 ELM Functional Description
          1. 12.3.5.3.1 ELM Software Reset
          2. 12.3.5.3.2 ELM Power Management
          3. 12.3.5.3.3 ELM Interrupt Requests
          4. 12.3.5.3.4 ELM Processing Initialization
          5. 12.3.5.3.5 ELM Processing Sequence
          6. 12.3.5.3.6 ELM Processing Completion
        4. 12.3.5.4 ELM Basic Programming Model
          1. 12.3.5.4.1 ELM Low-Level Programming Model
            1. 12.3.5.4.1.1 Processing Initialization
            2. 12.3.5.4.1.2 Read Results
            3. 12.3.5.4.1.3 2786
          2. 12.3.5.4.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.5.4.3 Use Case: ELM Used in Page Mode
        5. 12.3.5.5 ELM Registers
      6. 12.3.6 Multi-Media Card Secure Digital (MMCSD) Interface
        1. 12.3.6.1 MMCSD Overview
          1. 12.3.6.1.1 MMCSD Features
          2. 12.3.6.1.2 MMCSD Not Supported Features
        2. 12.3.6.2 MMCSD Environment
          1. 12.3.6.2.1 Protocol and Data Format
            1. 12.3.6.2.1.1 Protocol
            2. 12.3.6.2.1.2 Data Format
              1. 12.3.6.2.1.2.1 Coding Scheme for Command Token
              2. 12.3.6.2.1.2.2 Coding Scheme for Response Token
              3. 12.3.6.2.1.2.3 Coding Scheme for Data Token
        3. 12.3.6.3 MMCSD Integration
          1. 12.3.6.3.1 MMCSD Integration in MAIN Domain
        4. 12.3.6.4 MMCSD Functional Description
          1. 12.3.6.4.1 Block Diagram
          2. 12.3.6.4.2 Memory Regions
          3. 12.3.6.4.3 Interrupt Requests
          4. 12.3.6.4.4 ECC Support
            1. 12.3.6.4.4.1 ECC Aggregator
          5. 12.3.6.4.5 Advanced DMA
          6. 12.3.6.4.6 eMMC PHY BIST
            1. 12.3.6.4.6.1 BIST Overview
            2. 12.3.6.4.6.2 BIST Modes
              1. 12.3.6.4.6.2.1 DS Mode
              2. 12.3.6.4.6.2.2 HS Mode with TXDLY using DLL
              3. 12.3.6.4.6.2.3 HS Mode with TXDLY using Delay Chain
              4. 12.3.6.4.6.2.4 DDR50 Mode with TXDLY using DLL
              5. 12.3.6.4.6.2.5 DDR50 Mode with TXDLY using Delay Chain
              6. 12.3.6.4.6.2.6 HS200 Mode with TX/RXDLY using DLL
              7. 12.3.6.4.6.2.7 HS200 Mode with TX/RXDLY using Delay Chain
              8. 12.3.6.4.6.2.8 HS400 Mode
            3. 12.3.6.4.6.3 BIST Functionality
            4. 12.3.6.4.6.4 Signal Interface
            5. 12.3.6.4.6.5 Programming Flow
              1. 12.3.6.4.6.5.1 DS Mode
                1. 12.3.6.4.6.5.1.1 Configuration
                2. 12.3.6.4.6.5.1.2 BIST Programming
              2. 12.3.6.4.6.5.2 HS Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.2.1 Configuration
                2. 12.3.6.4.6.5.2.2 BIST Programming
              3. 12.3.6.4.6.5.3 HS Mode with DLL
                1. 12.3.6.4.6.5.3.1 Configuration
                2. 12.3.6.4.6.5.3.2 BIST Programming
              4. 12.3.6.4.6.5.4 DDR52 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.4.1 Configuration
                2. 12.3.6.4.6.5.4.2 BIST Programming
              5. 12.3.6.4.6.5.5 DDR52 Mode with DLL
                1. 12.3.6.4.6.5.5.1 Configuration
                2. 12.3.6.4.6.5.5.2 BIST Programming
              6. 12.3.6.4.6.5.6 HS200 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.6.1 Configuration
                2. 12.3.6.4.6.5.6.2 BIST Programming
              7. 12.3.6.4.6.5.7 HS200 Mode with DLL
                1. 12.3.6.4.6.5.7.1 Configuration
                2. 12.3.6.4.6.5.7.2 BIST Programming
              8. 12.3.6.4.6.5.8 HS400 Mode with DLL
                1. 12.3.6.4.6.5.8.1 Configuration
                2. 12.3.6.4.6.5.8.2 BIST Programming
            6. 12.3.6.4.6.6 HS200 BIST Result Check Procedure
        5. 12.3.6.5 MMCSD Programming Guide
          1. 12.3.6.5.1 Sequences
            1. 12.3.6.5.1.1  SD Card Detection
            2. 12.3.6.5.1.2  SD Clock Control
              1. 12.3.6.5.1.2.1 Internal Clock Setup Sequence
              2. 12.3.6.5.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.6.5.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.6.5.1.3  SD Bus Power Control
            4. 12.3.6.5.1.4  Changing Bus Width
            5. 12.3.6.5.1.5  Timeout Setting on DAT Line
            6. 12.3.6.5.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.6.5.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.6.5.1.7  SD Transaction Generation
              1. 12.3.6.5.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.6.5.1.7.1.2 The Sequence to Finalize a Command
                3. 12.3.6.5.1.7.1.3 2865
              2. 12.3.6.5.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.2.1 Not using DMA
                2. 12.3.6.5.1.7.2.2 Using SDMA
                3. 12.3.6.5.1.7.2.3 Using ADMA
            8. 12.3.6.5.1.8  Abort Transaction
              1. 12.3.6.5.1.8.1 Asynchronous Abort
              2. 12.3.6.5.1.8.2 Synchronous Abort
            9. 12.3.6.5.1.9  Changing Bus Speed Mode
            10. 12.3.6.5.1.10 Error Recovery
              1. 12.3.6.5.1.10.1 Error Interrupt Recovery
              2. 12.3.6.5.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.6.5.1.11 Wakeup Control (Optional)
            12. 12.3.6.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.6.5.1.12.1 Suspend Sequence
              2. 12.3.6.5.1.12.2 Resume Sequence
              3. 12.3.6.5.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.6.5.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.6.5.2 Driver Flow Sequence
            1. 12.3.6.5.2.1 Host Controller Setup and Card Detection
              1. 12.3.6.5.2.1.1 Host Controller Setup Sequence
              2. 12.3.6.5.2.1.2 Card Interface Detection Sequence
            2. 12.3.6.5.2.2 Boot Operation
              1. 12.3.6.5.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.6.5.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.6.5.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.6.5.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.6.5.2.3.1 Sampling Clock Tuning
              2. 12.3.6.5.2.3.2 Tuning Modes
              3. 12.3.6.5.2.3.3 Re-Tuning Mode 2
            4. 12.3.6.5.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.6.5.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.6.5.2.4.2 Task Issuance Sequence
              3. 12.3.6.5.2.4.3 Task Execution and Completion Sequence
              4. 12.3.6.5.2.4.4 Task Discard and Clear Sequence
              5. 12.3.6.5.2.4.5 Error Detect and Recovery when CQ is enabled
        6. 12.3.6.6 MMCSD Registers
          1. 12.3.6.6.1 MMCSD0 Subsystem Registers
          2. 12.3.6.6.2 MMCSD0 RX RAM ECC Aggregator Registers
          3. 12.3.6.6.3 MMCSD0 TX RAM ECC Aggregator Registers
          4. 12.3.6.6.4 MMCSD0 Host Controller Registers
          5. 12.3.6.6.5 MMCSD1 Subsystem Registers
          6. 12.3.6.6.6 MMCSD1 RX RAM ECC Aggregator Registers
          7. 12.3.6.6.7 MMCSD1 TX RAM ECC Aggregator Registers
          8. 12.3.6.6.8 MMCSD1 Host Controller Registers
    4. 12.4 Industrial and Control Interfaces
      1. 12.4.1 Enhanced Capture (ECAP) Module
        1. 12.4.1.1 ECAP Overview
          1. 12.4.1.1.1 ECAP Features
        2. 12.4.1.2 ECAP Environment
          1. 12.4.1.2.1 ECAP I/O Interface
        3. 12.4.1.3 ECAP Integration
          1. 12.4.1.3.1 Daisy-Chain Connectivity between ECAP Modules
        4. 12.4.1.4 ECAP Functional Description
          1. 12.4.1.4.1 Capture and APWM Operating Modes
            1. 12.4.1.4.1.1 ECAP Capture Mode Description
              1. 12.4.1.4.1.1.1 ECAP Event Prescaler
              2. 12.4.1.4.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.1.4.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.1.4.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.1.4.1.1.5 CAP1-CAP4 Registers
              6. 12.4.1.4.1.1.6 ECAP Interrupt Control
              7. 12.4.1.4.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.1.4.1.2 ECAP APWM Mode Operation
          2. 12.4.1.4.2 Summary of ECAP Functional Registers
        5. 12.4.1.5 ECAP Use Cases
          1. 12.4.1.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.1.5.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.1.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.1.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.1.5.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.1.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.1.5.5 Application of the APWM Mode
            1. 12.4.1.5.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.1.5.5.1.1 Code Snippet for APWM Mode
            2. 12.4.1.5.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.1.5.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.1.5.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.1.5.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
        6. 12.4.1.6 ECAP Registers
      2. 12.4.2 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.2.1 EPWM Overview
          1. 12.4.2.1.1 EPWM Features
          2. 12.4.2.1.2 EPWM Not Supported Features
          3. 12.4.2.1.3 2951
        2. 12.4.2.2 EPWM Environment
          1. 12.4.2.2.1 EPWM I/O Interface
        3. 12.4.2.3 EPWM Integration
          1. 12.4.2.3.1 Device Specific EPWM Features
          2. 12.4.2.3.2 Daisy-Chain Connectivity between EPWM Modules
          3. 12.4.2.3.3 ADC start of conversion signals (PWM_SOCA and PWM_SOCB)
          4. 12.4.2.3.4 EPWM Modules Time Base Clock Gating
        4. 12.4.2.4 EPWM Functional Description
          1. 12.4.2.4.1  EPWM Submodule Features
            1. 12.4.2.4.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.2.4.2  EPWM Time-Base (TB) Submodule
            1. 12.4.2.4.2.1 Overview
            2. 12.4.2.4.2.2 2964
            3. 12.4.2.4.2.3 Controlling and Monitoring the EPWM Time-Base Submodule
            4. 12.4.2.4.2.4 Calculating PWM Period and Frequency
              1. 12.4.2.4.2.4.1 EPWM Time-Base Period Shadow Register
              2. 12.4.2.4.2.4.2 EPWM Time-Base Counter Synchronization
            5. 12.4.2.4.2.5 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            6. 12.4.2.4.2.6 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.2.4.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.2.4.3.1 Overview
            2. 12.4.2.4.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.2.4.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.2.4.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.2.4.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.2.4.4.1 Overview
            2. 12.4.2.4.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.2.4.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.2.4.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.2.4.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.2.4.5.1 Overview
            2. 12.4.2.4.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.2.4.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.2.4.6  EPWM-Chopper (PC) Submodule
            1. 12.4.2.4.6.1 Overview
            2. 12.4.2.4.6.2 2987
            3. 12.4.2.4.6.3 Controlling the EPWM-Chopper Submodule
            4. 12.4.2.4.6.4 Operational Highlights for the EPWM-Chopper Submodule
            5. 12.4.2.4.6.5 EPWM-Chopper Waveforms
              1. 12.4.2.4.6.5.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.2.4.6.5.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.2.4.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.2.4.7.1 Overview
            2. 12.4.2.4.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.2.4.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.2.4.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.2.4.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.2.4.8.1 Overview
            2. 12.4.2.4.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.2.4.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.2.4.8.4 3002
          9. 12.4.2.4.9  EPWM High Resolution (HRPWM) Submodule
            1. 12.4.2.4.9.1 Overview
            2. 12.4.2.4.9.2 Architecture of the High-Resolution PWM Submodule
            3. 12.4.2.4.9.3 Controlling and Monitoring the High-Resolution PWM Submodule
            4. 12.4.2.4.9.4 Configuring the High-Resolution PWM Submodule
            5. 12.4.2.4.9.5 Operational Highlights for the High-Resolution PWM Submodule
              1. 12.4.2.4.9.5.1 HRPWM Edge Positioning
              2. 12.4.2.4.9.5.2 HRPWM Scaling Considerations
              3. 12.4.2.4.9.5.3 HRPWM Duty Cycle Range Limitation
          10. 12.4.2.4.10 EPWM / HRPWM Functional Register Groups
          11. 12.4.2.4.11 Proper EPWM Interrupt Initialization Procedure
        5. 12.4.2.5 EPWM Registers
      3. 12.4.3 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.3.1 EQEP Overview
          1. 12.4.3.1.1 EQEP Features
          2. 12.4.3.1.2 EQEP Not Supported Features
        2. 12.4.3.2 EQEP Environment
          1. 12.4.3.2.1 EQEP I/O Interface
        3. 12.4.3.3 EQEP Integration
          1. 12.4.3.3.1 Device Specific EQEP Features
        4. 12.4.3.4 EQEP Functional Description
          1. 12.4.3.4.1 EQEP Inputs
          2. 12.4.3.4.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.3.4.2.1 EQEP Position Counter Input Modes
              1. 12.4.3.4.2.1.1 Quadrature Count Mode
              2. 12.4.3.4.2.1.2 EQEP Direction-count Mode
              3. 12.4.3.4.2.1.3 EQEP Up-Count Mode
              4. 12.4.3.4.2.1.4 EQEP Down-Count Mode
            2. 12.4.3.4.2.2 EQEP Input Polarity Selection
            3. 12.4.3.4.2.3 EQEP Position-Compare Sync Output
          3. 12.4.3.4.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.3.4.3.1 EQEP Position Counter Operating Modes
              1. 12.4.3.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.3.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.3.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.3.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.3.4.3.2 EQEP Position Counter Latch
              1. 12.4.3.4.3.2.1 Index Event Latch
              2. 12.4.3.4.3.2.2 EQEP Strobe Event Latch
            3. 12.4.3.4.3.3 EQEP Position Counter Initialization
            4. 12.4.3.4.3.4 EQEP Position-Compare Unit
          4. 12.4.3.4.4 EQEP Edge Capture Unit
          5. 12.4.3.4.5 EQEP Watchdog
          6. 12.4.3.4.6 Unit Timer Base
          7. 12.4.3.4.7 EQEP Interrupt Structure
          8. 12.4.3.4.8 Summary of EQEP Functional Registers
        5. 12.4.3.5 EQEP Registers
      4. 12.4.4 Controller Area Network (MCAN)
        1. 12.4.4.1 MCAN Overview
          1. 12.4.4.1.1 MCAN Features
          2. 12.4.4.1.2 MCAN Not Supported Features
        2. 12.4.4.2 MCAN Environment
          1. 12.4.4.2.1 CAN Network Basics
        3. 12.4.4.3 MCAN Integration
          1. 12.4.4.3.1 MCAN Integration in MCU Domain
          2. 12.4.4.3.2 MCAN Integration in MAIN Domain
        4. 12.4.4.4 MCAN Functional Description
          1. 12.4.4.4.1  Module Clocking Requirements
          2. 12.4.4.4.2  Interrupt and DMA Requests
            1. 12.4.4.4.2.1 Interrupt Requests
            2. 12.4.4.4.2.2 DMA Requests
            3. 12.4.4.4.2.3 3064
          3. 12.4.4.4.3  Operating Modes
            1. 12.4.4.4.3.1 Software Initialization
            2. 12.4.4.4.3.2 Normal Operation
            3. 12.4.4.4.3.3 CAN FD Operation
            4. 12.4.4.4.3.4 Transmitter Delay Compensation
              1. 12.4.4.4.3.4.1 Description
              2. 12.4.4.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.4.4.3.5 Restricted Operation Mode
            6. 12.4.4.4.3.6 Bus Monitoring Mode
            7. 12.4.4.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.4.4.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.4.4.3.8 Power Down (Sleep Mode)
              1. 12.4.4.4.3.8.1 External Clock Stop Mode
              2. 12.4.4.4.3.8.2 Suspend Mode
              3. 12.4.4.4.3.8.3 Wakeup request
            9. 12.4.4.4.3.9 Test Modes
              1. 12.4.4.4.3.9.1 Internal Loopback Mode
          4. 12.4.4.4.4  Timestamp Generation
            1. 12.4.4.4.4.1 External Timestamp Counter
          5. 12.4.4.4.5  Timeout Counter
          6. 12.4.4.4.6  ECC Support
            1. 12.4.4.4.6.1 ECC Wrapper
            2. 12.4.4.4.6.2 ECC Aggregator
          7. 12.4.4.4.7  Rx Handling
            1. 12.4.4.4.7.1 Acceptance Filtering
              1. 12.4.4.4.7.1.1 Range Filter
              2. 12.4.4.4.7.1.2 Filter for specific IDs
              3. 12.4.4.4.7.1.3 Classic Bit Mask Filter
              4. 12.4.4.4.7.1.4 Standard Message ID Filtering
              5. 12.4.4.4.7.1.5 Extended Message ID Filtering
            2. 12.4.4.4.7.2 Rx FIFOs
              1. 12.4.4.4.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.4.4.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.4.4.7.3 Dedicated Rx Buffers
              1. 12.4.4.4.7.3.1 Rx Buffer Handling
            4. 12.4.4.4.7.4 Debug on CAN Support
          8. 12.4.4.4.8  Tx Handling
            1. 12.4.4.4.8.1 Transmit Pause
            2. 12.4.4.4.8.2 Dedicated Tx Buffers
            3. 12.4.4.4.8.3 Tx FIFO
            4. 12.4.4.4.8.4 Tx Queue
            5. 12.4.4.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.4.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.4.4.8.7 Transmit Cancellation
            8. 12.4.4.4.8.8 Tx Event Handling
          9. 12.4.4.4.9  FIFO Acknowledge Handling
          10. 12.4.4.4.10 Message RAM
            1. 12.4.4.4.10.1 Message RAM Configuration
            2. 12.4.4.4.10.2 Rx Buffer and FIFO Element
            3. 12.4.4.4.10.3 Tx Buffer Element
            4. 12.4.4.4.10.4 Tx Event FIFO Element
            5. 12.4.4.4.10.5 Standard Message ID Filter Element
            6. 12.4.4.4.10.6 Extended Message ID Filter Element
        5. 12.4.4.5 MCAN Registers
          1. 12.4.4.5.1 MCAN Subsystem Registers
          2. 12.4.4.5.2 MCAN Core Registers
          3. 12.4.4.5.3 MCAN ECC Aggregator Registers
    5. 12.5 Audio Interfaces
      1. 12.5.1 Audio Tracking Logic (ATL)
        1. 12.5.1.1 ATL Overview
          1. 12.5.1.1.1 ATL Features Overview
          2. 12.5.1.1.2 ATL Not Supported Features
    6. 12.6 Timer Modules
      1. 12.6.1 Global Timebase Counter (GTC)
        1. 12.6.1.1 GTC Overview
          1. 12.6.1.1.1 GTC Features
          2. 12.6.1.1.2 GTC Not Supported Features
        2. 12.6.1.2 GTC Integration
        3. 12.6.1.3 GTC Functional Description
          1. 12.6.1.3.1 GTC Block Diagram
          2. 12.6.1.3.2 GTC Counter
          3. 12.6.1.3.3 GTC Gray Encoder
          4. 12.6.1.3.4 GTC Push Event Generation
          5. 12.6.1.3.5 GTC Register Partitioning
        4. 12.6.1.4 GTC Registers
          1. 12.6.1.4.1 GTC0_GTC_CFG0 Registers
          2. 12.6.1.4.2 GTC0_GTC_CFG1 Registers
          3. 12.6.1.4.3 GTC0_GTC_CFG2 Registers
          4. 12.6.1.4.4 GTC0_GTC_CFG3 Registers
      2. 12.6.2 Windowed Watchdog Timer (WWDT)
        1. 12.6.2.1 RTI Overview
          1. 12.6.2.1.1 RTI Features
          2. 12.6.2.1.2 RTI Not Supported Features
        2. 12.6.2.2 RTI Integration
          1. 12.6.2.2.1 RTI Integration in MCU Domain
          2. 12.6.2.2.2 RTI Integration in MAIN Domain
        3. 12.6.2.3 RTI Functional Description
          1. 12.6.2.3.1 RTI Counter Operation
          2. 12.6.2.3.2 RTI Digital Watchdog
          3. 12.6.2.3.3 RTI Digital Windowed Watchdog
          4. 12.6.2.3.4 RTI Low Power Mode Operation
          5. 12.6.2.3.5 RTI Debug Mode Behavior
        4. 12.6.2.4 RTI Registers
      3. 12.6.3 Timers
        1. 12.6.3.1 Timers Overview
          1. 12.6.3.1.1 Timers Features
          2. 12.6.3.1.2 Timers Not Supported Features
        2. 12.6.3.2 Timers Environment
          1. 12.6.3.2.1 Timer External System Interface
        3. 12.6.3.3 Timers Integration
          1. 12.6.3.3.1 Timers Integration in MCU Domain
          2. 12.6.3.3.2 Timers Integration in MAIN Domain
        4. 12.6.3.4 Timers Functional Description
          1. 12.6.3.4.1  Timer Block Diagram
          2. 12.6.3.4.2  Timer Power Management
            1. 12.6.3.4.2.1 Wake-Up Capability
          3. 12.6.3.4.3  Timer Software Reset
          4. 12.6.3.4.4  Timer Interrupts
          5. 12.6.3.4.5  Timer Mode Functionality
            1. 12.6.3.4.5.1 1-ms Tick Generation
          6. 12.6.3.4.6  Timer Capture Mode Functionality
          7. 12.6.3.4.7  Timer Compare Mode Functionality
          8. 12.6.3.4.8  Timer Prescaler Functionality
          9. 12.6.3.4.9  Timer Pulse-Width Modulation
          10. 12.6.3.4.10 Timer Counting Rate
          11. 12.6.3.4.11 Timer Under Emulation
          12. 12.6.3.4.12 Accessing Timer Registers
            1. 12.6.3.4.12.1 Writing to Timer Registers
              1. 12.6.3.4.12.1.1 Write Posting Synchronization Mode
              2. 12.6.3.4.12.1.2 Write Nonposting Synchronization Mode
            2. 12.6.3.4.12.2 Reading From Timer Counter Registers
              1. 12.6.3.4.12.2.1 Read Posted
              2. 12.6.3.4.12.2.2 Read Non-Posted
          13. 12.6.3.4.13 Timer Posted Mode Selection
        5. 12.6.3.5 Timers Low-Level Programming Models
          1. 12.6.3.5.1 Timer Global Initialization
            1. 12.6.3.5.1.1 Global Initialization of Surrounding Modules
            2. 12.6.3.5.1.2 Timer Module Global Initialization
              1. 12.6.3.5.1.2.1 Main Sequence – Timer Module Global Initialization
          2. 12.6.3.5.2 Timer Operational Mode Configuration
            1. 12.6.3.5.2.1 Timer Mode
              1. 12.6.3.5.2.1.1 Main Sequence – Timer Mode Configuration
            2. 12.6.3.5.2.2 Timer Compare Mode
              1. 12.6.3.5.2.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.6.3.5.2.3 Timer Capture Mode
              1. 12.6.3.5.2.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.6.3.5.2.3.2 Subsequence – Initialize Capture Mode
              3. 12.6.3.5.2.3.3 Subsequence – Detect Event
            4. 12.6.3.5.2.4 Timer PWM Mode
              1. 12.6.3.5.2.4.1 Main Sequence – Timer PWM Mode Configuration
        6. 12.6.3.6 Timers Registers
    7. 12.7 Internal Diagnostics Modules
      1. 12.7.1 Dual Clock Comparator (DCC)
        1. 12.7.1.1 DCC Overview
          1. 12.7.1.1.1 DCC Features
          2. 12.7.1.1.2 DCC Not Supported Features
        2. 12.7.1.2 DCC Integration
          1. 12.7.1.2.1 DCC Integration in MCU Domain
          2. 12.7.1.2.2 DCC Integration in MAIN Domain
        3. 12.7.1.3 DCC Functional Description
          1. 12.7.1.3.1 DCC Counter Operation
          2. 12.7.1.3.2 DCC Low Power Mode Operation
          3. 12.7.1.3.3 DCC Suspend Mode Behavior
          4. 12.7.1.3.4 DCC Single-Shot Mode
          5. 12.7.1.3.5 DCC Continuous mode
            1. 12.7.1.3.5.1 DCC Continue on Error
            2. 12.7.1.3.5.2 DCC Error Count
          6. 12.7.1.3.6 DCC Control and count hand-off across clock domains
          7. 12.7.1.3.7 DCC Error Trajectory record
            1. 12.7.1.3.7.1 DCC FIFO capturing for Errors
            2. 12.7.1.3.7.2 DCC FIFO in continuous capture mode
            3. 12.7.1.3.7.3 DCC FIFO Details
            4. 12.7.1.3.7.4 DCC FIFO Debug mode behavior
          8. 12.7.1.3.8 DCC Count read registers
        4. 12.7.1.4 DCC Registers
      2. 12.7.2 Error Signaling Module (ESM)
        1. 12.7.2.1 ESM Overview
          1. 12.7.2.1.1 ESM Features
        2. 12.7.2.2 ESM Environment
        3. 12.7.2.3 ESM Integration
          1. 12.7.2.3.1 ESM Integration in WKUP Domain
          2. 12.7.2.3.2 ESM Integration in MCU Domain
          3. 12.7.2.3.3 ESM Integration in MAIN Domain
        4. 12.7.2.4 ESM Functional Description
          1. 12.7.2.4.1 ESM Interrupt Requests
            1. 12.7.2.4.1.1 ESM Configuration Error Interrupt
            2. 12.7.2.4.1.2 ESM Low Priority Error Interrupt
              1. 12.7.2.4.1.2.1 ESM Low Priority Error Level Event
              2. 12.7.2.4.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.7.2.4.1.3 ESM High Priority Error Interrupt
              1. 12.7.2.4.1.3.1 ESM High Priority Error Level Event
              2. 12.7.2.4.1.3.2 ESM High Priority Error Pulse Event
          2. 12.7.2.4.2 ESM Error Event Inputs
          3. 12.7.2.4.3 ESM Error Pin Output
          4. 12.7.2.4.4 ESM Minimum Time Interval
          5. 12.7.2.4.5 ESM Protection for Registers
          6. 12.7.2.4.6 ESM Clock Stop
        5. 12.7.2.5 ESM Registers
      3. 12.7.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.7.3.1 MCRC Overview
          1. 12.7.3.1.1 MCRC Features
          2. 12.7.3.1.2 MCRC Not Supported Features
        2. 12.7.3.2 MCRC Integration
        3. 12.7.3.3 MCRC Functional Description
          1. 12.7.3.3.1  MCRC Block Diagram
          2. 12.7.3.3.2  MCRC General Operation
          3. 12.7.3.3.3  MCRC Modes of Operation
            1. 12.7.3.3.3.1 AUTO Mode
            2. 12.7.3.3.3.2 Semi-CPU Mode
            3. 12.7.3.3.3.3 Full-CPU Mode
          4. 12.7.3.3.4  PSA Signature Register
          5. 12.7.3.3.5  PSA Sector Signature Register
          6. 12.7.3.3.6  CRC Value Register
          7. 12.7.3.3.7  Raw Data Register
          8. 12.7.3.3.8  Example DMA Controller Setup
            1. 12.7.3.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.7.3.3.8.2 AUTO Mode Using Software Trigger
            3. 12.7.3.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.7.3.3.9  Pattern Count Register
          10. 12.7.3.3.10 Sector Count Register/Current Sector Register
          11. 12.7.3.3.11 Interrupts
            1. 12.7.3.3.11.1 Compression Complete Interrupt
            2. 12.7.3.3.11.2 CRC Fail Interrupt
            3. 12.7.3.3.11.3 Overrun Interrupt
            4. 12.7.3.3.11.4 Underrun Interrupt
            5. 12.7.3.3.11.5 Timeout Interrupt
            6. 12.7.3.3.11.6 Interrupt Offset Register
            7. 12.7.3.3.11.7 Error Handling
          12. 12.7.3.3.12 Power Down Mode
          13. 12.7.3.3.13 Emulation
        4. 12.7.3.4 MCRC Programming Examples
          1. 12.7.3.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.7.3.4.1.1 DMA Setup
            2. 12.7.3.4.1.2 Timer Setup
            3. 12.7.3.4.1.3 CRC Setup
          2. 12.7.3.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.7.3.4.2.1 DMA Setup
            2. 12.7.3.4.2.2 CRC Setup
          3. 12.7.3.4.3 Example: Semi-CPU Mode
            1. 12.7.3.4.3.1 DMA Setup
            2. 12.7.3.4.3.2 Timer Setup
            3. 12.7.3.4.3.3 CRC Setup
          4. 12.7.3.4.4 Example: Full-CPU Mode
            1. 12.7.3.4.4.1 CRC Setup
        5. 12.7.3.5 MCRC Registers
      4. 12.7.4 ECC Aggregator
        1. 12.7.4.1 ECC Aggregator Overview
          1. 12.7.4.1.1 ECC Aggregator Features
        2. 12.7.4.2 ECC Aggregator Integration
        3. 12.7.4.3 ECC Aggregator Functional Description
          1. 12.7.4.3.1 ECC Aggregator Block Diagram
          2. 12.7.4.3.2 ECC Aggregator Register Groups
          3. 12.7.4.3.3 Read Access to the ECC Control and Status Registers
          4. 12.7.4.3.4 Serial Write Operation
          5. 12.7.4.3.5 Interrupts
          6. 12.7.4.3.6 Inject Only Mode
        4. 12.7.4.4 ECC Aggregator Registers
  15. 13On-Chip Debug
  16. 14Revision History
12.3.6.6.4 MMCSD0 Host Controller Registers

Table 12-4468 lists the memory-mapped registers for the MMCSD0 Host Controller. All register offset addresses not listed in Table 12-4468 should be considered as reserved locations and the register contents should not be modified.

Note:

UHSII is not supported. For more information, see Not Supported Features.

Table 12-4467 MMCSD0 HOST CONTROLLER Instances
Instance Base Address
MMCSD0_CTL_CFG 04F8 0000h
Table 12-4468 MMCSD0 Host Controller Registers
Offset Acronym Register Name MMCSD0_CTL_CFG
Physical Address
Host Controller Interface Register
0h MMCSD0_SDMA_SYS_ADDR_LO 32-bit Block Count/SDMA System Address Low Register 04F8 0000h
2h MMCSD0_SDMA_SYS_ADDR_HI 32-bit Block Count/SDMA System Address High Register 04F8 0002h
4h MMCSD0_BLOCK_SIZE 16-bit Block Size Register 04F8 0004h
6h MMCSD0_BLOCK_COUNT 16-bit Block Count Register 04F8 0006h
8h MMCSD0_ARGUMENT1_LO Argument1 Low Register 04F8 0008h
Ah MMCSD0_ARGUMENT1_HI Argument1 High Register 04F8 000Ah
Ch MMCSD0_TRANSFER_MODE Transfer Mode Register 04F8 000Ch
Eh MMCSD0_COMMAND Command Register 04F8 000Eh
10h to 1Eh MMCSD0_RESPONSE_0 to MMCSD0_RESPONSE_7 Response Register 04F8 0010h to
04F8 001Eh
20h MMCSD0_DATA_PORT Buffer Data Port Register 04F8 0020h
24h MMCSD0_PRESENTSTATE Present State Register 04F8 0024h
28h MMCSD0_HOST_CONTROL1 Host Control 1 Register 04F8 0028h
29h MMCSD0_POWER_CONTROL Power Control Register 04F8 0029h
2Ah MMCSD0_BLOCK_GAP_CONTROL Block Gap Control Register 04F8 002Ah
2Bh MMCSD0_WAKEUP_CONTROL Wakeup Control Register 04F8 002Bh
2Ch MMCSD0_CLOCK_CONTROL Clock Control Register 04F8 002Ch
2Eh MMCSD0_TIMEOUT_CONTROL Timeout Control Register 04F8 002Eh
2Fh MMCSD0_SOFTWARE_RESET Software Reset Register 04F8 002Fh
30h MMCSD0_NORMAL_INTR_STS Normal Interrupt Status Register 04F8 0030h
32h MMCSD0_ERROR_INTR_STS Error Interrupt Status Register 04F8 0032h
34h MMCSD0_NORMAL_INTR_STS_ENA Normal Interrupt Status Enable Register 04F8 0034h
36h MMCSD0_ERROR_INTR_STS_ENA Error Interrupt Status Enable Register 04F8 0036h
38h MMCSD0_NORMAL_INTR_SIG_ENA Normal Interrupt Signal Enable Register 04F8 0038h
3Ah MMCSD0_ERROR_INTR_SIG_ENA Error Interrupt Signal Enable Register 04F8 003Ah
3Ch MMCSD0_AUTOCMD_ERR_STS Auto CMD Error Status Register 04F8 003Ch
3Eh MMCSD0_HOST_CONTROL2 Host Control 2 Register 04F8 003Eh
40h MMCSD0_CAPABILITIES Capabilities Register 04F8 0040h
48h MMCSD0_MAX_CURRENT_CAP Maximum Current Capabilities Register 04F8 0048h
50h MMCSD0_FORCE_EVNT_ACMD_ERR_STS Force Event Register for Auto CMD Error Status 04F8 0050h
52h MMCSD0_FORCE_EVNT_ERR_INT_STS Force Event Register for Error Interrupt Status 04F8 0052h
54h MMCSD0_ADMA_ERR_STATUS ADMA Error Status Register 04F8 0054h
58h MMCSD0_ADMA_SYS_ADDRESS ADMA System Address Register 04F8 0058h
60h MMCSD0_PRESET_VALUE0 Preset Values 0 Register 04F8 0060h
62h MMCSD0_PRESET_VALUE1 Preset Values 1 Register 04F8 0062h
64h MMCSD0_PRESET_VALUE2 Preset Values 2 Register 04F8 0064h
66h MMCSD0_PRESET_VALUE3 Preset Values 3 Register 04F8 0066h
68h MMCSD0_PRESET_VALUE4 Preset Values 4 Register 04F8 0068h
6Ah MMCSD0_PRESET_VALUE5 Preset Values 5 Register 04F8 006Ah
6Ch MMCSD0_PRESET_VALUE6 Preset Values 6 Register 04F8 006Ch
6Eh MMCSD0_PRESET_VALUE7 Preset Values 7 Register 04F8 006Eh
72h MMCSD0_PRESET_VALUE8 Preset Values 8 Register 04F8 0072h
74h MMCSD0_PRESET_VALUE10 Preset Values 10 Register 04F8 0074h
78h MMCSD0_ADMA3_DESC_ADDRESS ADMA3 Integrated Descriptor Address Register 04F8 0078h
UHS-II Registers (1)
80h MMCSD0_UHS2_BLOCK_SIZE UHS-II Block Size Register 04F8 0080h
84h MMCSD0_UHS2_BLOCK_COUNT UHS-II Block Count Register 04F8 0084h
88h to 9Bh MMCSD0_UHS2_COMMAND_PKT_0 to MMCSD0_UHS2_COMMAND_PKT_19 UHS-II Command Packet Register 04F8 0088h to
04F8 009Bh
9Ch MMCSD0_UHS2_XFER_MODE UHS-II Transfer Mode Register 04F8 009Ch
9Eh MMCSD0_UHS2_COMMAND UHS-II Command Register 04F8 009Eh
A0h to B3h MMCSD0_UHS2_RESPONSE_0 to MMCSD0_UHS2_RESPONSE_19 UHS-II Response Register 04F8 00A0h to
04F8 00B3h
B4h MMCSD0_UHS2_MESSAGE_SELECT UHS-II Message Select Register 04F8 00B4h
B8h MMCSD0_UHS2_MESSAGE UHS-II Message Register 04F8 00B8h
BCh MMCSD0_UHS2_DEVICE_INTR_STATUS UHS-II Device Interrupt Status Register 04F8 00BCh
BEh MMCSD0_UHS2_DEVICE_SELECT UHS-II Device Select Register 04F8 00BEh
BFh MMCSD0_UHS2_DEVICE_INT_CODE UHS-II Device Interrupt Code Register 04F8 00BFh
C0h MMCSD0_UHS2_SOFTWARE_RESET UHS-II Software Reset Register 04F8 00C0h
C2h MMCSD0_UHS2_TIMER_CONTROL UHS-II Timeout Control Register 04F8 00C2h
C4h MMCSD0_UHS2_ERR_INTR_STS UHS-II Error Interrupt Status Register 04F8 00C4h
C8h MMCSD0_UHS2_ERR_INTR_STS_ENA UHS-II Error Interrupt Status Enable Register 04F8 00C8h
CCh MMCSD0_UHS2_ERR_INTR_SIG_ENA UHS-II Error Interrupt Signal Enable Register 04F8 00CCh
E0h MMCSD0_UHS2_SETTINGS_PTR Pointer for UHS-II Settings Register 04F8 00E0h
E2h MMCSD0_UHS2_CAPABILITIES_PTR Pointer for UHS-II Host Capabilities Register 04F8 00E2h
E4h MMCSD0_UHS2_TEST_PTR Pointer for UHS-II Test Register 04F8 00E4h
E6h MMCSD0_SHARED_BUS_CTRL_PTR Pointer for Embedded Control Register 04F8 00E6h
E8h MMCSD0_VENDOR_SPECFIC_PTR Pointer for Vendor Specific Area Register 04F8 00E8h
F4h MMCSD0_BOOT_TIMEOUT_CONTROL Boot Timeout Control Register 04F8 00F4h
F8h MMCSD0_VENDOR_REGISTER Vendor Register 04F8 00F8h
FCh MMCSD0_SLOT_INT_STS Slot Interrupt Status Register 04F8 00FCh
FEh MMCSD0_HOST_CONTROLLER_VER Host Controller Version Register 04F8 00FEh
100h MMCSD0_UHS2_GEN_SETTINGS UHS-II General Settings Register 04F8 0100h
104h MMCSD0_UHS2_PHY_SETTINGS UHS-II PHY Settings Register 04F8 0104h
108h MMCSD0_UHS2_LNK_TRN_SETTINGS UHS-II LINK/TRAN Settings Register 04F8 0108h
110h MMCSD0_UHS2_GEN_CAP UHS-II General Capabilities Register 04F8 0110h
114h MMCSD0_UHS2_PHY_CAP UHS-II PHY Capabilities Register 04F8 0114h
118h MMCSD0_UHS2_LNK_TRN_CAP UHS-II LINK/TRAN Capabilities Register 04F8 0118h
120h MMCSD0_FORCE_UHSII_ERR_INT_STS Force Event for UHS-II Error Interrupt Status Register 04F8 0120h
Command Queue Registers
200h MMCSD0_CQ_VERSION Command Queueing Version Register 04F8 0200h
204h MMCSD0_CQ_CAPABILITIES Command Queueing Capabilities Register 04F8 0204h
208h MMCSD0_CQ_CONFIG Command Queueing Configuration Register 04F8 0208h
20Ch MMCSD0_CQ_CONTROL Command Queueing Control Register 04F8 020Ch
210h MMCSD0_CQ_INTR_STS Command Queueing Interrupt Status Register 04F8 0210h
214h MMCSD0_CQ_INTR_STS_ENA Command Queueing Interrupt Status Enabled Register 04F8 0214h
218h MMCSD0_CQ_INTR_SIG_ENA Command Queueing Interrupt Signal Enable Register 04F8 0218h
21Ch MMCSD0_CQ_INTR_COALESCING Interrupt Coalescing Register 04F8 021Ch
220h MMCSD0_CQ_TDL_BASE_ADDR Command Queueing Task Descriptor List Base Address Low Register 04F8 0220h
224h MMCSD0_CQ_TDL_BASE_ADDR_UPBITS Command Queueing Task Descriptor List Base Address High Register 04F8 0224h
228h MMCSD0_CQ_TASK_DOOR_BELL Command Queueing Task Doorbell Register 04F8 0228h
22Ch MMCSD0_CQ_TASK_COMP_NOTIF Command Queueing Task Doorbell Notification Register 04F8 022Ch
230h MMCSD0_CQ_DEV_QUEUE_STATUS Command Queueing Device Queue Status Register 04F8 0230h
234h MMCSD0_CQ_DEV_PENDING_TASKS Command Queueing Device Pending Tasks Register 04F8 0234h
238h MMCSD0_CQ_TASK_CLEAR Command Queueing Task Clear Register 04F8 0238h
240h MMCSD0_CQ_SEND_STS_CONFIG1 Send Status Timer Configuration 1 Register 04F8 0240h
244h MMCSD0_CQ_SEND_STS_CONFIG2 Send Status Configuration 2 Register 04F8 0244h
248h MMCSD0_CQ_DCMD_RESPONSE Command Response Register for Direct Command Task 04F8 0248h
250h MMCSD0_CQ_RESP_ERR_MASK Response Mode Error Mask Register 04F8 0250h
254h MMCSD0_CQ_TASK_ERR_INFO Task Error Information Register 04F8 0254h
258h MMCSD0_CQ_CMD_RESP_INDEX Command Response Index Register 04F8 0258h
25Ch MMCSD0_CQ_CMD_RESP_ARG Command Response Argument Register 04F8 025Ch
260h MMCSD0_CQ_ERROR_TASK_ID Command Queueing Error Task ID Register 04F8 0260h
(1) UHSII is not supported. For more information, see Not Supported Features.

6.6.4.1 MMCSD0_SDMA_SYS_ADDR_LO Register (Offset = 0h) [reset = 0h]

MMCSD0_SDMA_SYS_ADDR_LO is shown in Figure 12-2315 and described in Table 12-4470.

Return to Summary Table.

This register contains the Lower 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10.

Table 12-4469 MMCSD0_SDMA_SYS_ADDR_LO Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0000h
Figure 12-2315 MMCSD0_SDMA_SYS_ADDR_LO Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMA_ADDRESS
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4470 MMCSD0_SDMA_SYS_ADDR_LO Register Field Descriptions
Bit Field Type Reset Description
15-0 SDMA_ADDRESS R/W 0h

32-bit Block Count (SDMA System Address) Low

When the MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 0h, DMA uses this register as system address in only 32-bit addressing mode. Auto CMD23 cannot be used with SDMA.

When the MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 1h, SDMA uses the MMCSD0_ADMA_SYS_ADDRESS register instead of using this register to support both 32-bit and 64-bit addressing. This register is re-assigned to 32-bit Block Count and then SDMA may use Auto CMD23.

(1) SDMA System Address (MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 0h)

This register contains the system memory address for a SDMA transfer in 32-bit addressing mode. When the Host Controller (HC) stops a SDMA transfer, this register shall point to the system address of the next contiguous data position.

It can be accessed only if no transaction is executing (after a transaction has stopped). Reading this register during SDMA transfers may return an invalid value. The Host Driver (HD) shall initialize this register before starting a SDMA transaction. After SDMA has stopped, the next system address of the next contiguous data position can be read from this register. The SDMA transfer waits at the every boundary specified by the MMCSD0_BLOCK_SIZE[14-12] SDMA_BUF_SIZE bit field. The Host Controller generates DMA Interrupt to request the Host Driver to update this register. The Host Driver sets the next system address of the next data position to this register. When the most upper byte of this register (Offset = 3h) is written, the Host Controller restarts the SDMA transfer. When restarting SDMA by setting the MMCSD0_BLOCK_GAP_CONTROL[1] CONTINUE bit, the Host Controller shall start at the next contiguous address stored here in the SDMA System Address register (MMCSD0_SDMA_SYS_ADDR_LO/MMCSD0_SDMA_SYS_ADDR_HI). ADMA does not use this register.

(2) 32-bit Block Count (MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 1h)

Host Controller Version 4.10 re-defines this register as 32-bit Block Count . In version 4.00, this register may be used as 32-bit block count only for Auto CMD23 to set the argument of the CMD23 while executing Auto CMD23.

The Host Controller would decrement the block count of this register every block transfer and data transfer stops when the count reaches zero.

FFFF FFFFh (4G - 1 Block)

....

0000 0002h (2 Blocks)

0000 0001h (1 Block)

0000 0000h (Stop Count)

Note: This register should be accessed only when no transaction is executing. Reading this register during data transfers may return invalid value.

6.6.4.2 MMCSD0_SDMA_SYS_ADDR_HI Register (Offset = 2h) [reset = 0h]

MMCSD0_SDMA_SYS_ADDR_HI is shown in Figure 12-2316 and described in Table 12-4472.

Return to Summary Table.

This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10.

Table 12-4471 MMCSD0_SDMA_SYS_ADDR_HI Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0002h
Figure 12-2316 MMCSD0_SDMA_SYS_ADDR_HI Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDMA_ADDRESS
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4472 MMCSD0_SDMA_SYS_ADDR_HI Register Field Descriptions
Bit Field Type Reset Description
15-0 SDMA_ADDRESS R/W 0h

32-bit Block Count (SDMA System Address) High

This register contains the Upper 16-bit of physical system memory address used for DMA transfers or the second argument for the Auto CMD23 in Host version 3.0 and as 32-bit Block Count in Version 4.10.

6.6.4.3 MMCSD0_BLOCK_SIZE Register (Offset = 4h) [reset = 0h]

MMCSD0_BLOCK_SIZE is shown in Figure 12-2317 and described in Table 12-4474.

Return to Summary Table.

This register is used to configure the number of bytes in a data block.

Table 12-4473 MMCSD0_BLOCK_SIZE Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0004h
Figure 12-2317 MMCSD0_BLOCK_SIZE Register
15 14 13 12 11 10 9 8
RESERVED SDMA_BUF_SIZE XFER_BLK_SIZE
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
XFER_BLK_SIZE
R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4474 MMCSD0_BLOCK_SIZE Register Field Descriptions
Bit Field Type Reset Description
15 RESERVED R 0h

Reserved
14-12 SDMA_BUF_SIZE R/W 0h

Host SDMA Buffer Size

To perform long DMA transfer, System Address register (MMCSD0_SDMA_SYS_ADDR_LO/MMCSD0_SDMA_SYS_ADDR_HI) shall be updated at every system boundary during DMA transfer. These bits specify the size of contiguous buffer in the system memory. The DMA transfer shall wait at the every boundary specified by these fields and the Host Controller generates the DMA Interrupt to request the Host Driver to update the System Address register (MMCSD0_SDMA_SYS_ADDR_LO/MMCSD0_SDMA_SYS_ADDR_HI).

These bits shall support when the MMCSD0_CAPABILITIES[22] SDMA_SUPPORT bit is set to 1h and this function is active when the MMCSD0_TRANSFER_MODE[0] DMA_ENA bit is set to 1h.

0h: 4KB (Detects A11 Carry out)

1h: 8KB (Detects A12 Carry out)

2h: 16KB (Detects A13 Carry out)

3h: 32KB (Detects A14 Carry out)

4h: 64KB (Detects A15 Carry out)

5h: 128KB (Detects A16 Carry out)

6h: 256KB (Detects A17 Carry out)

7h: 512KB (Detects A18 Carry out)
11-0 XFER_BLK_SIZE R/W 0h

Transfer Block Size

This field specifies the block size for block data transfers for CMD17, CMD18, CMD24, CMD25 and CMD53. It can be accessed only if no transaction is executing (after a transaction has stopped). Read operations during transfer return an invalid value and write operations shall be ignored.

0000h: No Data Transfer

0001h: 1 Byte

0002h: 2 Bytes

0003h: 3 Bytes

0004h: 4 Bytes

....

01FFh: 511 Bytes

0200h: 512 Bytes

....

0800h: 2048 Bytes

6.6.4.4 MMCSD0_BLOCK_COUNT Register (Offset = 6h) [reset = 0h]

MMCSD0_BLOCK_COUNT is shown in Figure 12-2318 and described in Table 12-4476.

Return to Summary Table.

This register is used to configure the number of data blocks.

Table 12-4475 MMCSD0_BLOCK_COUNT Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0006h
Figure 12-2318 MMCSD0_BLOCK_COUNT Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFER_BLK_CNT
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4476 MMCSD0_BLOCK_COUNT Register Field Descriptions
Bit Field Type Reset Description
15-0 XFER_BLK_CNT R/W 0h

16-bit Block Count

Host Controller Version 4.10 extends block count to 32-bit .

Selection of either 16-bit Block Count register or 32-bit Block Count register is defined as follows:

(1) If the MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 0h or 16-bit Block Count register is set to non-zero, 16-bit Block Count register is selected.

(2) If the MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 1h and 16-bit Block Count register is set to zero, 32-bit Block Count register is selected.

Use of 16-bit/32-bit Block Count register is enabled when the MMCSD0_TRANSFER_MODE[1] BLK_CNT_ENA bit is set to 1h and is valid only for multiple block transfers.

The Host Driver shall set this register to a value between 1h and the maximum block count. The Host Controller decrements the block count after each block transfer and stops when the count reaches zero. Setting the block count to 0h results in no data blocks is transferred.

This register should be accessed only when no transaction is executing (after transactions are stopped).

During data transfer, read operations on this register may return an invalid value and write operations are ignored.

0000h: Stop Count

0001h: 1 Block

0002h: 2 Blocks

....

FFFFh: 65535 Blocks

6.6.4.5 MMCSD0_ARGUMENT1_LO Register (Offset = 8h) [reset = 0h]

MMCSD0_ARGUMENT1_LO is shown in Figure 12-2319 and described in Table 12-4478.

Return to Summary Table.

This register contains Lower bits of SD Command Argument.

Table 12-4477 MMCSD0_ARGUMENT1_LO Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0008h
Figure 12-2319 MMCSD0_ARGUMENT1_LO Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD_ARG1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4478 MMCSD0_ARGUMENT1_LO Register Field Descriptions
Bit Field Type Reset Description
15-0 CMD_ARG1 R/W 0h

Command Argument 1 Low

The SD Command Argument is specified as bit 23-8 of Command-Format.

6.6.4.6 MMCSD0_ARGUMENT1_HI Register (Offset = Ah) [reset = 0h]

MMCSD0_ARGUMENT1_HI is shown in Figure 12-2320 and described in Table 12-4480.

Return to Summary Table.

This register contains higher bits of SD Command Argument.

Table 12-4479 MMCSD0_ARGUMENT1_HI Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 000Ah
Figure 12-2320 MMCSD0_ARGUMENT1_HI Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD_ARG1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4480 MMCSD0_ARGUMENT1_HI Register Field Descriptions
Bit Field Type Reset Description
15-0 CMD_ARG1 R/W 0h

Command Argument 1 High

The SD Command Argument is specified as bit 39-24 of Command-Format.

6.6.4.7 MMCSD0_TRANSFER_MODE Register (Offset = Ch) [reset = 0h]

MMCSD0_TRANSFER_MODE is shown in Figure 12-2321 and described in Table 12-4482.

Return to Summary Table.

Table 12-4481 MMCSD0_TRANSFER_MODE Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 000Ch
Figure 12-2321 MMCSD0_TRANSFER_MODE Register
15 14 13 12 11 10 9 8
RESERVED RESP_INTR_DIS
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESP_ERR_CHK_ENA RESP_TYPE MULTI_BLK_SEL DATA_XFER_DIR AUTO_CMD_ENA BLK_CNT_ENA DMA_ENA
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4482 MMCSD0_TRANSFER_MODE Register Field Descriptions
Bit Field Type Reset Description
15-9 RESERVED R 0h

Reserved
8 RESP_INTR_DIS R/W 0h

Response Interrupt Disable

Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked. If Host Driver checks response error, sets this bit to 0h and waits Command Complete Interrupt (MMCSD0_NORMAL_INTR_STS[0] CMD_COMPLETE) and then checks the Response register (MMCSD0_RESPONSE_0 to MMCSD0_RESPONSE_7).

If Host Controller checks response error, sets this bit to 1h and sets the MMCSD0_TRANSFER_MODE[7] RESP_ERR_CHK_ENA bit to 1h. Command Complete Interrupt (MMCSD0_NORMAL_INTR_STS[0] CMD_COMPLETE) is disabled by this bit regardless of Command Complete Signal Enable (MMCSD0_NORMAL_INTR_SIG_ENA[0] CMD_COMPLETE).

0h: Response Interrupt is enabled

1h: Response Interrupt is disabled
7 RESP_ERR_CHK_ENA R/W 0h

Response Error Check Enable

Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.

If Host Driver checks response error, this bit is set to 0h and the MMCSD0_TRANSFER_MODE[8] RESP_INTR_DIS bit is set to 0h.

If Host Controller checks response error, sets this bit to 1h and sets the Response Interrupt Disable bit to 1h (MMCSD0_TRANSFER_MODE[8] RESP_INTR_DIS = 1h).

The MMCSD0_TRANSFER_MODE[6] RESP_TYPE bit selects either R1 or R5 response type. If an error is detected, Response Error Interrupt is generated in the MMCSD0_ERROR_INTR_STS register.

0h: Response Error Check is disabled

1h: Response Error Check is enabled
6 RESP_TYPE R/W 0h

Response Type R1/R5

When response error check is enabled (MMCSD0_TRANSFER_MODE[7] RESP_ERR_CHK_ENA = 1h), this bit selects either R1 or R5 response types. Two types of response checks are supported: R1 for memory and R5 for SDIO.

Error Statuses Checked in R1:

Bit31 OUT_OF_RANGE

Bit30 ADDRESS_ERROR

Bit29 BLOCK_LEN_ERROR

Bit26 WP_VIOLATION

Bit25 CARD_IS_LOCKED

Bit23 COM_CRC_ERROR

Bit21 CARD_ECC_FAILED

Bit20 CC_ERROR

Bit19 ERROR

Response Flags Checked in R5:

Bit07 COM_CRC_ERROR

Bit03 ERROR

Bit01 FUNCTION_NUMBER

Bit00 OUT_OF_RANGE

0h: R1 (Memory)

1h: R5 (SDIO)
5 MULTI_BLK_SEL R/W 0h

Multi/Single Block Select

This bit enables multiple block data transfers.

0h: Single Block

1h: Multiple Block
4 DATA_XFER_DIR R/W 0h

Data Transfer Direction Select

This bit defines the direction of data transfers.

0h: Write (Host to Card)

1h: Read (Card to Host)
3-2 AUTO_CMD_ENA R/W 0h

Auto CMD Enable

This field determines use of auto command functions.

There are three methods to stop Multiple-block read and write operation by CMD23 or CMD12. In the other operations (for example single read/write operation), this field is set to 0h.

(1) Auto CMD12 Enable:

Multiple-block read and write commands for memory require CMD12 to stop the operation. When this field is set to 1h, the Host Controller issues CMD12 automatically when last block transfer is completed. Auto CMD12 error is indicated to the MMCSD0_AUTOCMD_ERR_STS register. The Host Driver shall not set this bit if the command does not require CMD12.

When MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 0h, CMD12 is issued when 16-bit Block Count is expired.

When MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 1h, CMD12 is issued when 16-bit Block Count or 32-bit Block Count is expired.

(2) Auto CMD23 Enable:

When this bit field is set to 2h, the Host Controller issues a CMD23 automatically before issuing a command specified in the MMCSD0_COMMAND register. The Host Controller Version 3.00 and later shall support this function.

The following conditions are required to use the Auto CMD23:

Auto CMD23 Supported (Host Controller Version is 3.00 or later).

A memory card that supports CMD23 (SCR[33] = 1h).

If DMA is used, it shall be ADMA.

Only when CMD18 or CMD25 is issued. Auto CMD23 can be used with or without ADMA. By writing the MMCSD0_COMMAND register, the Host Controller issues a CMD23 first and then issues a command specified by the MMCSD0_COMMAND[13:8] CMD_INDEX bit field. If response errors of CMD23 are detected, the second command is not issued. A CMD23 error is indicated in the MMCSD0_AUTOCMD_ERR_STS register.

32-bit block count value for CMD23 is set to 32-bit Block Count (MMCSD0_SDMA_SYS_ADDR_LO/MMCSD0_SDMA_SYS_ADDR_HI) register.

(3) Auto CMD Auto Select (Version 4.10):

As CMD23 is optional for SD memory card except UHS 104 card, if card supports CMD23, Auto CMD 23 should be used instead of Auto CMD12. Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode. Selection of Auto CMD depends on setting of the MMCSD0_HOST_CONTROL2[11] CMD23_ENA bit which indicates whether card supports CMD23. If MMCSD0_HOST_CONTROL2[11] CMD23_ENA = 1h, Auto CMD23 is used and if MMCSD0_HOST_CONTROL2[11] CMD23_ENA = 0h, Auto CMD12 is used. In case of Version 4.10 or later, use of Auto CMD Auto Select is recommended rather than use of Auto CMD12 Enable or Auto CMD23 Enable.

0h: Auto Command Disabled

1h: Auto CMD12 Enable

2h: Auto CMD23 Enable

3h: Reserved
1 BLK_CNT_ENA R/W 0h

Block Count Enable

This bit is used to enable the MMCSD0_BLOCK_COUNT register, which is only relevant for multiple block transfers. When this bit is 0h, the MMCSD0_BLOCK_COUNT register is disabled, which is useful in executing an infinite transfer.

0h: Disable

1h: Enable
0 DMA_ENA R/W 0h

DMA Enable

DMA can be enabled only if the MMCSD0_CAPABILITIES[22] SDMA_SUPPORT bit is set. If this bit is set to 1h, a DMA operation shall begin when the HD writes to the upper byte of the MMCSD0_COMMAND register.

0h: Disable

1h: Enable

This register is used to control the operations of data transfers.

This register is used to control the operation of data transfers. The Host Driver shall set this register before issuing a command which transfers data (Refer to MMCSD0_COMMAND[5] DATA_PRESENT bit), or before issuing a Resume command. The Host Driver shall save the value of this register when the data transfer is suspended (as a result of a Suspend command) and restore it before issuing a Resume command. To prevent data loss, the Host Controller shall implement write protection for this register during data transactions. Writes to this register shall be ignored when the MMCSD0_PRESENTSTATE[1] INHIBIT_DAT bit is 1h.

Table 12-4483 shows the determination of transfer type.

Table 12-4483 Determination of Transfer Type
Multi/Single Block Select Block Count Enable Block Count Function
0 Don't Care Don't Care Single Transfer
1 0 Don't Care Infinite Transfer
1 1 Not Zero Multiple Transfer
1 1 Zero Stop Multiple Transfer

6.6.4.8 MMCSD0_COMMAND Register (Offset = Eh) [reset = 0h]

MMCSD0_COMMAND is shown in Figure 12-2322 and described in Table 12-4485.

Return to Summary Table.

This register is used to program the Command for host controller.

Table 12-4484 MMCSD0_COMMAND Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 000Eh
Figure 12-2322 MMCSD0_COMMAND Register
15 14 13 12 11 10 9 8
RESERVED CMD_INDEX
R-0h R/W-0h
7 6 5 4 3 2 1 0
CMD_TYPE DATA_PRESENT CMD_INDEX_CHK_ENA CMD_CRC_CHK_ENA SUB_CMD RESP_TYPE_SEL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4485 MMCSD0_COMMAND Register Field Descriptions
Bit Field Type Reset Description
15-14 RESERVED R 0h

Reserved
13-8 CMD_INDEX R/W 0h

Command Index

This bit shall be set to the command number (CMD0-63, ACMD0-63).
7-6 CMD_TYPE R/W 0h

Command Type

There are three types of special commands. Suspend, Resume and Abort. These bits shall be set to 0h for all other commands.

Suspend Command:

If the Suspend command succeeds, the HC shall assume the SD Bus has been released and that it is possible to issue the next command which uses the DAT line. The HC shall de-assert Read Wait for read transactions and stop checking busy for write transactions. The Interrupt cycle shall start, in 4-bit mode. If the Suspend command fails, the HC shall maintain its current state. and the HD shall restart the transfer by setting the MMCSD0_BLOCK_GAP_CONTROL[1] CONTINUE bit.

Resume Command:

The HD re-starts the data transfer by restoring the registers in the range of 04F8 0000h - 04F8 000Dh. The HC shall check for busy before starting write transfers.

Abort Command:

If this command is set when executing a read transfer, the HC shall stop reads to the buffer. If this command is set when executing a write transfer, the HC shall stop driving the DAT line. After issuing the Abort command, the HD should issue a software reset.

0h: Normal

1h: Suspend

2h: Resume

3h: Abort
5 DATA_PRESENT R/W 0h

Data Present Select

This bit is set to 1h to indicate that data is present and shall be transferred using the DAT line. If is set to 0h for the following:

1. Commands using only CMD line (for example CMD52).

2. Commands with no data transferbut using busy signal on DAT[0]line (R1b or R5b for example CMD38).

3. Resume Command.

0h: No Data Present

1h: Data Present
4 CMD_INDEX_CHK_ENA R/W 0h

Command Index Check Enable

If this bit is set to 1h, the HC shall check the index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error. If this bit is set to 0h, the Index field is not checked.

0h: Disable

1h: Enable
3 CMD_CRC_CHK_ENA R/W 0h

Command CRC Check Enable

If this bit is set to 1h, the HC shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. If this bit is set to 0h, the CRC field is not checked.

0h: Disable

1h: Enable
2 SUB_CMD R/W 0h

Sub Command Flag

This bit is added from Version 4.10 to distinguish a main command or sub command . When issuing a main command, this bit is set to 0h and when issuing a sub command, this bit is set to 1h. Setting of this bit is checked by the MMCSD0_PRESENTSTATE[28] SUB_COMMAND_STS bit.

Host Driver manages whether main or sub command. Host Controller does not refer to this bit to issue a command.

0h: Sub Command

1h: Main Command
1-0 RESP_TYPE_SEL R/W 0h

Response Type Select

0h: No Response

1h: Response length 136

2h: Response length 48

3h: Response length 48 check Busy after response

6.6.4.9 MMCSD0_RESPONSE_0 to MMCSD0_RESPONSE_7 Register (Offset = 10h to 1Eh) [reset = 0h]

MMCSD0_RESPONSE_0 to MMCSD0_RESPONSE_7 is shown in Figure 12-2323 and described in Table 12-4487.

Return to Summary Table.

This registers is used to store responses from SD Cards.

Table 12-4486 MMCSD0_RESPONSE_0 to MMCSD0_RESPONSE_7 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0010h to 04F8 001Eh
Figure 12-2323 MMCSD0_RESPONSE_0 to MMCSD0_RESPONSE_7 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD_RESP
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4487 Register Field Descriptions
Bit Field Type Reset Description
15-0 CMD_RESP R 0h

Command Response

R[] refers to a bit range within the response data as transmitted on the SD Bus, REP[] refers to a bit range within the Response register.

Table 12-4488 defines the relation between the parameter and name of response type.

Table 12-4488 Relation between Parameters and the Name of Response Type
Response Type Index Check Enable CRC Check Enable Name of Response Type
00 0 0 No Response
01 0 1 R2
10 0 0 R3, R4
10 1 1 R1, R6, R5, R7
11 1 1 R1b, R5b

The following table describes the mapping of command responses from the SD Bus to this register for each response type. In the table, R[] refers to a bit range within the response data as transmitted on the SD Bus, REP[] refers to a bit range within the Response register.

Table 12-4489 shows response bit definition for each response type.

Table 12-4489 Response Bit Definition for each Response Type
Kind of Response Meaning of Response Response Field Response Register
R1, R1b (normal response) Card Status R[39:8] REP[31:0]
R1b (Auto CMD12 response) Card Status for Auto CMD12 R[39:8] REP[127:96]
R1 (Auto CMD23 response) Card Status for Auto CMD23 R[39:8] REP [127:96]
R2 (CID, CSD Register) CID or CSD register include R[127:8] REP[119:0]
R3 (OCR Register) OCR Register for memory R[39:8] REP[31:0]
R4 (OCR Register) OCR Register for I/O etc. R[39:8] REP[31:0]
R5, R5b SDIO Response R[39:8] REP[31:0]
R6 (Published RCA response) New published RCA[31:16] etc. R[39:8] REP[31:0]

The Response Field indicates bit positions of "Responses" defined in the Physical Layer Specification. The table shows most responses with a length of 48 (R[47:0]) have 32 bits of the response data (R[39:8]) stored in the Response register at REP[31:0]. Responses of type R1b (Auto CMD12 responses) and R1 (Auto CMD23 response) have response data bits R[39:8] stored in the Response register at REP[127:96]. Responses with length 136 (R[135:0]) have 120 bits of the response data (R[127:8]) stored in the Response register at REP[119:0].

To read the response status efficiently, the Host Controller only stores part of the response data in the Response register. This enables the Host Driver to read 32 bits of response data efficiently in one read cycle on a 32-bit bus system. Parts of the response, the Index field and the CRC, are checked by the Host Controller (as specified by the MMCSD0_COMMAND[4] CMD_INDEX_CHK_ENA and MMCSD0_COMMAND[3] CMD_CRC_CHK_ENA bits) and generate an error interrupt if an error is detected. The bit range for the CRC check depends on the response length. If the response length is 48, the Host Controller shall check R[47:1], and if the response length is 136 the Host Controller shall check R[119:1].

Since the Host Controller may have a multiple block data DAT line transfer executing concurrently with a CMD_wo_DAT command, the Host Controller stores the Auto CMD12 response in the upper bits (REP[127:96]) of the Response register. The CMD_wo_DAT response is stored in REP[31:0]. This allows the Host Controller to avoid overwriting the Auto CMD12 response with the CMD_wo_DAT and vice versa.

While executing Auto CMD23, the response of CMD23 is saved to REP [127:96] and the response of multiple-block read and write command is save to REP [31:0]. The response error of CMD23 is indicated in the MMCSD0_AUTOCMD_ERR_STS register. When the Host Controller modifies part of the Response register, as shown in the table, it shall preserve the unmodified bits.

6.6.4.10 MMCSD0_DATA_PORT Register (Offset = 20h) [reset = 0h]

MMCSD0_DATA_PORT is shown in Figure 12-2324 and described in Table 12-4491.

Return to Summary Table.

This register is used to access internal buffer.

Table 12-4490 MMCSD0_DATA_PORT Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0020h
Figure 12-2324 MMCSD0_DATA_PORT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BUF_RD_DATA
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4491 MMCSD0_DATA_PORT Register Field Descriptions
Bit Field Type Reset Description
31-0 BUF_RD_DATA R/W 0h

Buffer Data

The Host Controller Buffer can be accessed through this 32-bit Data Port Register.

6.6.4.11 MMCSD0_PRESENTSTATE Register (Offset = 24h) [reset = 1F00000h]

MMCSD0_PRESENTSTATE is shown in Figure 12-2325 and described in Table 12-4493.

Return to Summary Table.

The Host Driver can get status of the Host Controller from this 32-bit read-only register.

Table 12-4492 MMCSD0_PRESENTSTATE Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0024h
Figure 12-2325 MMCSD0_PRESENTSTATE Register
31 30 29 28 27 26 25 24
UHS2_IF_DETECTION UHS2_IF_LANE_SYNC UHS2_DORMANT SUB_COMMAND_STS CMD_NOT_ISS_BY_ERR RESERVED SDIF_CMDIN
R-0h R-0h R-0h R-0h R-0h R-0h R-1h
23 22 21 20 19 18 17 16
SDIF_DAT3IN SDIF_DAT2IN SDIF_DAT1IN SDIF_DAT0IN WRITE_PROTECT CARD_DETECT CARD_STATE_STABLE CARD_INSERTED
R-1h R-1h R-1h R-1h R-0h R-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED BUF_RD_ENA BUF_WR_ENA RD_XFER_ACTIVE WR_XFER_ACTIVE
R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
SDIF_DAT7IN SDIF_DAT6IN SDIF_DAT5IN SDIF_DAT4IN RETUNING_REQ DATA_LINE_ACTIVE INHIBIT_DAT INHIBIT_CMD
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4493 MMCSD0_PRESENTSTATE Register Field Descriptions
Bit Field Type Reset Description
31 UHS2_IF_DETECTION R 0h

UHS-II IF Detection (UHS-II Only)

This status indicates whether a card supports UHS-II IF. This status is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register (MMCSD0_HOST_CONTROL2[8] UHS2_INTF_ENABLE = 1h). UHS-II interface initialization is activated by setting the MMCSD0_CLOCK_CONTROL[2] SD_CLK_ENA bit. Host Controller drives STB.L on D0 lane from EIDL state and waits for receiving STB.L on D1 lane. This bit is set to 1h if STB.L is detected on D1 lane. Host Controller shall compensate latency from setting SD Clock Enable to output STB.L on D0 lane when reading this status . This bit may be read any time after setting SD Clock Enable for faster UHS-II IF detection but Host Driver shall check this status at least 200µs period from setting SD Clock Enable (MMCSD0_CLOCK_CONTROL[2] SD_CLK_ENA) until detecting UHS-II IF.

After UHS-II IF is detected, this bit is cleared by when EIDL is detected on D0 lane, UHS-II Interface Enable is set to 0h (MMCSD0_HOST_CONTROL2[8] UHS2_INTF_ENABLE = 0h) or Host full reset is executed.

1h: UHS-II IF is detected

0h: UHS-II IF is not detected
30 UHS2_IF_LANE_SYNC R 0h

Lane Synchronization (UHS-II Only)

This status indicates whether lane is synchronized in UHS-II mode. This status is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register (MMCSD0_HOST_CONTROL2[8] UHS2_INTF_ENABLE = 1h). On detecting UHS-II Interface (D31 = 1h), Host Controller provides SYN LSS on D0 lane and waits for receiving SYN LSS on D1 lane. If SYN LSS is detected on D1 lane, Host Controller provides LIDL LSS on D0 lane and waits for receiving LIDL LSS on D1 lane.

In case of Version 4.00, this bit indicates completion of Device PHY Initialization by detecting LIDL LSS on D1 lane.

From Version 4.10, Host Controller may implement a specific PHY verification method and PHY Initialization Failure can be indicated by keeping this bit to 0h even LIDL LSS is detected on D1 lane. Host Driver detects PHY Initialization Failure by timeout.

This bit is cleared by when D0 lane is set to EIDL, UHS-II Interface Enable is set to 0h (MMCSD0_HOST_CONTROL2[8] UHS2_INTF_ENABLE = 0h) or executes Host full reset.

1h: UHS-II PHY is initialized

0h: UHS-II PHY is not initialized
29 UHS2_DORMANT R 0h

In Dormant State (UHS-II Only)

This status indicates whether UHS-II lanes enter Dormant state. This function is enabled by setting UHS-II Interface Enable to 1h in the Host Control 2 register (MMCSD0_HOST_CONTROL2[8] UHS2_INTF_ENABLE = 1h). On issuing GO_DORMAT_STATE command, "Go Dormant Command (7h)" is set to Command type in the UHS-II Command register (MMCSD0_UHS2_COMMAND[7:6] CMD_TYPE). This command type acts as a trigger to enter lanes into dormant state. Host Controller provides STB.H and EIDL on D0 lane and waits for receiving STB.H and EIDL on D1 lane. This bit is set to 1h after the time of T_DMT_ENTRY (750 RCLK cycle) or more from detecting EIDL on D1 lane.

RCLK may be stopped in dormant state, by setting SD Clock Enable to 0h in the Clock Control register (MMCSD0_CLOCK_CONTROL[2] SD_CLK_ENA = 0h) while In Dormant State bit is set to 1h. On writing Clock Control register with setting SD Clock Enable to 1h (MMCSD0_CLOCK_CONTROL[2] SD_CLK_ENA = 1h), Host Controller wakes lanes to exit Dormant State and In Dormant State is set to 0h.

In case of the card enters Hibernate Mode (RCLK is stopped), Host Driver may turn off VDD1 by clearing SD Bus Power for VDD1 bit in the MMCSD0_POWER_CONTROL register. Host Controller shall turn off VDD1 after stopping RCLK. This bit is cleared by when Host Controller drives STB.L on D0 lane, UHS-II Interface Enable is set to 0h (MMCSD0_HOST_CONTROL2[8] UHS2_INTF_ENABLE = 0h) or executes Host full reset.

1h: In DORMANT state

0h: Not in DORMANT state
28 SUB_COMMAND_STS R 0h

Sub Command Status

The MMCSD0_COMMAND register and Response register (MMCSD0_RESPONSE_0 to MMCSD0_RESPONSE_7) are commonly used for main command and sub command. This status is used to distinguish which response error statuses, main command or sub command, indicated in the MMCSD0_ERROR_INTR_STS register or in the MMCSD0_UHS2_ERR_INTR_STS register. Just before reading of this register, the MMCSD0_COMMAND[2] SUB_CMD bit or the MMCSD0_UHS2_COMMAND register is copied to this status. This status is effective not only when Response Error interrupt is generated but also when data error interrupt is generated with Command Not Issued by Error (D27 of this register) or Auto CMD Error interrupt is generated with Command Not Issued by Error by Auto CMD12 in the MMCSD0_AUTOCMD_ERR_STS register.

1h: Sub Command Status

0h: Main Command Status
27 CMD_NOT_ISS_BY_ERR R 0h

Command Not Issued by Error

Setting of this status indicates that a command cannot be issued due to an error except Auto CMD12 error (equivalent error status by Auto CMD12 error is defined as Command Not Issued By Auto CMD12 Error in the MMCSD0_AUTOCMD_ERR_STS register). This status is set to 1h when Host Controller cannot issue a command after setting MMCSD0_COMMAND register or MMCSD0_UHS2_COMMAND register. Sub Command Status (D28) indicates which command is not issued (main or sub).

1h: Command cannot be issued

0h: No error for issuing a command
26-25 RESERVED R 0h

Reserved
24 SDIF_CMDIN R 1h

CMD Line Signal Level (SD Mode Only)

This status is used to check CMD line level to recover from errors, and for debugging.
23 SDIF_DAT3IN R 1h

DAT[3] Line Signal Level (SD Mode Only)

This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[3].

D23 - DAT[3]
22 SDIF_DAT2IN R 1h

DAT[2] Line Signal Level (SD Mode Only)

This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[2].

D22 - DAT[2]
21 SDIF_DAT1IN R 1h

DAT[1] Line Signal Level (SD Mode Only)

This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[1].

D21 - DAT[1]
20 SDIF_DAT0IN R 1h

DAT[0] Line Signal Level (SD Mode Only)

This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0].

D20 - DAT[0]
19 WRITE_PROTECT R 0h

Write Protect Switch Pin Level

The Write Protect Switch is supported for memory and combo cards.This bit reflects the SDWP# pin.

0h: Write protected (SDWP# = 1)

1h: Write enabled (SDWP# = 0)
18 CARD_DETECT R 0h

Card Detect Pin Level

This bit reflects the inverse value of the SDCD# pin.

0h: No Card present (SDCD# = 1)

1h: Card present (SDCD# = 0)
17 CARD_STATE_STABLE R 0h

Card State Stable

This bit is used for testing. If it is 0h, the Card Detect Pin Level is not stable. If this bit is set to 1h, it means the Card Detect Pin Level is stable. The MMCSD0_SOFTWARE_RESET[0] SWRST_FOR_ALL bit shall not affect this bit.

0h: Reset of Debouncing

1h: No Card or Inserted
16 CARD_INSERTED R 0h

Card Inserted

This bit indicates whether a card has been inserted. Changing from 0h to 1h generates a Card Insertion interrupt in the MMCSD0_NORMAL_INTR_STS register and changing from 1h to h0 generates a Card Removal Interrupt in the MMCSD0_NORMAL_INTR_STS register. The MMCSD0_SOFTWARE_RESET[0] SWRST_FOR_ALL bit shall not affect this bit.

If a Card is removed while its power is on and its clock is oscillating, the HC shall clear the MMCSD0_POWER_CONTROL[0] SD_BUS_POWER bit and the MMCSD0_CLOCK_CONTROL[2] SD_CLK_ENA bit. In addition the HD should clear the HC by the MMCSD0_SOFTWARE_RESET[0] SWRST_FOR_ALL bit. The card detect is active regardless of the SD Bus Power.

0h: Reset or Debouncing or No Card

1h: Card Inserted
15-12 RESERVED R 0h

Reserved
11 BUF_RD_ENA R 0h

Buffer Read Enable

This status is used for non-DMA read transfers. This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1h, readable data exists in the buffer. A change of this bit from 1h to 0h occurs when all the block data is read from the buffer. A change of this bit from 0h to 1h occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt.

0h: Read Disable

1h: Read Enable
10 BUF_WR_ENA R 0h

Buffer Write Enable

This status is used for non-DMA write transfers. This read only flag indicates if space is available for write data. If this bit is 1h, data can be written to the buffer. A change of this bit from 1h to 0h occurs when all the block data is written to the buffer. A change of this bit from 0h to 1h occurs when top of block data can be written to the buffer and generates the Buffer Write Ready Interrupt.

0h: Write Disable

1h: Write Enable
9 RD_XFER_ACTIVE R 0h

Read Transfer Active (SD Mode Only)

This status is used for detecting completion of a read transfer.

This bit is set to 1h for either of the following conditions:

After the end bit of the read command.

When writing a 1h to continue Request in the MMCSD0_BLOCK_GAP_CONTROL register to restart a read transfer.

This bit is cleared to 0h for either of the following conditions:

When the last data block as specified by block length is transferred to the system.

When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request set to 1h (MMCSD0_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP = 1h). A transfer complete interrupt is generated when this bit changes to 0h.

1h: Transferring data

0h: No valid data
8 WR_XFER_ACTIVE R 0h

Write Transfer Active (SD Mode Only)

This status indicates a write transfer is active. If this bit is 0h, it means no valid write data exists in the HC. This bit is set in either of the following cases:

After the end bit of the write command.

When writing a 1h to the MMCSD0_BLOCK_GAP_CONTROL[1] CONTINUE bit to restart a write transfer.

This bit is cleared in either of the following cases:

After getting the CRC status of the last data block as specified by the transfer count (Single or Multiple).

After getting a CRC status of any block where data transmission is about to be stopped by a Stop At Block Gap Request. During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0h, as a result of the Stop At Block Gap Request being set. This status is useful for the HD in determining when to issue commands during write busy.

1h: Transferring data

0h: No valid data
7 SDIF_DAT7IN R 0h

DAT[7] Line Signal Level (Embedded Only)

This status is used to check DAT line level to recover from errors, and for debugging.

D07 - DAT[7]
6 SDIF_DAT6IN R 0h

DAT[6] Line Signal Level (Embedded Only)

This status is used to check DAT line level to recover from errors, and for debugging.

D06 - DAT[6]
5 SDIF_DAT5IN R 0h

DAT[5] Line Signal Level (Embedded Only)

This status is used to check DAT line level to recover from errors, and for debugging.

D05 - DAT[5]
4 SDIF_DAT4IN R 0h

DAT[4] Line Signal Level (Embedded Only)

This status is used to check DAT line level to recover from errors, and for debugging.

D04 - DAT[4]
3 RETUNING_REQ R 0h

Re-Tuning Request (UHS-I Only)

Host Controller may request Host Driver to execute re-tuning sequence by setting this bit when the data window is shifted by temperature drift and a tuned sampling point does not have a good margin to receive correct data.

This bit is cleared when a command is issued with setting the MMCSD0_HOST_CONTROL2[6] EXECUTE_TUNING bit.

Changing of this bit from 0h to 1h generates Re-Tuning Event.

This bit isn't set to 1h if the MMCSD0_HOST_CONTROL2[7] SAMPLING_CLK_SELECT bit is set to 0h (using fixed sampling clock).

1h: Sampling clock needs re-tuning

0h: Fixed or well tuned sampling clock
2 DATA_LINE_ACTIVE R 0h

DAT Line Active (SD Mode Only)

This bit indicates whether one of the DAT line on SD bus is in use.

1h: DAT line active

0h: DAT line inactive
1 INHIBIT_DAT R 0h

Command Inhibit (DAT) (SD Mode Only)

This status bit is generated if either the DAT Line Active or the Read transfer Active is set to 1h. If this bit is 0h, it indicates the HC can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (for example R1b, R5b type). Changing from 1h to 0h generates a Transfer Complete interrupt in the MMCSD0_NORMAL_INTR_STS register.

Note: The SD Host Driver can save registers in the range of 04F8 0000h - 04F8 000Dh for a suspend transaction after this bit has changed from 1h to 0h.

1h: Cannot issue command which uses the DAT line

0h: Can issue command which uses the DAT line
0 INHIBIT_CMD R 0h

Command Inhibit (CMD)

SD Mode:

If this bit is 0h, it indicates the CMD line is not in use and the HC can issue a SD command using the CMD line. This bit is set immediately after the MMCSD0_COMMAND register is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1h.

Commands using only the CMD line can be issued if this bit is 0h. Changing from 1h to 0h generates a Command complete interrupt in the MMCSD0_NORMAL_INTR_STS register. If the HC cannot issuethe command because of a command conflict error or because of Command Not Issued By Auto CMD12 Error, this bit shall remain 1h and the Command Complete is not set. Status issuing Auto CMD12 is not read from this bit. Auto CMD12 and Auto CMD23 consist of two responses. In this case, this bit is not cleared by the response of CMD12 or CMD23 but cleared by the response of a read/write command. Status issuing Auto CMD12 is not read from this bit. So if a command is issued during Auto CMD12 operation, Host Controller shall manage to issue two commands: CMD12 and a command set by the MMCSD0_COMMAND register.

UHS-II Mode:

This bit is 0h means that a command packet can be issued by the Host Controller. While this bit is set to 1h, which means the Host Controller is not ready to issue a next command, Host Driver shall not write the registers from the MMCSD0_UHS2_BLOCK_SIZE to the MMCSD0_UHS2_COMMAND. Changing from 1h to 0h generates a Command Complete Interrupt in the MMCSD0_NORMAL_INTR_STS register.

1h: Host Controller is not ready to issue a command

0h: Host Controller is ready to issue a command

Version 4.10 adds a new control to prevent error statuses from overwriting by receipt of a next command. This status keeps indicating 1h while any of response error statuses is set to 1h , Command Not Issued by Error in this register is set to 1h or the MMCSD0_AUTOCMD_ERR_STS[7] CMD_NOT_ISSUED bit is set to 1h. Software Reset For CMD Lineis used to clear the error statuses above and this status (MMCSD0_SOFTWARE_RESET[1] SWRST_FOR_CMD).

Note: DAT line active indicates whether one of the DAT line is on SD bus is in use.

(a) In the case of read transactions

This status indicates whether a read transfer is executing on the SD Bus. Changing this value from 1h to 0h generates a Block Gap Event interrupt in the MMCSD0_NORMAL_INTR_STS register, as the result of the Stop At Block Gap Request being set.

This bit shall be set in either of the following cases:

(1) After the end bit of the read command.

(2) When writing a 1h to the MMCSD0_BLOCK_GAP_CONTROL[1] CONTINUE bit to restart a read transfer.

This bit shall be cleared in either of the following cases:

(1) When the end bit of the last data block is sent from the SD Bus to the Host Controller. In case of ADMA2, the last block is designated by the last transfer of Descriptor Table.

(2) When a read transfer is stopped at the block gap initiated by a Stop At Block Gap Request (MMCSD0_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP).

The Host Controller shall stop read operation at the start of the interrupt cycle of the next block gap by driving Read Wait or stopping SD clock. If the Read Wait signal is already driven (due to data buffer cannot receive data), the Host Controller can continue to stop read operation by driving the Read Wait signal. It is necessary to support Read Wait in order to use suspend/resume function.

(b) In the case of write transactions

This status indicates that a write transfer is executing on the SD Bus. Changing this value from 1h to 0h generate a Transfer Complete interrupt in the MMCSD0_NORMAL_INTR_STS register.

This bit shall be set in either of the following cases:

(1) After the end bit of the write command.

(2) When writing to 1h to the MMCSD0_BLOCK_GAP_CONTROL[1] CONTINUE bit to continue a write transfer.

This bit shall be cleared in either of the following cases:

(1) When the SD card releases write busy of the last data block. If SD card does not drive busy signal for 8 SD Clocks, the Host Controller shall consider the card drive "Not Busy". In case of ADMA2, the last block is designated by the last transfer of Descriptor Table.

(2) When the SD card releases write busy prior to waiting for write transfer as a result of a Stop At Block Gap Request (MMCSD0_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP).

(c) Command with busy

This status indicates whether a command indicates busy (for example erase command for memory) is executing on the SD Bus. This bit is set after the end bit of the command with busy and cleared when busy is de-asserted. Changing this bit from 1h to 0h generate a Transfer Complete interrupt in the MMCSD0_NORMAL_INTR_STS register.

Note:

The HD can issue cmd0, cmd12, cmd13 (for memory) and cmd52 (for SDIO) when the DAT lines are busy during data transfer. These commands can be issued when Command Inhibit (CMD) is set to zero (MMCSD0_PRESENTSTATE[0] INHIBIT_CMD = 0h). Other commands shall be issued when Command Inhibit (DAT) is set to zero (MMCSD0_PRESENTSTATE[1] INHIBIT_DAT = 0h).

6.6.4.12 MMCSD0_HOST_CONTROL1 Register (Offset = 28h) [reset = 0h]

MMCSD0_HOST_CONTROL1 is shown in Figure 12-2326 and described in Table 12-4495.

Return to Summary Table.

This register is used to program DMA modes, LED control, data transfer width, High Speed enable, card detect test level and signal selection.

Table 12-4494 MMCSD0_HOST_CONTROL1 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0028h
Figure 12-2326 MMCSD0_HOST_CONTROL1 Register
7 6 5 4 3 2 1 0
CD_SIG_SEL CD_TEST_LEVEL EXT_DATA_WIDTH DMA_SELECT HIGH_SPEED_ENA DATA_WIDTH LED_CONTROL
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4495 MMCSD0_HOST_CONTROL1 Register Field Descriptions
Bit Field Type Reset Description
7 CD_SIG_SEL R/W 0h

Card Detect Signal Detection

This bit selects source for card detection.

1h: The card detect test level is selected

0h: SDCD# is selected (for normal use)
6 CD_TEST_LEVEL R/W 0h

Card Detect Test Level

This bit is enabled while the Card Detect Signal Selection is set to 1h and it indicates card inserted or not.

Generates (card ins or card removal) interrupt when the normal interrupt status enable bit is set.

1h: Card Inserted

0h: No Card
5 EXT_DATA_WIDTH R/W 0h

Extended Data Transfer Width (Embedded and SD Mode Only)

This bit controls 8-bit bus width mode for embedded device. Support of this function is indicated in 8-bit Support for Embedded Device in the MMCSD0_CAPABILITIES register. If a device supports 8-bit bus mode, this bit may be set to 1h. If this bit is 0h, bus width is controlled by the MMCSD0_HOST_CONTROL1[1] DATA_WIDTH bit.

This bit is not effective when multiple devices are installed on a bus slot (Slot Type is set to 2h in the MMCSD0_CAPABILITIES register). In this case, each device bus width is controlled by Bus Width Preset field in the Shared Bus register (MMCSD0_SHARED_BUS_CTRL_PTR).

1h: 8-bit Bus Width

0h: Bus Width is Selected by Data Transfer Width
4-3 DMA_SELECT R/W 0h

DMA Select

This field is used to select DMA type. The Host Driver shall check support of DMA modes by referring the MMCSD0_CAPABILITIES register. Selected DMA is enabled by the MMCSD0_TRANSFER_MODE[0] DMA_ENA bit in SD mode and the MMCSD0_UHS2_XFER_MODE[0] DMA_ENA bit in UHS-II mode.

(1) Up to Version 3.00:

When MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 0h, setting of this field is compatible to Host Controller Version 3.00.

SDMA is initiated by writing to the MMCSD0_COMMAND register when this field is set to 0h and the SDMA System Address register (32-bit) is used (MMCSD0_SDMA_SYS_ADDR_LO/MMCSD0_SDMA_SYS_ADDR_HI). SDMA does not support 64-bit addressing.

ADMA2 is initiated by writing to the MMCSD0_COMMAND register when this field is set to 2h or 3h. Lower 32-bit of the ADMA System Address register (MMCSD0_SDMA_SYS_ADDR_LO/MMCSD0_SDMA_SYS_ADDR_HI) is used when this field is set to 2h and 64-bit of the ADMA System Address register is used when this field is set to 3h. Support of 64-bit System Addressing is indicated by the MMCSD0_CAPABILITIES[28] ADDR_64BIT_SUPPORT_V3 bit. 64-bit AMDA2 uses 96-bit Descriptor.

0h: SDMA is selected

1h: 32-bit Address ADMA1 is selected

2h: 32-bit Address ADMA2 is selected

3h: 64-bit Address ADMA2 is selected (Optional)

(2) Version 4.00 or later:

When the MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 1h, setting of this field is changed as follows.

SDMA is initiated by Host Driver writes to the MMCSD0_COMMAND register when this field is set to 0h.

ADMA2 is initiated by Host Driver writes to the MMCSD0_COMMAND register when this field is set to 2h or 3h and by ADMA3 sets to the ADMA System Address register (MMCSD0_SDMA_SYS_ADDR_LO/MMCSD0_SDMA_SYS_ADDR_HI) when this field is set to 3h.

ADMA3 is initiated by Host Driver writes to the MMCSD0_ADMA3_DESC_ADDRESS register when this field is set to 3h.

0h: SDMA is selected

1h: Not Used (New assignment is not allowed)

2h: ADMA2 is selected (AMDA3 is not supported or disabled)

3h: ADMA2 or ADMA3 is selected

Support of 64-bit DMA and 128-bit Descriptor is indicated by the MMCSD0_CAPABILITIES[27] ADDR_64BIT_SUPPORT_V4 bit. If the support bit is set to 1h, all supported DMAs (depends on Support, ADMA2 Support and ADMA3 Support) shall support 64-bit addressing. The MMCSD0_HOST_CONTROL2[13] BIT64_ADDRESSING bit selects either 32-bit or 64-bit system addressing of DMAs.
2 HIGH_SPEED_ENA R/W 0h

High Speed Enable (SD Mode Only)

This bit is optional. Before setting this bit, the HD shall check the MMCSD0_CAPABILITIES[21] HIGH_SPEED_SUPPORT bit. If this bit is set to 0h (default), the HC outputs CMD line and DAT lines at the falling edge of the SD clock (up to 25 MHz/20 MHz for MMC). If this bit is set to 1h, the HC outputs CMD line and DAT lines at the rising edge of the SD clock (up to 50 MHz for SD/52 MHz for MMC)/208 MHz (for SD3.0).

If the MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA bit is set to 1h, Host Driver needs to reset SD Clock Enable (MMCSD0_CLOCK_CONTROL[2] SD_CLK_ENA) before changing this field to avoid generating clock glitches. After setting this field, the Host Driver sets SD Clock Enable again. This bit is not effective in UHS-II mode.

1h: High Speed Mode

0h: Normal Speed Mode
1 DATA_WIDTH R/W 0h

Data Transfer Width (SD Mode Only)

This bit selects the data width of the HC. The HD shall select it to match the data width of the SD card. This bit is not effective in UHS-II mode.

1h: 4 bit mode

0h: 1 bit mode
0 LED_CONTROL R/W 0h

LED Control

This bit is used to caution the user not to remove the card while the SD card is being accessed. If the software is going to issue multiple SD commands, this bit can be set during all transactions. It is not necessary to change for each transaction.

1h: LED on

0h: LED off

6.6.4.13 MMCSD0_POWER_CONTROL Register (Offset = 29h) [reset = 0h]

MMCSD0_POWER_CONTROL is shown in Figure 12-2327 and described in Table 12-4497.

Return to Summary Table.

This register is used to program the SD Bus power and voltage level.

Table 12-4496 MMCSD0_POWER_CONTROL Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0029h
Figure 12-2327 MMCSD0_POWER_CONTROL Register
7 6 5 4 3 2 1 0
UHS2_VOLTAGE UHS2_POWER SD_BUS_VOLTAGE SD_BUS_POWER
R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4497 MMCSD0_POWER_CONTROL Register Field Descriptions
Bit Field Type Reset Description
7-5 UHS2_VOLTAGE R/W 0h

SD Bus Voltage Select for VDD2 (UHS-II Only)

This field determines supply voltage range to VDD2. This field can be set to 5h if the MMCSD0_CAPABILITIES[60] VDD2_1P8_SUPPORT bit is set to 1h.

111b: Not used

110b: Not used

101b: 1.8 V

100b: Reserved for 1.2 V

011b – 001b: Reserved

000b: VDD2 Not Supported
4 UHS2_POWER R/W 0h

SD Bus Power for VDD2 (UHS-II Only)

Setting this bit enables providing VDD2.

1h: Power on

0h: Power off
3-1 SD_BUS_VOLTAGE R/W 0h

SD Bus Voltage Select for VDD1

By setting these bits, the HD selects the voltage level for the SD card. Before setting this register, the HD shall check the voltage support bits in the MMCSD0_CAPABILITIES register. If an unsupported voltage is selected, the Host System shall not supply SD bus voltage.

111b: 3.3 V (Flattop.)

110b: 3.0 V (Typ.)

101b: 1.8 V (Typ.) for Embedded

100b – 000b: Reserved
0 SD_BUS_POWER R/W 0h

SD Bus Power for VDD1

Before setting this bit, the SD host driver shall set SD Bus Voltage Select (MMCSD0_POWER_CONTROL[3-1] SD_BUS_VOLTAGE). If the HC detects the No Card State, this bit shall be cleared.

If this bit is cleared, the Host Controller should immediately stop driving CMD and DAT[3:0] (tri-state), and drive SDCLK to low level. If card is connected to Host Controller, Host Controller shall set these lines to low before stopping to supply VDD1.

In UHS-II mode, before clearing this bit, Host Driver shall clear the MMCSD0_CLOCK_CONTROL[2] SD_CLK_ENA bit and before stopping to supply VDD1, Host Controller shall set DAT[2] to low if DAT[2] is used as out-of band interrupt.

1h: Power on

0h: Power off

6.6.4.14 MMCSD0_BLOCK_GAP_CONTROL Register (Offset = 2Ah) [reset = 80h]

MMCSD0_BLOCK_GAP_CONTROL is shown in Figure 12-2328 and described in Table 12-4499.

Return to Summary Table.

This register is used to program the block gap request, read wait control and interrupt at block gap.

Table 12-4498 MMCSD0_BLOCK_GAP_CONTROL Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 002Ah
Figure 12-2328 MMCSD0_BLOCK_GAP_CONTROL Register
7 6 5 4 3 2 1 0
BOOT_ACK_ENA ALT_BOOT_MODE BOOT_ENABLE RESERVED INTRPT_AT_BLK_GAP RDWAIT_CTRL CONTINUE STOP_AT_BLK_GAP
R/W-1h R/W-0h R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4499 MMCSD0_BLOCK_GAP_CONTROL Register Field Descriptions
Bit Field Type Reset Description
7 BOOT_ACK_ENA R/W 1h

Boot Acknowledge Check

To check for the boot acknowledge in boot operation.

1h: Wait for boot ack from eMMC card

0h: Will not wait for boot ack from eMMC card
6 ALT_BOOT_MODE R/W 0h

Alternative Boot Mode

To start boot code access in alternative mode.

1h: To start alternate boot mode access

0h: To stop alternate boot mode access
5 BOOT_ENABLE R/W 0h

Boot Enable

To start boot code access.

1h: To start boot code access

0h: To stop boot code access
4 RESERVED R 0h

Reserved
3 INTRPT_AT_BLK_GAP R/W 0h

Interrupt At Block Gap (SD Mode Only)

This bit is valid only in 4-bit mode of the SDIO card and selects a sample point in the interrupt cycle. Setting to 1h enables interrupt detection at the block gap for a multiple block transfer. If the SD card cannot signal an interrupt during a multiple block transfer, this bit should be set to 0h. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card.
2 RDWAIT_CTRL R/W 0h

Read Wait Control (SD Mode Only)

The read wait function is optional for SDIO cards. If the card supports read wait, set this bit to enable use of the read wait protocol to stop read data using DAT[2] line. Otherwise the HC has to stop the SD clock to hold read data, which restricts commands generation. When the HD detects an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. If the card does not support read wait, this bit shall never be set to 1h otherwise DAT line conflict may occur. If this bit is set to 0h, Suspend/Resume cannot be supported.

In UHS-II mode, Read Wait is disabled and DAT[2] line is used for Interrupt Signal from UHS-II Card.

1h: Enable Read Wait Control

0h: Disable Read Wait Control
1 CONTINUE R/W 0h

Continue Request

This bit is used to restart a transaction which was stopped using the Stop At Block Gap Request. To cancel stop at the block gap, set Stop At block Gap Request to 0h (MMCSD0_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP = 0h) and set this bit to restart the transfer.

The Host Controller automatically clears this bit when the transaction re-starts.

If MMCSD0_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP = 1h, any write to this bit is ignored.

In SD mode, this bit is cleared in either of the following cases:

1) In the case of a read transaction, the DAT Line Active changes from 0h to 1h as a read transaction restarts.

2) In the case of a write transaction, the Write transfer active changes from 0h to 1h as the write transaction restarts.

Therefore it is not necessary for Host driver to set this bit to 0h. If MMCSD0_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP = 1h, any write to this bit is ignored.

1h: Restart

0h: Ignored
0 STOP_AT_BLK_GAP R/W 0h

Stop At Block Gap Request

This bit is used to stop executing a transaction at the next block gap for non-DMA, SDMA and ADMA transfers. Until the transfer complete is set to 1h, indicating a transfer completion the HD shall leave this bit set to 1h.

Clearing both the MMCSD0_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP and MMCSD0_BLOCK_GAP_CONTROL[1] CONTINUE bits shall not cause the transaction to restart. The MMCSD0_BLOCK_GAP_CONTROL[2] RDWAIT_CTRL bit is used to stop the read transaction at the block gap. The HC shall honour Stop At Block Gap Request for write transfers, but for read transfers it requires that the SD card support Read Wait. Therefore the HD shall not set this bit during read transfers unless the SD card supports Read Wait and has set Read Wait Control to 1h (MMCSD0_BLOCK_GAP_CONTROL[2] RDWAIT_CTRL) = 1h). In case of write transfers in which the HD writes data to the MMCSD0_DATA_PORT register, the HD shall set this bit after all block data is written. If this bit is set to 1h, the HD shall not write data to the MMCSD0_DATA_PORT register. This bit affects Read Transfer Active, Write Transfer Active, DAT line active and Command Inhibit (DAT) in the MMCSD0_PRESENTSTATE register.

In case of UHS-II, a transaction can be stopped at the boundary of DATA Burst (Flow Control basis). Host Controller waits for sending Flow Control MSG until the MMCSD0_BLOCK_GAP_CONTROL[1] CONTINUE bit is set to 1h.

1h: Stop

0h: Transfer

There are three cases to restart the transfer after stop at the block gap. Which case is appropriate depends on whether the HC issues a Suspend command or the SD card accepts the Suspend command.

1. If the HD does not issue Suspend command, the Continue Request shall be used to restart the transfer.

2. If the HD issues a Suspend command and the SD card accepts it, a Resume Command shall be used to restart the transfer.

3. If the HD issues a Suspend command and the SD card does not accept it, the Continue Request shall be used to restart the transfer.

Any time Stop At Block Gap Request stops the data transfer, the HD shall wait for Transfer Complete (in the MMCSD0_NORMAL_INTR_STS register) before attempting to restart the transfer. When restarting the data transfer by Continue Request, the HD shall clear Stop At Block Gap Request before or simultaneously.

Host Controller should not generate timeout interrupts while Stop At Block Gap is set. Host Driver should ignore timeout interrupts while Stop At Block Gap is set.

6.6.4.15 MMCSD0_WAKEUP_CONTROL Register (Offset = 2Bh) [reset = 0h]

MMCSD0_WAKEUP_CONTROL is shown in Figure 12-2329 and described in Table 12-4501.

Return to Summary Table.

This register is used to program the wakeup functionality.

The MMCSD0_WAKEUP_CONTROL register is mandatory for the HC, but wakeup functionality depends on the HC system hardware and software. The HD shall maintain voltage on the SD Bus, by setting the MMCSD0_POWER_CONTROL[0] SD_BUS_POWER bit to 1h, when wakeup event via card interrupt is desired.

Table 12-4500 MMCSD0_WAKEUP_CONTROL Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 002Bh
Figure 12-2329 MMCSD0_WAKEUP_CONTROL Register
7 6 5 4 3 2 1 0
RESERVED CARD_REMOVAL CARD_INSERTION CARD_INTERRUPT
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4501 MMCSD0_WAKEUP_CONTROL Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R 0h

Reserved
2 CARD_REMOVAL R/W 0h

Wakeup Event Enable On SD Card Removal

This bit enables wakeup event via Card removal assertion in the MMCSD0_NORMAL_INTR_STS register.

FN_WUS (Wake up Support) in CIS does not affect this bit.

1h: Enable

0h: Disable
1 CARD_INSERTION R/W 0h

Wakeup Event Enable On SD Card Insertion

This bit enables wakeup event via Card Insertion assertion in the MMCSD0_NORMAL_INTR_STS register.

FN_WUS (Wake up Support) in CIS does not affect this bit.

1h: Enable

0h: Disable
0 CARD_INTERRUPT R/W 0h

Wakeup Event Enable On Card Interrupt

This bit enables wakeup event via Card Interrupt assertion in the MMCSD0_NORMAL_INTR_STS register.

This bit can be set to 1h if FN_WUS (Wake Up Support) in CIS is set to 1h.

1h: Enable

0h: Disable

6.6.4.16 MMCSD0_CLOCK_CONTROL Register (Offset = 2Ch) [reset = 0h]

MMCSD0_CLOCK_CONTROL is shown in Figure 12-2330 and described in Table 12-4503.

Return to Summary Table.

This register is used to program the Clock frequency select, Clock generator select, Clock enable, Internal clock state fields.

At the initialization of the HC, the HD shall set the SDCLK Frequency Select (MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL) according to the MMCSD0_CAPABILITIES register. This register controls SDCLK in SD Mode and RCLK in UHS-II mode.

Table 12-4502 MMCSD0_CLOCK_CONTROL Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 002Ch
Figure 12-2330 MMCSD0_CLOCK_CONTROL Register
15 14 13 12 11 10 9 8
SDCLK_FRQSEL
R/W-0h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL_UPBITS CLKGEN_SEL RESERVED PLL_ENA SD_CLK_ENA INT_CLK_STABLE INT_CLK_ENA
R/W-0h R/W-0h R-0h R/W-0h R/W-0h R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4503 MMCSD0_CLOCK_CONTROL Register Field Descriptions
Bit Field Type Reset Description
15-8 SDCLK_FRQSEL R/W 0h

SDCLK/RCLK Frequency Select

This register is used to select the frequency of the SDCLK pin. The frequency is not programmed directly; rather this register holds the divisor of the Base Clock Frequency For SD clock in the Capabilities register (MMCSD0_CAPABILITIES[15-8] BASE_CLK_FREQ).

Only the following settings are allowed.

(1) 8-bit Divided Clock Mode:

80h: base clock divided by 256

40h: base clock divided by 128

20h: base clock divided by 64

10h: base clock divided by 32

08h: base clock divided by 16

04h: base clock divided by 8

02h: base clock divided by 4

01h: base clock divided by 2

00h: base clock (10 MHz - 63 MHz)

Setting 00h specifies the highest frequency of the SD Clock. When setting multiple bits, the most significant bit is used as the divisor. But multiple bits should not be set. The three default divider values can be calculated by the frequency that is defined by the MMCSD0_CAPABILITIES[15-8] BASE_CLK_FREQ bit field.

400 KHz divider value

25 MHz divider value

50 MHz divider value

According to the Physical Layer Specification, the maximum SD Clock frequency is 25 MHz in normal speed mode and 50 MHz in high speed mode, and shall never exceed this limit.

The frequency of SDCLK is set by the following formula:

Clock Frequency = (Base Clock) / divisor

Thus, choose the smallest possible divisor which results in a clock frequency that is less than or equal to the target frequency.

For example, if the MMCSD0_CAPABILITIES[15-8] BASE_CLK_FREQ bit field has the value 33 MHz, and the target frequency is 25 MHz, then choosing the divisor value of 1h will yield 16.5 MHz, which is the nearest frequency less than or equal to the target. Similarly, to approach a clock value of 400 KHz, the divisor value of 40h yields the optimal clock value of 258 KHz.

(2) 10-bit Divided Clock Mode:

Host Controller Version 3.00 or later supports this mandatory mode instead of the 8-bit Divided Clock Mode. The length of divider is extended to 10 bits and all divider values shall be supported.

3FFh: 1/2046 Divided Clock

N: 1/2N Divided Clock (Duty 50%)

002h: 1/4 Divided Clock

001h: 1/2 Divided Clock

000h: Base Clock (10 MHz - 254 MHz)

(3) Programmable Clock Mode:

Host Controller Version 3.00 or later supports this mode as optional. A non-zero value set to the MMCSD0_CAPABILITIES[55-48] CLOCK_MULTIPLIER bit field indicates support of this clock mode. The multiplier enables the Host System to select a finer grain SD clock frequency. It is not necessary to support all frequency generation specified by this field because programmable clock generator is vendor specific and dependent on the implementation. Therefore, this mode is used with Preset Value registers (MMCSD0_PRESET_VALUE0 - MMCSD0_PRESET_VALUE10). The Host Controller vendor provides possible settings and the Host System vendor sets appropriate values to the Preset Value registers (MMCSD0_PRESET_VALUE0 - MMCSD0_PRESET_VALUE10).

3FFh - Base Clock × M / 1024

........... .......................

N-1 - Base Clock × M / N

........... .......................

002h - Base Clock × M / 3

001h - Base Clock × M / 2

000h - Base Clock × M

This field depends on setting of the MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA bit.

If MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA = 0h, this field is set by Host Driver.

If MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA = 1h, this field is automatically set to a value specified in one of Preset Value registers (MMCSD0_PRESET_VALUE0 - MMCSD0_PRESET_VALUE10).
7-6 SDCLK_FRQSEL_UPBITS R/W 0h

Upper Bits of SDCLK/RCLK Frequency Select

This bit field is assigned to the MMCSD0_CLOCK_CONTROL[9-8] SDCLK_FRQSEL bit field of clock divider in SDCLK/RCLK Frequency Select.
5 CLKGEN_SEL R/W 0h

Clock Generator Select

This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select (MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL).

If the Programmable Clock Mode is supported (non-zero value is set to the MMCSD0_CAPABILITIES[55-48] CLOCK_MULTIPLIER bit field), this bit attribute is R/W, and if not supported, this bit attribute is RO and zero is read.

This bit depends on the setting of the MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA bit.

If MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA = 0h, this bit is set by Host Driver.

If MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA = 1h, this bit is automatically set to a value specified in one of Preset Value registers (MMCSD0_PRESET_VALUE0 - MMCSD0_PRESET_VALUE10).

1h: Programmable Clock Mode

0h: Divided Clock Mode
4 RESERVED R 0h

Reserved
3 PLL_ENA R/W 0h

PLL Enable

This bit is added from Version 4.10 for Host Controller using PLL. This feature allows Host Controller to initialize clock generator in two steps: by Internal Clock Enable (MMCSD0_CLOCK_CONTROL[0] INT_CLK_ENA) and PLL Enable and to minimize output latency (for example SDCLK/RCLK, D0 lane) from SD Clock Enable (MMCSD0_CLOCK_CONTROL[2] SD_CLK_ENA). There are two modes to keep Host Drivers compatibility. In both modes, PLL Locked timing is indicated by Internal Clock Stable (MMCSD0_CLOCK_CONTROL[1] INT_CLK_STABLE).

(1) When MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 0h (Host Driver Version 3, which does not support this bit) or this bit is not implemented, the MMCSD0_CLOCK_CONTROL[0] INT_CLK_ENA bit (or the MMCSD0_CLOCK_CONTROL[2] SD_CLK_ENA bit) may activate PLL (exit low power mode and start locking clock).

(2) When MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 1h (Host Driver Version 4), the MMCSD0_CLOCK_CONTROL[0] INT_CLK_ENA bit is set before setting this bit and then setting this bit may activate PLL (exit low power mode and start locking clock).

1h: PLL is enabled

0h: PLL is in low power mode
2 SD_CLK_ENA R/W 0h

SD Clock Enable

The HC shall stop SDCLK when writing this bit to 0h. The MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field can be changed when this bit is 0h. Then, the HC shall maintain the same clock frequency until SDCLK is stopped (Stop at SDCLK = 0). If the HC detects the No Card state, this bit shall be cleared.

1h: Enable providing SDCLK or RCLK

0h: Disable providing SDCLK or RCLK
1 INT_CLK_STABLE R 0h

Internal Clock Stable

This bit is set to 1h when SD clock is stable after writing 1h to MMCSD0_CLOCK_CONTROL[0] INT_CLK_ENA bit. The SD Host Driver shall wait to set the MMCSD0_CLOCK_CONTROL[2] SD_CLK_ENA bit until this bit is set to 1h.

Note: This is useful when using PLL for a clock oscillator that requires setup time.

(1) Internal Clock Stable (when MMCSD0_CLOCK_CONTROL[3] PLL_ENA = 0h or not supported)

This bit is set to 1h when internal clock is stable after writing 1h to MMCSD0_CLOCK_CONTROL[0] INT_CLK_ENA bit.

(2) PLL Clock Stable (when MMCSD0_CLOCK_CONTROL[3] PLL_ENA = 1h)

Host Controller which supports PLL Enable sets this status to 0h once when PLL Enable is changed 0h to 1h and then this status is set to 1h when PLL is locked (PLL uses an internal clock in stable as a reference clock which is enabled by the MMCSD0_CLOCK_CONTROL[0] INT_CLK_ENA bit). After this bit is set to 1h, Host Driver may set the MMCSD0_CLOCK_CONTROL[2] SD_CLK_ENA bit.

1h: Ready

0h: Not Ready
0 INT_CLK_ENA R/W 0h

Internal Clock Enable

This bit is set to 0h when the HD is not using the HC or the HC awaits a wakeup event. The HC should stop its internal clock to go very low power state. Still, registers shall be able to be read and written. Clock starts to oscillate when this bit is set to 1h. When clock oscillation is stable, the HC shall set the MMCSD0_CLOCK_CONTROL[1] INT_CLK_STABLE bit to 1h. This bit shall not affect card detection.

1h: Oscillate

0h: Stop

6.6.4.17 MMCSD0_TIMEOUT_CONTROL Register (Offset = 2Eh) [reset = 0h]

MMCSD0_TIMEOUT_CONTROL is shown in Figure 12-2331 and described in Table 12-4505.

Return to Summary Table.

The register sets the data timeout counter value.

At the initialization of the HC, the HD shall set the Data Timeout Counter Value according to the MMCSD0_CAPABILITIES register.

Table 12-4504 MMCSD0_TIMEOUT_CONTROL Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 002Eh
Figure 12-2331 MMCSD0_TIMEOUT_CONTROL Register
7 6 5 4 3 2 1 0
RESERVED COUNTER_VALUE
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4505 MMCSD0_TIMEOUT_CONTROL Register Field Descriptions
Bit Field Type Reset Description
7-4 RESERVED R 0h

Reserved
3-0 COUNTER_VALUE R/W 0h

Data Timeout Counter Value

This value determines the interval by which DAT line time-outs are detected. Refer to the MMCSD0_ERROR_INTR_STS[4] DATA_TIMEOUT bit for information on factors that dictate time-out generation. Time-out clock frequency will be generated by dividing the SD clock TMCLK by this value. When setting this register, prevent inadvertent time-out events by clearing the MMCSD0_ERROR_INTR_STS[4] DATA_TIMEOUT bit.

1111: Reserved

1110: TMCLK × 227

--------------------

--------------------

0001: TMCLK × 214

0000: TMCLK × 213

6.6.4.18 MMCSD0_SOFTWARE_RESET Register (Offset = 2Fh) [reset = 0h]

MMCSD0_SOFTWARE_RESET is shown in Figure 12-2332 and described in Table 12-4507.

Return to Summary Table.

This register is used to program the software reset for data, command and for all.

A reset pulse is generated when writing 1h to each bit of this register. After completing the reset, the HC shall clear each bit. Because it takes some time to complete software reset, the SD Host Driver shall confirm that these bits are 0h.

Table 12-4506 MMCSD0_SOFTWARE_RESET Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 002Fh
Figure 12-2332 MMCSD0_SOFTWARE_RESET Register
7 6 5 4 3 2 1 0
RESERVED SWRST_FOR_DAT SWRST_FOR_CMD SWRST_FOR_ALL
R-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4507 MMCSD0_SOFTWARE_RESET Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R 0h

Reserved
2 SWRST_FOR_DAT R/W 0h

Software Reset for DAT Line (SD Mode Only)

Only part of data circuit is reset. The following registers and bits are cleared by this bit:

MMCSD0_DATA_PORT

Buffer is cleared and Initialized.

MMCSD0_PRESENTSTATE

Buffer read Enable

Buffer write Enable

Read Transfer Active

Write Transfer Active

DAT Line Active

Command Inhibit (DAT)

MMCSD0_BLOCK_GAP_CONTROL

Continue Request

Stop At Block Gap Request

MMCSD0_NORMAL_INTR_ST

Buffer Read Ready

Buffer Write Ready

Block Gap Event

Transfer Complete

1h: Reset

0h: Work
1 SWRST_FOR_CMD R/W 0h

Software Reset for CMD Line (SD Mode Only)

Only part of command circuit is reset to be able to issue a command. From Version 4.10, this bit is also used to initialize UHS-II command circuit. This reset is effective only command issuing circuit (including response error statuses related to Command Inhibit (CMD) control - MMCSD0_PRESENTSTATE[0] INHIBIT_CMD bit) and does not affect data transfer circuit. Host Controller can continue data transfer even this reset is executed during handling of sub command response errors.

The following registers and bits are cleared by this bit:

MMCSD0_PRESENTSTATE register:

Command Inhibit (CMD)

MMCSD0_NORMAL_INTR_STS register:

Command Complete

MMCSD0_ERROR_INTR_STS register (Error Interrupt Status from Version 4.10)

Response error statuses related to Command Inhibit (CMD) - MMCSD0_PRESENTSTATE[0] INHIBIT_CMD bit

1h: Reset

0h: Work
0 SWRST_FOR_ALL R/W 0h

Software Reset for All

This reset affects the entire HC except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are cleared to 0h. During its initialization, the HD shall set this bit to 1h to reset the HC. The HC shall reset this bit to 0h when Capabilities registers are valid and the HD can read them. Additional use of 'Software Reset For All' may not affect the value of the Capabilities registers. If this bit is set to 1h, the SD card shall reset itself and must be re-initialized by the HD.

1h: Reset

0h: Work

6.6.4.19 MMCSD0_NORMAL_INTR_STS Register (Offset = 30h) [reset = 0h]

MMCSD0_NORMAL_INTR_STS is shown in Figure 12-2333 and described in Table 12-4509.

Return to Summary Table.

This register gives the status of all the interrupts.

The Normal Interrupt Signal Enable (see MMCSD0_NORMAL_INTR_SIG_ENA register) affects read of this register, but Normal Interrupt Signal does not affect these reads. An Interrupt is generated when the Normal Interrupt Signal Enable is enabled and at least one of the status bits is set to 1h. For all bits except Card Interrupt (MMCSD0_NORMAL_INTR_STS[8] CARD_INTR) and Error Interrupt (MMCSD0_NORMAL_INTR_STS[15] ERROR_INTR), writing 1h to a bit clears it. The MMCSD0_NORMAL_INTR_STS[8] CARD_INTR bit is cleared when the card stops asserting the interrupt: that is when the Card Driver services the Interrupt condition.

Table 12-4508 MMCSD0_NORMAL_INTR_STS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0030h
Figure 12-2333 MMCSD0_NORMAL_INTR_STS Register
15 14 13 12 11 10 9 8
ERROR_INTR BOOT_COMPLETE RCV_BOOT_ACK RETUNING_EVENT INTC INTB INTA CARD_INTR
R-0h R/W1C-0h R/W1C-0h R-0h R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
CARD_REM CARD_INS BUF_RD_READY BUF_WR_READY DMA_INTERRUPT BLK_GAP_EVENT XFER_COMPLETE CMD_COMPLETE
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-4509 MMCSD0_NORMAL_INTR_STS Register Field Descriptions
Bit Field Type Reset Description
15 ERROR_INTR R 0h

Error Interrupt

If any of the bits in the MMCSD0_ERROR_INTR_STS register are set, then this bit is set. Therefore the HD can test for an error by checking this bit first.

In UHS-II mode is enabled, if any of the bits in the MMCSD0_UHS2_ERR_INTR_STS register are set, this bit is also set.

0h: No Error

1h: Error
14 BOOT_COMPLETE R/W1C 0h

Boot Terminate Interrupt

This status is set if the boot operation gets terminated.

0h: Boot operation is not terminated

1h: Boot operation is terminated
13 RCV_BOOT_ACK R/W1C 0h

Boot Acknowledge Receive

This status is set if the boot acknowledge is received from device.

0h: Boot acknowledge is not received

1h: Boot acknowledge is received
12 RETUNING_EVENT R 0h

Re-Tuning Event (UHS-I Only)

This status is set if the MMCSD0_PRESENTSTATE[3] RETUNING_REQ bit changes from 0h to 1h.

Host Controller requests Host Driver to perform re-tuning for next data transfer. Current data transfer (not large block count) can be completed without re-tuning.

In UHS-II mode, this bit is not effective.

1h: Re-Tuning should be performed

0h: Re-Tuning is not required
11 INTC R 0h

int_c (Embedded)

This status is set if INT_C is enabled and INT_C# pin is in low level. Writing this bit to 1h does not clear this bit. It is cleared by resetting the INT_C interrupt factor.
10 INTB R 0h

int_b (Embedded)

This status is set if INT_B is enabled and INT_B# pin is in low level. Writing this bit to 1h does not clear this bit. It is cleared by resetting the INT_B interrupt factor.
9 INTA R 0h

int_a (Embedded)

This status is set if INT_A is enabled and INT_A# pin is in low level. Writing this bit to 1h does not clear this bit. It is cleared by resetting the INT_A interrupt factor.
8 CARD_INTR R 0h

Card Interrupt

When this status has been set and the Host Driver needs to start this interrupt service, the MMCSD0_NORMAL_INTR_STS_ENA[8] CARD_INTERRUPT bit may be set to 0h in order to clear the card interrupt status latched in the Host Controller and to stop driving the interrupt signal to the Host System. After completion of the card interrupt service (it should reset interrupt factors in the SD card and the interrupt signal may not be asserted), set the MMCSD0_NORMAL_INTR_STS_ENA[8] CARD_INTERRUPT bit to 1h and start sampling the interrupt signal again.

Writing this bit to 1h does not clear this bit. It is cleared by resetting the SD card interrupt factor.

(1) DAT[1] Interrupt Input in SD Mode

In 1-bit mode, the Host Controller shall detect the Card Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the SD card and the interrupt to the Host System. Interrupt detected by DAT[1] is supported when there is a card per slot. In case of UHS-I mode, switching time of Interrupt Period is relaxed for 2 clock cycles. Then Host Controller needs to delay start of interrupt sampling at least 2 clocks and should sample interrupt while Interrupt Period is stable.

(2) DAT[2] Interrupt Input in UHS-II Mode

When the MMCSD0_PRESENTSTATE[16] CARD_INSERTED and MMCSD0_POWER_CONTROL[0] SD_BUS_POWER bits are set to 1h, Host Controller configures DAT[2] as Interrupt Input and enables pull-up of DAT[2]. DAT[2] interrupt is asynchronous to RCLK, low level sensitive and 3.3 V signal level. DAT[2] interrupt is masked by setting the MMCSD0_NORMAL_INTR_STS_ENA[8] CARD_INTERRUPT bit to 0h. When either the MMCSD0_PRESENTSTATE[16] CARD_INSERTED bit or the MMCSD0_POWER_CONTROL[0] SD_BUS_POWER bit is set to 0h, Host Controller sets DAT[2] to low. Only point to point connection is allowed between Host and Card.

(3) INT MSG in UHS-II Mode

INT MSG is enabled by setting the MMCSD0_UHS2_DEVICE_SELECT[7] INT_MSG_ENA bit. DAT[2] and INT MSG interrupt sources are ORed and indicated to Card Interrupt. If any bit in the MMCSD0_UHS2_DEVICE_INTR_STATUS register is set to 1h, INT MSG interrupt is generated. INT MSG interrupt is cleared by writing a correspondent bit to 1h in the MMCSD0_UHS2_DEVICE_INTR_STATUS register. Masking DAT[2] interrupt also disables INT MSG interupt due to the MMCSD0_NORMAL_INTR_STS_ENA[8] CARD_INTERRUPT bit is set to 0h. SDIO Version 4.00 does not support INT MSG.

1h: Generate Card Interrupt

0h: No Card Interrupt
7 CARD_REM R/W1C 0h

Card Removal

This status is set if the MMCSD0_PRESENTSTATE[16] CARD_INSERTED bit changes from 1h to 0h. When the HD writes this bit to 1h to clear this status the status of the MMCSD0_PRESENTSTATE[16] CARD_INSERTED bit should be confirmed. Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.

0h: Card State Stable or Debouncing

1h: Card Removed
6 CARD_INS R/W1C 0h

Card Insertion

This status is set if the MMCSD0_PRESENTSTATE[16] CARD_INSERTED bit changes from 0h to 1h. When the HD writes this bit to 1h to clear this status the status of the MMCSD0_PRESENTSTATE[16] CARD_INSERTED bit should be confirmed. Because the card detect may possibly be changed when the HD clear this bit an Interrupt event may not be generated.

0h: Card State Stable or Debouncing

1h: Card Inserted
5 BUF_RD_READY R/W1C 0h

Buffer Read Ready

This status is set if the MMCSD0_PRESENTSTATE[11] BUF_RD_ENA bit changes from 0h to 1h.

The MMCSD0_PRESENTSTATE[11] BUF_RD_ENA bit is set to 1h for every CMD19 execution in tuning procedure.

In UHS-II mode, this bit is set at FC (Flow Control) unit basis.

0h: Not Ready to read Buffer

1h: Ready to read Buffer
4 BUF_WR_READY R/W1C 0h

Buffer Write Ready

This status is set if the MMCSD0_PRESENTSTATE[10] BUF_WR_ENA bit changes from 0h to 1h.

In UHS-II mode, this bit is set at FC (Flow Control) unit basis.

0h: Not Ready to Write Buffer

1h: Ready to Write Buffer
3 DMA_INTERRUPT R/W1C 0h

DMA Interrupt

This status is set if the HC detects the Host DMA Buffer Boundary in the MMCSD0_BLOCK_SIZE regiser.

0h: No DMA Interrupt

1h: DMA Interrupt is Generated
2 BLK_GAP_EVENT R/W1C 0h

Block Gap Event

If the MMCSD0_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP bit is set, this bit is set.

Read Transaction:

This bit is set at the falling edge of the DAT Line Active Status (see MMCSD0_PRESENTSTATE[2] DATA_LINE_ACTIVE bit). When the transaction is stopped at SD Bus timing. The Read Wait must be supported in order to use this function.

Write Transaction:

This bit is set at the falling edge of Write Transfer Active Status (see MMCSD0_PRESENTSTATE[8] WR_XFER_ACTIVE bit). After getting CRC status at SD Bus timing. In UHS-II mode, this bit is set at FC (Flow Control) unit basis.

0h: No Block Gap Event

1h: Transaction stopped at Block Gap
1 XFER_COMPLETE R/W1C 0h

Transfer Complete

This bit is set when a read/write transaction is completed.

SD Mode

Read Transaction:

This bit is set at the falling edge of Read Transfer Active Status (MMCSD0_PRESENTSTATE[9] RD_XFER_ACTIVE).

There are two cases in which the Interrupt is generated. The first is when a data transfer is completed as specified by data length (after the last data has been read to the Host System). The second is when data has stopped at the block gap and completed the data transfer by setting the MMCSD0_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP bit (after valid data has been read to the Host System).

Write Transaction:

This bit is set at the falling edge of the DAT Line Active Status (see MMCSD0_PRESENTSTATE[2] DATA_LINE_ACTIVE bit). There are two cases in which the Interrupt is generated. The first is when the last data is written to the card as specified by data length and Busy signal is released. The second is when data transfers are stopped at the block gap by setting the MMCSD0_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP bit and data transfers completed (after valid data is written to the SD card and the busy signal is released).

Note: MMCSD0_NORMAL_INTR_STS[1] XFER_COMPLETE bit has higher priority than the MMCSD0_ERROR_INTR_STS[4] DATA_TIMEOUT bit. If both bits are set to 1h, the data transfer can be considered complete.

Note: While performing tuning procedure (the MMCSD0_HOST_CONTROL2[6] EXECUTE_TUNING bit is set to 1h), the MMCSD0_NORMAL_INTR_STS[1] XFER_COMPLETE bit is not set to 1h.

Command with Busy:

This bit is set when busy is de-asserted. Refer to DAT Line Active and Command Inhibit (DAT) in the MMCSD0_PRESENTSTATE register.

UHS-I mode

While performing tuning procedure (the MMCSD0_HOST_CONTROL2[6] EXECUTE_TUNING bit is set to 1h), the MMCSD0_NORMAL_INTR_STS[1] XFER_COMPLETE bit is not set to 1h.

0h: No Data Transfer Complete

1h: Data Transfer Complete

UHS-II Mode

This interrupt is generated in following two cases:

(a) EBSY Completion (for EBSY supported commands)

When the MMCSD0_UHS2_XFER_MODE[14] EBSY_WAIT bit is set to 1h, this bit is set when EBSY packet has been received, and all valid data have been sent to system memory in case of read operation.

(b) Stop and Continue during DCMD Data Transfer

When the MMCSD0_BLOCK_GAP_CONTROL[0] STOP_AT_BLK_GAP bit is set to 1h and data transfer is stopped at the Flow Control.

Following is for both SD mode and UHS-II mode.

The table below shows that the MMCSD0_NORMAL_INTR_STS[1] XFER_COMPLETE bit has higher priority than the MMCSD0_ERROR_INTR_STS[4] DATA_TIMEOUT bit. If both bits are set to 1h, execution of a command can be considered to be completed.

1h: Command execution is completed

0h: Not complete
0 CMD_COMPLETE R/W1C 0h

Command Complete

SD Mode

This bit is set when we get the end bit of the command response (Except Auto CMD12 and Auto CMD23).

Note: The MMCSD0_ERROR_INTR_STS[0] CMD_TIMEOUT bit has higher priority than the MMCSD0_NORMAL_INTR_STS[0] CMD_COMPLETE bit. If both are set to 1h, it can be considered that the response was not received correctly.

Version 4.00 defines response check function for R1 and R5. If the MMCSD0_TRANSFER_MODE[8] RESP_INTR_DIS bit is set to 1h, generation of this interrupt is prohibited regardless of the MMCSD0_NORMAL_INTR_SIG_ENA[0] CMD_COMPLETE bit.

UHS-II Mode

If the MMCSD0_TRANSFER_MODE[8] RESP_INTR_DIS bit is set to 0h, this interrupt is generated when response packet is received.

If the MMCSD0_TRANSFER_MODE[8] RESP_INTR_DIS bit is set to 1h, generation of this interrupt is prohibited regardless of the MMCSD0_NORMAL_INTR_SIG_ENA[0] CMD_COMPLETE bit.

0h: No Command Complete

1h: Command Complete

Table 12-4510 shows the relation between transfer complete and data timeout error.

Table 12-4510 Relation between transfer complete and data timeout error
Transfer Complete Data Timeout Error Meaning of the Status
0 0 Interrupted by Another Factor
0 1 Timeout occur during transfer
1 Don't Care Data Transfer Complete

Table 12-4511 shows the relation between command complete and command timeout error.

Table 12-4511 Relation between command complete and command timeout error
Command Complete Command Timeout Error Meaning of the Status
0 0 Interrupted by Another Factor
Don't Care 1 Response not received within 64 SDCLK cycles
1 0 Response Received

6.6.4.20 MMCSD0_ERROR_INTR_STS Register (Offset = 32h) [reset = 0h]

MMCSD0_ERROR_INTR_STS is shown in Figure 12-2334 and described in Table 12-4513.

Return to Summary Table.

This register gives the status of the error interrupts.

Status defined in this register can be enabled by the MMCSD0_ERROR_INTR_STS_ENA register, but not by the MMCSD0_ERROR_INTR_SIG_ENA register. The Interrupt is generated when the MMCSD0_ERROR_INTR_SIG_ENA register is enabled and at least one of the statuses is set to 1h. Writing to 1h clears the bit and writing to 0h keeps the bit unchanged. More than one status can be cleared at the one register write.

Table 12-4512 MMCSD0_ERROR_INTR_STS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0032h
Figure 12-2334 MMCSD0_ERROR_INTR_STS Register
15 14 13 12 11 10 9 8
RESERVED HOST RESP RESERVED ADMA AUTO_CMD
R-0h R/W1C-0h R/W1C-0h R-0h R/W1C-0h R/W1C-0h
7 6 5 4 3 2 1 0
CURR_LIMIT DATA_ENDBIT DATA_CRC DATA_TIMEOUT CMD_INDEX CMD_ENDBIT CMD_CRC CMD_TIMEOUT
R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-4513 MMCSD0_ERROR_INTR_STS Register Field Descriptions
Bit Field Type Reset Description
15-13 RESERVED R 0h

Reserved
12 HOST R/W1C 0h

Target Response Error

Occurs when detecting ERROR in m_hresp (DMA transaction)

0h: No error

1h: Error
11 RESP R/W1C 0h

Response Error (SD Mode Only)

Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If the MMCSD0_TRANSFER_MODE[7] RESP_ERR_CHK_ENA bit is set to 1h, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1h.

0h: No error

1h: Error
10 RESERVED R 0h

Reserved
9 ADMA R/W1C 0h

ADMA Error

This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the MMCSD0_ADMA_ERR_STATUS register.

0h: No error

1h: Error
8 AUTO_CMD R/W1C 0h

Auto CMD Error (SD Mode Only)

Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that any of the bits D00 to D05 in the MMCSD0_AUTOCMD_ERR_STS register has changed from 0h to 1h. D07 is effective in case of Auto CMD12. The MMCSD0_AUTOCMD_ERR_STS register is valid while this bit is set to 1h and may be cleared with clearing of this bit (another implementation is also allowed).

0h: No error

1h: Error
7 CURR_LIMIT R/W1C 0h

Current Limit Error

By setting the MMCSD0_POWER_CONTROL[0] SD_BUS_POWER bit, the HC is requested to supply power for the SD Bus. If the HC supports the Current Limit Function, it can be protected from an Illegal card by stopping power supply to the card in which case this bit indicates a failure status. Reading 1h means the HC is not supplying power to SD card due to some failure. Reading 0 means that the HC is supplying power and no error has occurred. This bit shall always set to be 0, if the HC does not support this function.

0h: No error

1h: Power Fail
6 DATA_ENDBIT R/W1C 0h

Data End Bit Error (SD Mode Only)

Occurs when detecting 0 at the end bit position of read data which uses the DAT line or the end bit position of the CRC status.

0h: No error

1h: Error
5 DATA_CRC R/W1C 0h

Data CRC Error (SD Mode Only)

Occurs when detecting CRC error when transferring read data which uses the DAT line or when detecting the Write CRC Status having a value of other than 2h.

0h: No error

1h: Error
4 DATA_TIMEOUT R/W1C 0h

Data Timeout Error (SD Mode Only)

Occurs when detecting one of following timeout conditions:

1. Busy Timeout for R1b, R5b type

2. Busy Timeout after Write CRC status

3. Write CRC status Timeout

4. Read Data Timeout

0h: No error

1h: Timeout
3 CMD_INDEX R/W1C 0h

Command Index Error (SD Mode Only)

Occurs if a Command Index error occurs in the Command Response (MMCSD0_RESPONSE_0 to MMCSD0_RESPONSE_7).

0h: No error

1h: Error
2 CMD_ENDBIT R/W1C 0h

Command End Bit Error (SD Mode Only)

Occurs when detecting that the end bit of a command response is 0h.

0h: No error

1h: End Bit Error Generated
1 CMD_CRC R/W1C 0h

Command CRC Error (SD Mode Only)

Command CRC Error is generated in two cases.

1. If a response is returned and the MMCSD0_ERROR_INTR_STS[0] CMD_TIMEOUT bit is set to 0h, this bit is set to 1h when detecting a CRT error in the command response.

2. The HC detects a CMD line conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD line to 1 level, but detects 0 level on the CMD line at the next SDCLK edge, then the HC shall abort the command (Stop driving CMD line) and set this bit to 1h. The MMCSD0_ERROR_INTR_STS[0] CMD_TIMEOUT bit shall also be set to 1h to distinguish CMD line conflict.

0h: No error

1h: CRC Error Generated
0 CMD_TIMEOUT R/W1C 0h

Command Timeout Error (SD Mode Only)

Occurs only if the no response is returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a CMD line conflict, in which case the MMCSD0_ERROR_INTR_STS[1] CMD_CRC bit shall also be set. This bit shall be set without waiting for 64 SDCLK cycles because the command will be aborted by the HC.

0h: No error

1h: Timeout

Table 12-4514 shows the relation between command CRC error and command time-out error.

Table 12-4514 Relation between command CRC error and command time-out error
Command CRC Error Command Time-out Error Kinds of Error
0 0 No Error
0 1 Response Timeout Error
1 0 Response CRC Error
1 1 CMD Line Conflict

6.6.4.21 MMCSD0_NORMAL_INTR_STS_ENA Register (Offset = 34h) [reset = 0h]

MMCSD0_NORMAL_INTR_STS_ENA is shown in Figure 12-2335 and described in Table 12-4516.

Return to Summary Table.

This register is used to enable the MMCSD0_NORMAL_INTR_STS register fields.

Table 12-4515 MMCSD0_NORMAL_INTR_STS_ENA Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0034h
Figure 12-2335 MMCSD0_NORMAL_INTR_STS_ENA Register
15 14 13 12 11 10 9 8
BIT15_FIXED0 BOOT_COMPLETE RCV_BOOT_ACK RETUNING_EVENT INTC INTB INTA CARD_INTERRUPT
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CARD_REMOVAL CARD_INSERTION BUF_RD_READY BUF_WR_READY DMA_INTERRUPT BLK_GAP_EVENT XFER_COMPLETE CMD_COMPLETE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4516 MMCSD0_NORMAL_INTR_STS_ENA Register Field Descriptions
Bit Field Type Reset Description
15 BIT15_FIXED0 R 0h

Fixed to 0

The HC shall control error Interrupts using the MMCSD0_ERROR_INTR_STS_ENA register.
14 BOOT_COMPLETE R/W 0h

Boot Terminate Interrupt Enable

0h: Masked

1h: Enabled
13 RCV_BOOT_ACK R/W 0h

Boot Acknowledge Enable

0h: Masked

1h: Enabled
12 RETUNING_EVENT R/W 0h

Re-Tuning Event Status Enable (UHS-I Only)

0h: Masked

1h: Enabled
11 INTC R/W 0h

INT_C Status Enable (Embedded)

If this bit is set to 0h, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin are cleared to prevent inadvertent interrupts.
10 INTB R/W 0h

INT_B Status Enable (Embedded)

If this bit is set to 0h, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin are cleared to prevent inadvertent interrupts.
9 INTA R/W 0h

INT_A Status Enable (Embedded)

If this bit is set to 0h, the Host Controller shall clear the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin are cleared to prevent inadvertent interrupts.
8 CARD_INTERRUPT R/W 0h

Card Interrupt Status Enable

If this bit is set to 0h, the HC shall clear Interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1h. The HD may clear the MMCSD0_ERROR_INTR_STS_ENA[8] CARD_INTERRUPT bit before servicing the Card Interrupt and may set this bit again after all Interrupt requests from the card are cleared to prevent inadvertent Interrupts.

By setting this bit to 0h, interrupt input should be masked by implementation so that the interrupt Input is not affected by external signal in any state (for example: floating).

0h: Masked

1h: Enabled
7 CARD_REMOVAL R/W 0h

Card Removal Status Enable

0h: Masked

1h: Enabled
6 CARD_INSERTION R/W 0h

Card Insertion Status Enable

0h: Masked

1h: Enabled
5 BUF_RD_READY R/W 0h

Buffer Read Ready Status Enable

0h: Masked

1h: Enabled
4 BUF_WR_READY R/W 0h

Buffer Write Ready Status Enable

0h: Masked

1h: Enabled
3 DMA_INTERRUPT R/W 0h

DMA Interrupt Status Enable

0h: Masked

1h: Enabled
2 BLK_GAP_EVENT R/W 0h

Block Gap Event Status Enable

0h: Masked

1h: Enabled
1 XFER_COMPLETE R/W 0h

Transfer Complete Status Enable

0h: Masked

1h: Enabled
0 CMD_COMPLETE R/W 0h

Command Complete Status Enable

0h: Masked

1h: Enabled

Note: The HC may sample the card Interrupt signal during interrupt period and may hold its value in the flip-flop. If the MMCSD0_ERROR_INTR_STS_ENA[8] CARD_INTERRUPT bit is set to 0h, the HC shall clear all internal signals regarding Card Interrupt (MMCSD0_NORMAL_INTR_STS[8] CARD_INTR).

6.6.4.22 MMCSD0_ERROR_INTR_STS_ENA Register (Offset = 36h) [reset = 0h]

MMCSD0_ERROR_INTR_STS_ENA is shown in Figure 12-2336 and described in Table 12-4518.

Return to Summary Table.

This register is used to enable the MMCSD0_ERROR_INTR_STS register fields.

Table 12-4517 MMCSD0_ERROR_INTR_STS_ENA Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0036h
Figure 12-2336 MMCSD0_ERROR_INTR_STS_ENA Register
15 14 13 12 11 10 9 8
VENDOR_SPECIFIC RESP TUNING ADMA AUTO_CMD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CURR_LIMIT DATA_ENDBIT DATA_CRC DATA_TIMEOUT CMD_INDEX CMD_ENDBIT CMD_CRC CMD_TIMEOUT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4518 MMCSD0_ERROR_INTR_STS_ENA Register Field Descriptions
Bit Field Type Reset Description
15-12 VENDOR_SPECIFIC R/W 0h

Vendor Specific Error Status Enable

N/A
11 RESP R/W 0h

Response Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
10 TUNING R/W 0h

Tuning Error Status Enable (UHS-I Only)

0h: Masked

1h: Enabled
9 ADMA R/W 0h

ADMA Error Status Enable

0h: Masked

1h: Enabled
8 AUTO_CMD R/W 0h

Auto CMD Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
7 CURR_LIMIT R/W 0h

Current Limit Error Status Enable

0h: Masked

1h: Enabled
6 DATA_ENDBIT R/W 0h

Data End Bit Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
5 DATA_CRC R/W 0h

Data CRC Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
4 DATA_TIMEOUT R/W 0h

Data Timeout Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
3 CMD_INDEX R/W 0h

Command Index Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
2 CMD_ENDBIT R/W 0h

Command End Bit Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
1 CMD_CRC R/W 0h

Command CRC Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled
0 CMD_TIMEOUT R/W 0h

Command Timeout Error Status Enable (SD Mode Only)

0h: Masked

1h: Enabled

Note: To Detect CMD Line conflict, the HD must set both MMCSD0_ERROR_INTR_STS_ENA[0] CMD_TIMEOUT and MMCSD0_ERROR_INTR_STS_ENA[1] CMD_CRC bits to 1h.

6.6.4.23 MMCSD0_NORMAL_INTR_SIG_ENA Register (Offset = 38h) [reset = 0h]

MMCSD0_NORMAL_INTR_SIG_ENA is shown in Figure 12-2337 and described in Table 12-4520.

Return to Summary Table.

Normal Interrupt Signal Enable Register

This register is used to select which interrupt status is indicated to the Host System as the Interrupt. These status bits all share the sample 1 bit interrupt line. Setting any of these bits to 1h enables Interrupt generation.

Table 12-4519 MMCSD0_NORMAL_INTR_SIG_ENA Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0038h
Figure 12-2337 MMCSD0_NORMAL_INTR_SIG_ENA Register
15 14 13 12 11 10 9 8
BIT15_FIXED0 BOOT_COMPLETE RCV_BOOT_ACK RETUNING_EVENT INTC INTB INTA CARD_INTERRUPT
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CARD_REMOVAL CARD_INSERTION BUF_RD_READY BUF_WR_READY DMA_INTERRUPT BLK_GAP_EVENT XFER_COMPLETE CMD_COMPLETE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4520 MMCSD0_NORMAL_INTR_SIG_ENA Register Field Descriptions
Bit Field Type Reset Description
15 BIT15_FIXED0 R 0h

Fixed to 0

The HD shall control error Interrupts using the MMCSD0_ERROR_INTR_SIG_ENA register.
14 BOOT_COMPLETE R/W 0h

Boot Terminate Interrupt Signal Enable

0h: Masked

1h: Enabled
13 RCV_BOOT_ACK R/W 0h

Boot Acknowledge Receive Signal Enable

0h: Masked

1h: Enabled
12 RETUNING_EVENT R/W 0h

Re-Tuning Event Signal Enable (UHS-I Only)

0h: Masked

1h: Enabled
11 INTC R/W 0h

INT_C Signal Enable (Embedded)

0h: Masked

1h: Enabled
10 INTB R/W 0h

INT_B Signal Enable (Embedded)

0h: Masked

1h: Enabled
9 INTA R/W 0h

INT_A Signal Enable (Embedded)

0h: Masked

1h: Enabled
8 CARD_INTERRUPT R/W 0h

Card Interrupt Signal Enable

0h: Masked

1h: Enabled
7 CARD_REMOVAL R/W 0h

Card Removal Signal Enable

0h: Masked

1h: Enabled
6 CARD_INSERTION R/W 0h

Card Insertion Signal Enable

0h: Masked

1h: Enabled
5 BUF_RD_READY R/W 0h

Buffer Read Ready Signal Enable

0h: Masked

1h: Enabled
4 BUF_WR_READY R/W 0h

Buffer Write Ready Signal Enable

0h: Masked

1h: Enabled
3 DMA_INTERRUPT R/W 0h

DMA Interrupt Signal Enable

0h: Masked

1h: Enabled
2 BLK_GAP_EVENT R/W 0h

Block Gap Event Signal Enable

0h: Masked

1h: Enabled
1 XFER_COMPLETE R/W 0h

Transfer Complete Signal Enable

0h: Masked

1h: Enabled
0 CMD_COMPLETE R/W 0h

Command Complete Signal Enable

0h: Masked

1h: Enabled

6.6.4.24 MMCSD0_ERROR_INTR_SIG_ENA Register (Offset = 3Ah) [reset = 0h]

MMCSD0_ERROR_INTR_SIG_ENA is shown in Figure 12-2338 and described in Table 12-4522.

Return to Summary Table.

Error Interrupt Signal Enable Register

This register is used to select which interrupt status is notified to the Host System as the Interrupt. These status bits all share the same 1 bit interrupt line. Setting any of these bits to 1h enables Interrupt generation.

Table 12-4521 MMCSD0_ERROR_INTR_SIG_ENA Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 003Ah
Figure 12-2338 MMCSD0_ERROR_INTR_SIG_ENA Register
15 14 13 12 11 10 9 8
VENDOR_SPECIFIC RESP TUNING ADMA AUTO_CMD
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
CURR_LIMIT DATA_ENDBIT DATA_CRC DATA_TIMEOUT CMD_INDEX CMD_ENDBIT CMD_CRC CMD_TIMEOUT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4522 MMCSD0_ERROR_INTR_SIG_ENA Register Field Descriptions
Bit Field Type Reset Description
15-12 VENDOR_SPECIFIC R/W 0h

Vendor Specific Error Signal Enable

N/A
11 RESP R/W 0h

Response Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
10 TUNING R/W 0h

Tuning Error Signal Enable (UHS-I Only)

0h: Masked

1h: Enabled
9 ADMA R/W 0h

ADMA Error Signal Enable

0h: Masked

1h: Enabled
8 AUTO_CMD R/W 0h

Auto CMD Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
7 CURR_LIMIT R/W 0h

Current Limit Error Signal Enable

0h: Masked

1h: Enabled
6 DATA_ENDBIT R/W 0h

Data End Bit Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
5 DATA_CRC R/W 0h

Data CRC Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
4 DATA_TIMEOUT R/W 0h

Data Timeout Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
3 CMD_INDEX R/W 0h

Command Index Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
2 CMD_ENDBIT R/W 0h

Command End Bit Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
1 CMD_CRC R/W 0h

Command CRC Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled
0 CMD_TIMEOUT R/W 0h

Command Timeout Error Signal Enable (SD Mode Only)

0h: Masked

1h: Enabled

6.6.4.25 MMCSD0_AUTOCMD_ERR_STS Register (Offset = 3Ch) [reset = 0h]

MMCSD0_AUTOCMD_ERR_STS is shown in Figure 12-2339 and described in Table 12-4524.

Return to Summary Table.

This register is used to indicate CMD12 response error of Auto CMD12 and CMD23 response error of Auto CMD23.

The Host driver can determine what kind of Auto CMD12/CMD23 errors occur by this register. Auto CMD23 errors are indicated in bit 04-01. This register is valid only when the Auto CMD Error is set.

Table 12-4523 MMCSD0_AUTOCMD_ERR_STS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 003Ch
Figure 12-2339 MMCSD0_AUTOCMD_ERR_STS Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
CMD_NOT_ISSUED RESERVED INDEX ENDBIT CRC TIMEOUT ACMD12_NOT_EXEC
R-0h R-0h R-0h R-0h R-0h R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4524 MMCSD0_AUTOCMD_ERR_STS Register Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R 0h

Reserved
7 CMD_NOT_ISSUED R 0h

Command Not Issued By Auto CMD12 Error

Setting this bit to 1h means CMD_wo_DAT is not executed due to an Auto CMD12 error (D04- D01) in this register.

This bit is set to 0h when Auto CMD Error is generated by Auto CMD23.

0h: No Error

1h: Not Issued
6-5 RESERVED R 0h

Reserved
4 INDEX R 0h

Auto CMD Index Error

Occurs if the Command Index error occurs in response to a command.

0h: No Error

1h: Error
3 ENDBIT R 0h

Auto CMD End Bit Error

Occurs when detecting that the end bit of command response is 0h.

0h: No Error

1h: End Bit Error Generated
2 CRC R 0h

Auto CMD CRC Error

Occurs when detecting a CRC error in the command response.

0h: No Error

1h: CRC Error Generated
1 TIMEOUT R 0h

Auto CMD Timeout Error

Occurs if the no response is returned within 64 SDCLK cycles from the end bit of the command.

If this bit is set to 1h, the other error status bits (D04 - D02) are meaningless.

0h: No Error

1h: Timeout
0 ACMD12_NOT_EXEC R 0h

Auto CMD12 not Executed

If memory multiple block data transfer is not started due to command error, this bit is not set because it is not necessary to issue Auto CMD12. Setting this bit to 1h means the HC cannot issue Auto CMD12 to stop memory multiple block transfer due to some error. If this bit is set to 1h, other error status bits (D04 - D01) are meaningless.

This bit is set to 0h when Auto CMD Error is generated by Auto CMD23.

0h: Executed

1h: Not Executed

Table 12-4525 shows the relation between Auto CMD12 CRC error and Auto CMD12 timeout error.

Table 12-4525 Relation between Auto CMD12 CRC Error and Auto CMD12 Timeout Error
Auto Cmd12 CRC Error Auto CMD12 Timeout Error Kinds of Error
0 0 No Error
0 1 Response Timeout Error
1 0 Response CRC Error
1 1 CMD Line Conflict

The timing of changing Auto CMD12 Error Status can be classified in three scenarios:

1. When the HC is going to issue Auto CMD12:

Set D00 to 1h if Auto CMD12 cannot be issued due to an error in the previous command.

Set D00 to 0h if Auto CMD12 is issued.

2. At the end bit of Auto CMD12 response:

Check received responses by checking the error bits D01, D02, D03, D04.

set to 1h if Error is Detected.

set to 0h if Error is Not Detected.

3. Before reading the Auto CMD12 Error Status bit D07:

Set D07 to 1h if there is a command cannot be issued.

Set D07 to 0h if there is no command to issue.

Timing of generating the Auto CMD12 Error and writing to the MMCSD0_COMMAND register are Asynchronous. Then D07 shall be sampled when driver never writing to the MMCSD0_COMMAND register. So just before reading the MMCSD0_AUTOCMD_ERR_STS register is good timing to set the D07 status bit.

6.6.4.26 MMCSD0_HOST_CONTROL2 Register (Offset = 3Eh) [reset = 0h]

MMCSD0_HOST_CONTROL2 is shown in Figure 12-2340 and described in Table 12-4527.

Return to Summary Table.

This register is used to program UHS Mode Select, Driver Strength Select, Execute Tuning, Sampling Clock Select, Asynchronous Interrupt Enable and Preset Value Enable.

Table 12-4526 MMCSD0_HOST_CONTROL2 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 003Eh
Figure 12-2340 MMCSD0_HOST_CONTROL2 Register
15 14 13 12 11 10 9 8
PRESET_VALUE_ENA ASYNCH_INTR_ENA BIT64_ADDRESSING HOST_VER40_ENA CMD23_ENA ADMA2_LEN_MODE DRIVER_STRENGTH2 UHS2_INTF_ENABLE
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
SAMPLING_CLK_SELECT EXECUTE_TUNING DRIVER_STRENGTH1 V1P8_SIGNAL_ENA UHS_MODE_SELECT
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4527 MMCSD0_HOST_CONTROL2 Register Field Descriptions
Bit Field Type Reset Description
15 PRESET_VALUE_ENA R/W 0h

Preset Value Enable

Host Controller Version 3.00 supports this bit. As the operating SDCLK frequency and I/O driver strength depend on the Host System implementation, it is difficult to determine these parameters in the Standard Host Driver. When the MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA bit is set to automatic. This bit enables the functions defined in the Preset Value registers (MMCSD0_PRESET_VALUE0 - MMCSD0_PRESET_VALUE10).

If this bit is set to 0h, SDCLK Frequency Select, Clock Generator Select in the MMCSD0_CLOCK_CONTROL register and Driver Strength Select in the MMCSD0_HOST_CONTROL2 register are set by Host Driver.

If this bit is set to 1h, SDCLK Frequency Select, Clock Generator Select in the MMCSD0_CLOCK_CONTROL register and Driver Strength Select in the MMCSD0_HOST_CONTROL2 register are set by Host Controller as specified in the Preset Value registers (MMCSD0_PRESET_VALUE0 - MMCSD0_PRESET_VALUE10).

0h: SDCLK and Driver Strength are controlled by Host Driver

1h: Automatic Selection by Preset Value are Enabled
14 ASYNCH_INTR_ENA R/W 0h

Asynchronous Interrupt Enable

This bit can be set to 1h if a card support asynchronous interrupt and the MMCSD0_CAPABILITIES[29] ASYNCH_INTR_SUPPORT bit is set to 1h. Asynchronous interrupt is effective when DAT[1] interrupt is used in 4-bit SD mode . If this bit is set to 1h, the Host Driver can stop the SDCLK during asynchronous interrupt period to save power. During this period, the Host Controller continues to deliver Card Interrupt to the host when it is asserted by the Card.

0h: Disabled

1h: Enabled
13 BIT64_ADDRESSING R/W 0h

64-bit Addressing

This field is effective when the MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 1h.

Host Controller selects either of 32-bit or 64-bit addressing modes to access system memory. Whether 32-bit or 64-bit is determined by OS installed in a host system. Host Driver sets this bit depends on addressing mode of installed OS. Refer to 64-bit System Address Support in the MMCSD0_CAPABILITIES register.

0h: 32-bits Addressing

1h: 64-bits Addressing
12 HOST_VER40_ENA R/W 0h

Host Version 4 Enable

This bit selects either Version 3.00 compatible mode or Version 4.00 mode. In Version 4.00, support of 64-bit System Addressing is modified. All DMAs support 64-bit System Addressing. UHS-II supported Host Driver shall enable this bit.

In Version 4.10, supported 32-bit Block Count for all operations.

Functions of following fields are modified.

SDMA Address

SDMA uses the MMCSD0_ADMA_SYS_ADDRESS register instead of SDMA System Address register (MMCSD0_SDMA_SYS_ADDR_LO/MMCSD0_SDMA_SYS_ADDR_HI)

ADMA2/ADMA3 Selection

ADMA3 is selected by MMCSD0_HOST_CONTROL1[4-3] DMA_SELECT bit.

64-bit ADMA Descriptor Size

128-bit descriptor is used instead of 96-bit descriptor when 64-bit Addressing is set to 1h.

Selection of 32-bit/64-bit System Addressing

Either 32-bit or 64-bit system addressing is selected by 64-bit Addressing bit in this register instead of MMCSD0_HOST_CONTROL1[4-3] DMA_SELECT bit.

32-bit Block Count

SDMA System Address register (MMCSD0_SDMA_SYS_ADDR_LO/MMCSD0_SDMA_SYS_ADDR_HI) is modified to 32-bit Block Count register.

0h: Version 3.00 Compatible Mode

1h: Version 4.Mode
11 CMD23_ENA R/W 0h

CMD23 Enable

In memory card initialization, Host Driver Version 4.10 checks whether card supports CMD23 by checking a bit SCR[33]. If the card supports CMD23 (SCR[33] = 1h), this bit is set to 1h. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 datatransfer. Refer to MMCSD0_TRANSFER_MODE[3-2] AUTO_CMD_ENA bit.
10 ADMA2_LEN_MODE R/W 0h

ADMA2 Length Mode

This bit selects one of ADMA2 Length Modes either 16-bit or 26-bit.

0h: 16-bit Data Length Mode

1h: 26-bit Data Length Mode
9 DRIVER_STRENGTH2 R/W 0h

Driver Strength Select

This is the programmed Drive Strength output and Bit[2] of the sdhccore_drivestrength value.
8 UHS2_INTF_ENABLE R/W 0h

UHS-II Interface Enable

This bit is used to enable UHS-II Interface. Before trying to start UHS-II initialization, this bit shall be set to 1h. Before trying to start SD mode initialization, this bit shall be set to 0h.

This bit is used to enable UHS-II IF Detection, Lane Synchronization and In Dormant State in the MMCSD0_PRESENTSTATE register, and to select clock source of either SD mode or UHS-II mode.

Host Controller shall not leave unused SD 4-bit Interface lines (CLK, CMD and DAT[3:2]) floating in UHS-II mode by using pull-up or driving to low. When DAT[2] is used as interrupt input in UHS-II mode, DAT[2] of Host Controller is set to input and then DAT[2] of SDIO card is set to output to avoid conflict.

0h: 4-bit SD Interface Enabled

1h: UHS-II Interface Enabled
7 SAMPLING_CLK_SELECT R/W 0h

Sampling Clock Select (UHS-I Only)

This bit is set by tuning procedure when the MMCSD0_HOST_CONTROL2[6] EXECUTE_TUNING bit is cleared. Writing 1h to this bit is meaningless and ignored. Setting 1h means that tuning is completed successfully and setting 0 means that tuning is failed. Host Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is cleared by writing 0h. Change of this bit is not allowed while the Host Controller is receiving response or a read data block.

0h: Fixed clock is used to sample data

1h: Tuned clock is used to sample data
6 EXECUTE_TUNING R/W 0h

Execute Tuning (UHS-I Only)

This bit is set to 1h to start tuning procedure and automatically cleared when tuning procedure is completed. The result of tuning is indicated to the MMCSD0_HOST_CONTROL2[7] SAMPLING_CLK_SELECT bit. Tuning procedure is aborted by writing 0h for more detail about tuning procedure.

0h: Not Tuned or Tuning Completed

1h: Execute Tuning
5-4 DRIVER_STRENGTH1 R/W 0h

Driver Strength Select (UHS-I Only)

Host Controller output driver in 1.8 V signaling is selected by this bit. In 3.3 V signaling, this field is not effective. This field can be set depends on Driver Type A, C and D support bits in the MMCSD0_CAPABILITIES register. This bit depends on setting of the MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA bit.

If MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA = 0h, this field is set by Host Driver.

If MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA = 1h, this field is automatically set by a value specified in the one of Preset Value registers (MMCSD0_PRESET_VALUE0 - MMCSD0_PRESET_VALUE10).

0h: Driver Type B is Selected (Default)

1h: Driver Type A is Selected

2h: Driver Type C is Selected

3h: Driver Type D is Selected
3 V1P8_SIGNAL_ENA R/W 0h

1.8 V Signaling Enable (UHS-I Only)

This bit controls voltage regulator for I/O cell. 3.3 V is supplied to the card regardless of signaling voltage.

Setting this bit from 0h to 1h starts changing signal voltage from 3.3 V to 1.8 V.

1.8 V regulator output shall be stable within 5 ms. Host Controller clears this bit if switching to 1.8 V signaling fails.

Clearing this bit from 1h to 0h starts changing signal voltage from 1.8 V to 3.3 V.

3.3 V regulator output shall be stable within 5 ms.

Host Driver can set this bit to 1h when Host Controller supports 1.8 V signaling (one of support bits is set to 1h: SDR50, SDR104 or DDR50 in the MMCSD0_CAPABILITIES register) and the card or device supports UHS-I.

0h: 3.3 V Signaling

1h: 1.8 V Signaling
2-0 UHS_MODE_SELECT R/W 0h

UHS Mode Select (UHS-I Only)

This field is used to select one of UHS-I modes or UHS-II mode. In case of UHS-I mode, this field is effective when the MMCSD0_HOST_CONTROL2[3] V1P8_SIGNAL_ENA bit is set to 1h. In case of UHS-II mode, the MMCSD0_HOST_CONTROL2[3] V1P8_SIGNAL_ENA bit shall be set to 0h. Setting of this field is used to select one of preset values in UHS-I or UHS-II mode.

If the MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA is set to 1h,Host Controller sets SDCLK/RCLK Frequency Select, Clock Generator Select in the MMCSD0_CLOCK_CONTROL register and Driver Strength Select according to Preset Value registers (MMCSD0_PRESET_VALUE0 - MMCSD0_PRESET_VALUE10). In this case, one of preset value registers is selected by this field. Host Driver needs to reset the MMCSD0_CLOCK_CONTROL[2] SD_CLK_ENA bit before changing this field to avoid generating clock glitch. After setting this field, Host Driver sets the MMCSD0_CLOCK_CONTROL[2] SD_CLK_ENA bit again.

0h: SDR12

1h: SDR25

2h: SDR50

3h: SDR104

4h: DDR50

5h: HS400

6h: Reserved

7h: UHS-II

When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt detection at the block gap shall not be used. Read Wait timing is changed for these modes. Refer to the SDIO Specification Version 3.00 for more details.

6.6.4.27 MMCSD0_CAPABILITIES Register (Offset = 40h) [reset = 980004073CECC801h]

MMCSD0_CAPABILITIES is shown in Figure 12-2341 and described in Table 12-4529.

Return to Summary Table.

This register provides the HD with information specific to the HC implementation. The HC may implement these values as fixed or loaded from flash memory during power on initialization.

Table 12-4528 MMCSD0_CAPABILITIES Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0040h
Figure 12-2341 MMCSD0_CAPABILITIES Register
63 62 61 60 59 58 57 56
HS400_SUPPORT RESERVED VDD2_1P8_SUPPORT ADMA3_SUPPORT RESERVED SPI_BLK_MODE SPI_SUPPORT
R-1h R-0h R-1h R-1h R-0h R-0h R-0h
55 54 53 52 51 50 49 48
CLOCK_MULTIPLIER
R-0h
47 46 45 44 43 42 41 40
RETUNING_MODES TUNING_FOR_SDR50 RESERVED RETUNING_TIMER_CNT
R-0h R-0h R-0h R-4h
39 38 37 36 35 34 33 32
RESERVED DRIVERD_SUPPORT DRIVERC_SUPPORT DRIVERA_SUPPORT UHS2_SUPPORT DDR50_SUPPORT SDR104_SUPPORT SDR50_SUPPORT
R-0h R-0h R-0h R-0h R-0h R-1h R-1h R-1h
31 30 29 28 27 26 25 24
SLOT_TYPE ASYNCH_INTR_SUPPORT ADDR_64BIT_SUPPORT_V3 ADDR_64BIT_SUPPORT_V4 VOLT_1P8_SUPPORT VOLT_3P0_SUPPORT VOLT_3P3_SUPPORT
R-0h R-1h R-1h R-1h R-1h R-0h R-0h
23 22 21 20 19 18 17 16
SUSP_RES_SUPPORT SDMA_SUPPORT HIGH_SPEED_SUPPORT RESERVED ADMA2_SUPPORT BUS_8BIT_SUPPORT MAX_BLK_LENGTH
R-1h R-1h R-1h R-0h R-1h R-1h R-0h
15 14 13 12 11 10 9 8
BASE_CLK_FREQ
R-C8h
7 6 5 4 3 2 1 0
TIMEOUT_CLK_UNIT RESERVED TIMEOUT_CLK_FREQ
R-0h R-0h R-1h
LEGEND: R = Read Only; -n = value after reset
Table 12-4529 MMCSD0_CAPABILITIES Register Field Descriptions
Bit Field Type Reset Description
63 HS400_SUPPORT R 1h

HS400 Support

0h: HS400 is Not Supported

1h: HS400 is Supported
62-61 RESERVED R 0h

Reserved
60 VDD2_1P8_SUPPORT R 1h

1.8 V VDD2 Support

This bit indicates that support of VDD2 on Host system.

0h: 1.8 V VDD2 is not supported

1h: 1.8 V VDD2 is supported
59 ADMA3_SUPPORT R 1h

ADMA3 Support

This bit indicates that support of ADMA3 on Host Controller.

0h: ADMA3 is not supported

1h: ADMA3 is supported
58 RESERVED R 0h

Reserved
57 SPI_BLK_MODE R 0h

SPI Block Mode

This bit indicates whether SPI Block Mode is supported or not.

0h: Not Supported

1h: Supported
56 SPI_SUPPORT R 0h

SPI Mode

This bit indicates whether SPI Mode is supported or not.

0h: Not Supported

1h: Supported
55-48 CLOCK_MULTIPLIER R 0h

Clock Multiplier

This field indicates clock multiplier value of programmable clock generator. Refer to the MMCSD0_CLOCK_CONTROL register. Setting 00h means that Host Controller does not support programmable clock generator.

FFh: Clock Multiplier M = 256

----

02h: Clock Multiplier M = 3

01h: Clock Multiplier M = 2

00h: Clock Multiplier is Not Supported
47-46 RETUNING_MODES R 0h

Re-tuning Modes (UHS-I Only)

This field defines the re-tuning capability of a Host Controller and how to manage the data transfer length and a Re-Tuning Timer by the Host Driver.

0h: Mode 1

1h: Mode 2

2h: Mode 3

3h: Reserved

There are two re-tuning timings: Re-Tuning Request and expiration of a Re-Tuning Timer. By receiving either timing, the Host Driver executes the re-tuning procedure just before a next command issue.
45 TUNING_FOR_SDR50 R 0h

Use Tuning for SDR50 (UHS-I Only)

If this bit is set to 1h, this Host Controller requires tuning to operate SDR50 (tuning is always required to operate SDR104).

0h: SDR50 does not require tuning

1h: SDR50 requires tuning

Note: Tuning is required for SDR50 to compensate temperature variation.
44 RESERVED R 0h

Reserved
43-40 RETUNING_TIMER_CNT R 4h

Timer Count for Re-Tuning (UHS-I Only)

This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3.

0h - Get information via other source

1h = 1 seconds

2h = 2 seconds

3h = 4 seconds

4h = 8 seconds

----

n = 2(n-1) seconds

----

Bh = 1024 seconds

Fh - Ch = Reserved
39 RESERVED R 0h

Reserved
38 DRIVERD_SUPPORT R 0h

Driver Type D Support (UHS-I Only)

This bit indicates support of Driver Type D for 1.8 Signaling.

0h: Driver Type D is Not Supported

1h: Driver Type D is Supported
37 DRIVERC_SUPPORT R 0h

Driver Type C Support (UHS-I Only)

This bit indicates support of Driver Type C for 1.8 Signaling.

0h: Driver Type C is Not Supported

1h: Driver Type C is Supported
36 DRIVERA_SUPPORT R 0h

Driver Type A Support (UHS-I Only)

This bit indicates support of Driver Type A for 1.8 Signaling.

0h: Driver Type A is Not Supported

1h: Driver Type A is Supported
35 UHS2_SUPPORT R 0h

UHS-II Support (UHS-II Only)

This bit indicates whether Host Controller supports UHS-II. If this bit is set to 1h, the MMCSD0_CAPABILITIES[60] VDD2_1P8_SUPPORT bit shall be set to 1h (Host System shall support VDD2 power supply).

0h: UHS-II is Not Supported

1h: UHS-II is Supported
34 DDR50_SUPPORT R 1h

DDR50 Support (UHS-I Only)

This bit indicates whether DDR50 is supported or not.

0h: DDR50 is Not Supported

1h: DDR50 is Supported
33 SDR104_SUPPORT R 1h

SDR104 Support (UHS-I Only)

This bit indicates whether SDR104 is supported or not. SDR104 requires tuning.

0h: SDR104 is Not Supported

1h: SDR104 is Supported
32 SDR50_SUPPORT R 1h

SDR50 Support (UHS-I Only)

If SDR104 is supported, this bit shall be set to 1h. Bit 40 indicates whether SDR50 requires tuning or not.

0h: SDR50 is Not Supported

1h: SDR50 is Supported
31-30 SLOT_TYPE R 0h

Slot Type

This field indicates usage of a slot by a specific Host System (a host controller register set is defined per slot). Embedded slot for one device (1h) means that only one non-removable device is connected to a SD bus slot. Shared Bus Slot (2h) can be set if Host Controller supports Shared Bus Control register.

The Standard Host Driver controls only a removable card or one embedded device is connected to a SD bus slot. If a slot is configured for shared bus (2h), the Standard Host Driver does not control embedded devices connected to a shared bus. Shared bus slot is controlled by a specific host driver developed by a Host System.

0h: Removable Card Slot

1h: Embedded Slot for One Device

2h: Shared Bus Slot (SD Mode)

3h: UHS-II Multiple Embedded Devices
29 ASYNCH_INTR_SUPPORT R 1h

Asynchronous Interrupt Support (SD Mode Only)

Refer to SDIO Specification Version 3.00 about asynchronous interrupt.

0h: Asynchronous Interrupt Not Supported

1h: Asynchronous Interrupt Supported
28 ADDR_64BIT_SUPPORT_V3 R 1h

64-bit System Address Support for V3

Meaning of this bit is different depends on Versions. Host Controller Version 3.00 and Version 4.10 use this bit as 64-bit System Address support for V3 mode. Host Controller Version 4.00 uses this bit as 64-bit System Address support for both V3 and V4 modes.

SDMA cannot be used in 64-bit Addressing in Version 3 mode.

If this bit is set to 1h, 64-bit ADMA2 with using 96-bit Descriptor may be enabled as follows:

In case of Host Controller Version 3, 64-bit ADMA2 is enabled by MMCSD0_HOST_CONTROL1[4-3] DMA_SELECT = 3h. In case of Host Controller Version 4, 64-bit ADMA2 for Version 3 is enabled by setting MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 0h and MMCSD0_HOST_CONTROL1[4-3] DMA_SELECT = 3h.

0h: 64-bit System Address for V3 is not Supported

1h: 64-bit System Address for V3 is Supported
27 ADDR_64BIT_SUPPORT_V4 R 1h

64-bit System Address Support for V4

This bit is added from Version 4.10. Setting 1h to this bit indicates that the Host Controller supports 64-bit System Addressing of Version 4 mode .

When this bit is set to 1h, full or a part of 64-bit address should be used to decode Host Controller Registers so that Host Controller Registers can be placed above system memory area. 64-bit address decode of Host Controller Registers is effective regardless of setting to the MMCSD0_HOST_CONTROL2[13] BIT64_ADDRESSING bit.

If this bit is set to 1h, 64-bit DMA Addressing for Version 4 is enabled by setting MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 1h, MMCSD0_HOST_CONTROL2[13] BIT64_ADDRESSING = 1h. SDMA can be used and ADMA2 uses 128-bit Descriptor.

0h: 64-bit System Address for V4 is not Supported

1h: 64-bit System Address for V4 is Supported
26 VOLT_1P8_SUPPORT R 1h

Voltage Support 1.8 V

This bit indicates whether the HC supports 1.8 V.

0h: 1.8 V Not Supported

1h: 1.8 V Supported
25 VOLT_3P0_SUPPORT R 0h

Voltage Support 3.0 V

This bit indicates whether the HC supports 3.0 V.

0h: 3.0 V Not Supported

1h: 3.0 V Supported
24 VOLT_3P3_SUPPORT R 0h

Voltage Support 3.3 V

This bit indicates whether the HC supports 3.3 V.

0h: 3.3 V Not Supported

1h: 3.3 V Supported
23 SUSP_RES_SUPPORT R 1h

Suspend/Resume Support

This bit indicates whether the HC supports Suspend/Resume functionality. If this bit is 0h, the Suspend and Resume mechanism are not supported and the HD shall not issue either Suspend/Resume commands.

0h: Not Supported

1h: Supported
22 SDMA_SUPPORT R 1h

SDMA Support

This bit indicates whether the HC is capable of using DMA to transfer data between system memory and the HC directly.

Version 4.10 Host Controller shall support SDMA if ADMA2 is supported.

0h: SDMA Not Supported

1h: SDMA Supported
21 HIGH_SPEED_SUPPORT R 1h

High Speed Support

This bit indicates whether the HC and the Host System support High Speed mode and they can supply SD Clock frequency from 25 MHz to 50 MHz (for SD)/20 MHz to 52 MHz (for MMC).

0h: High Speed Not Supported

1h: High Speed Supported
20 RESERVED R 0h

Reserved
19 ADMA2_SUPPORT R 1h

ADMA2 Support

0h: ADMA2 Not support

1h: ADMA2 support
18 BUS_8BIT_SUPPORT R 1h

8-bit Support for Embedded Device (Embedded)

This bit indicates whether the Host Controller is capable of using 8-bit bus width mode. This bit is not effective when the MMCSD0_CAPABILITIES[31-30] SLOT_TYPE bit field is set to 2h.

0h: 8-bit Bus Width Not Supported

1h: 8-bit Bus Width Supported
17-16 MAX_BLK_LENGTH R 0h

Max Block Length

This value indicates the maximum block size that the HD can read and write to the buffer in the HC. The buffer shall transfer this block size without wait cycles. Three sizes can be defined as indicated below.

0h: 512 byte

1h: 1024 byte

2h: 2048 byte

3h: 4096 byte
15-8 BASE_CLK_FREQ R C8h

Base Clock Frequency for SD Clock

(1) 6-bit Base Clock Frequency:

This mode is supported by the Host Controller Version 1.00 and 2.00. Upper 2-bit is not effective and always 0. Unit values are 1 MHz. The supported clock range is 10 MHz to 63 MHz.

11xx xxxxb: Not Supported

0011 1111b: 63 MHz

0000 0010b: 2 MHz

0000 0001b: 1 MHz

0000 0000b: Get Information via another method

(2) 8-bit Base Clock Frequency:

This mode is supported by the Host Controller Version 3.00. Unit values are 1 MHz. The supported clock range is 10 MHz to 255 MHz.

FFh: 255 MHz

02h: 2 MHz

01h: 1 MHz

00h: Get Information via another method

If the real frequency is 16.5 MHz, the lager value shall be set 0001 0001b (17 MHz) because the Host Driver use this value to calculate the clock divider value (refer to the MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field) and it shall not exceed upper limit of the SD Clock frequency. If these bits are all 0, the Host System has to get information via another method.
7 TIMEOUT_CLK_UNIT R 0h

Timeout Clock Unit

This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCSD0_ERROR_INTR_STS[4] DATA_TIMEOUT).

0h: KHz

1h: MHz
6 RESERVED R 0h

Reserved
5-0 TIMEOUT_CLK_FREQ R 1h

Timeout Clock Frequency

This bit shows the base clock frequency used to detect Data Timeout Error (MMCSD0_ERROR_INTR_STS[4] DATA_TIMEOUT).

0h: Get Information via another method

Not 0h: 1 KHz to 63 KHz/1 MHz to 63 MHz

Table 12-4530 shows the 64-bit System Address Support depends on Versions.

Table 12-4530 64-bit System Address Support depends on Versions
Host Controller Version 3.00 Version 4.00 Version 4.10
D28 (from Version 2.00) for V3 for V3 and V4 for V3
D27 (from Version 4.10) D27 (from Version 4.10) Not Defined for V4
Register Decode 32-bit or 64-bit (up to implementation) 32-bit or 64-bit (up to implementation) If D27 = 1h, 64-bit
SDMA Not supported Supported when MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 1h Supported when MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 1h
ADMA2 (96-bit Descriptor) DMA Select = 3h Selected by MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 0h Selected by MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 0h
ADMA2 (128-bit Descriptor) Not Defined Selected by MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 1h Selected by MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA = 1h

As the specification of 64-bit System Address Support has been changed, capabilities of 64-bit functions are different depends on versions.

Definition of D28 is different depends on Versions. 96-bit Descriptor was defined by Version 2 but notation V3 is used including V2. Version 4.10 divides 64-bit System Address Support into V3 mode (D28) and V4 mode (D27) so that V3 mode can be optional. Migrate to V4 is recommended. From Host Controller Version 4.00, either V3 mode or V4 mode is selected by Host Version 4 Enable in the Host Control 2 register. V3 mode can be used if 64-bit System Address Support for V3 is set to 1h. V4 mode can be used if 64-bit System Address Support for V4 is set to 1h.

Prior to Version 4.10, address length of Host Controller registers decoding is not defined and whether 32-bit or 64-bit address is used to decode Host Controller registers is up to implementation. If Host Controller decodes 32-bit system address in default, the Host Controller Registers shall be placed in 32-bit addressing space.

When D27 = 1h, Host Controller Version 4.10 or later should use full or a part of 64-bit address to decode Host Controller Registers so that Host Controller Registers can be placed above system memory area. 64-bit address decode of Host Controller Registers is effective regardless of setting to the MMCSD0_HOST_CONTROL2[13] BIT64_ADDRESSING bit. How to decode register also should follow a system bus specification or a mother board specification.

From Version 4.00, 64-bit System Addressing of DMA is enabled by setting to the MMCSD0_HOST_CONTROL2[13] BIT64_ADDRESSING bit. 64-bit SDMA is not supported in V3 mode and is supported in V4 mode. There are two Descriptor types for ADMA2 96-bit (V3) or 128-bit (V4). Support of 96-bit Descriptor is optional for Host Controller Version 4.10. If D28 = 0h, 96-bit Descriptor is not supported.

Note: The Host System shall support at least one of these voltages above. The HD sets the MMCSD0_POWER_CONTROL[3:1] SD_BUS_VOLTAGE bit field according to these support bits. If multiple voltages are supported, select the usable lower voltage by comparing the OCR value from the card.

These registers indicate maximum current capability for each voltage. The value is meaningful if Voltage Support is set in the MMCSD0_CAPABILITIES register.

Table 12-4531 describes the re-tuning modes.

Table 12-4531 64-bit System Address Support depends on Versions
Bit47-46 Re-Tuning Mode Data length Timer Modes
0h Mode1 4 MB (Max.) Always enabled
1h Mode2 4 MB (Max.) Stop during data transfer
2h Reserved Reserved Reserved
3h Reserved Reserved Reserved

There are two re-tuning timings: Re-Tuning Request and expiration of a Re-Tuning Timer. By receiving either timing, the Host Driver executes the re-tuning procedure just before a next command issue.

Data length per a read/write command is restricted by whether Host Controller generates Re-Tuning Request during data transfer so that re-tuning procedures can be inserted during data transfers.

6.6.4.28 MMCSD0_MAX_CURRENT_CAP Register (Offset = 48h) [reset = 0h]

MMCSD0_MAX_CURRENT_CAP is shown in Figure 12-2342 and described in Table 12-4533.

Return to Summary Table.

This register indicates maximum current capability for each voltage.

Table 12-4532 MMCSD0_MAX_CURRENT_CAP Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0048h
Figure 12-2342 MMCSD0_MAX_CURRENT_CAP Register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
RESERVED
R-0h
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED VDD2_1P8V
R-0h R-0h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED VDD1_1P8V
R-0h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VDD1_3P0V VDD1_3P3V
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4533 MMCSD0_MAX_CURRENT_CAP Register Field Descriptions
Bit Field Type Reset Description
63-40 RESERVED R 0h

Reserved
39-32 VDD2_1P8V R 0h

Maximum Current for 1.8 V VDD2
31-24 RESERVED R 0h

Reserved
23-16 VDD1_1P8V R 0h

Maximum Current for 1.8 V VDD1
15-8 VDD1_3P0V R 0h

Maximum Current for 3.0 V VDD1
7-0 VDD1_3P3V R 0h

Maximum Current for 3.3 V VDD1

Table 12-4534 describes the maximum current value.

Table 12-4534 Maximum Current Value Definition
Register Value Current Value
0 Get Information via another method
1 4 mA
2 8 mA
3 12 mA
------------------- -------------------
255 1020 mA

6.6.4.29 MMCSD0_FORCE_EVNT_ACMD_ERR_STS Register (Offset = 50h) [reset = 0h]

MMCSD0_FORCE_EVNT_ACMD_ERR_STS is shown in Figure 12-2343 and described in Table 12-4536.

Return to Summary Table.

This register is not physically implemented, rather it is an address where the MMCSD0_AUTOCMD_ERR_STS register can be written.

Writing 1h: set each bit of the MMCSD0_AUTOCMD_ERR_STS register

Writing 0h: no effect

By setting a bit in this register, the correspondent bit is set in the MMCSD0_ERROR_INTR_ST register. In order to generate interrupt signal, the correspondent bit shall be set in the MMCSD0_ERROR_INTR_STS_ENA register and MMCSD0_ERROR_INTR_SIG_ENA register.

Table 12-4535 MMCSD0_FORCE_EVNT_ACMD_ERR_STS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0050h
Figure 12-2343 MMCSD0_FORCE_EVNT_ACMD_ERR_STS Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
CMD_NOT_ISS RESERVED RESP INDEX ENDBIT CRC TIMEOUT ACMD_NOT_EXEC
W-0h R-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R = Read Only; W = Write Only; -n = value after reset
Table 12-4536 MMCSD0_FORCE_EVNT_ACMD_ERR_STS Register Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R 0h

Reserved
7 CMD_NOT_ISS W 0h

Force Event for Command Not Issued by AUTO CMD12 Error

0h: Not Affected

1h: Command Not Issued By Auto CMD12 Error Status is set
6 RESERVED R 0h

Reserved
5 RESP W 0h

Force Event for AUTO CMD Response Error

0h: Not Affected

1h: Auto CMD Response Error Status is set
4 INDEX W 0h

Force Event for AUTO CMD Index Error

0h: Not Affected

1h: Auto CMD Index Error Status is set
3 ENDBIT W 0h

Force Event for AUTO CMD End Bit Error

0h: Not Affected

1h: Auto CMD End bit Error Status is set
2 CRC W 0h

Force Event for AUTO CMD Timeout Error

0h: Not Affected

1h: Auto CMD CRC Error Status is set
1 TIMEOUT W 0h

Force Event for AUTO CMD Timeout Error

0h: Not Affected

1h: Auto CMD Timeout Error Status is set
0 ACMD_NOT_EXEC W 0h

Force Event for AUTO CMD12 Not Executed

0h: Not Affected

1h: Auto CMD12 Not Executed Status is set

6.6.4.30 MMCSD0_FORCE_EVNT_ERR_INT_STS Register (Offset = 52h) [reset = 0h]

MMCSD0_FORCE_EVNT_ERR_INT_STS is shown in Figure 12-2344 and described in Table 12-4538.

Return to Summary Table.

This register is not physically implemented, rather it is an address where the MMCSD0_ERROR_INTR_STS register can be written.

The MMCSD0_FORCE_EVNT_ERR_INT_STS register is not a physically implemented register. Rather, it is an address at which the MMCSD0_ERROR_INTR_STS register can be written. The effect of a write to this address will be reflected in the MMCSD0_ERROR_INTR_STS register if the corresponding bit of the MMCSD0_ERROR_INTR_STS_ENA register is set.

Writing 1h: set each bit of the MMCSD0_ERROR_INTR_STS register

Writing 0h: no effect

Table 12-4537 MMCSD0_FORCE_EVNT_ERR_INT_STS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0052h
Figure 12-2344 MMCSD0_FORCE_EVNT_ERR_INT_STS Register
15 14 13 12 11 10 9 8
VEND_SPEC RESP TUNING ADMA AUTO_CMD
W-0h W-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
CURR_LIM DAT_ENDBIT DAT_CRC DAT_TIMEOUT CMD_INDEX CMD_ENDBIT CMD_CRC CMD_TIMEOUT
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: W = Write Only; -n = value after reset
Table 12-4538 MMCSD0_FORCE_EVNT_ERR_INT_STS Register Field Descriptions
Bit Field Type Reset Description
15-12 VEND_SPEC W 0h

N/A
11 RESP W 0h

Force Event for Response Error

0h: Not Affected

1h: Response Error Status is set
10 TUNING W 0h

Force Event for Tuning Error

0h: Not Affected

1h: Tuning Error Status is set
9 ADMA W 0h

Force Event for ADMA Error

0h: Not Affected

1h: ADMA Error Status is set
8 AUTO_CMD W 0h

Force Event for Auto CMD Error

0h: Not Affected

1h: Auto CMD Error Status is set
7 CURR_LIM W 0h

Force Event for Current Limit Error

0h: Not Affected

1h: Current Limit Error Status is set
6 DAT_ENDBIT W 0h

Force Event for Data End Bit Error

0h: Not Affected

1h: Data End Bit Error Status is set
5 DAT_CRC W 0h

Force Event for Data CRC Error

0h: Not Affected

1h: CRC Error Status is set
4 DAT_TIMEOUT W 0h

Force Event for Data Timeout Error

0h: Not Affected

1h: Timeout Error Status is set
3 CMD_INDEX W 0h

Force Event for Command Index Error

0h: Not Affected

1h: Command Index Error Status is set
2 CMD_ENDBIT W 0h

Force Event for Command End Bit Error

0h: Not Affected

1h: Command End Bit Error Status is set
1 CMD_CRC W 0h

Force Event for Command CRC Error

0h: Not Affected

1h: Command CRC Error Status is set
0 CMD_TIMEOUT W 0h

Force Event for CMD Timeout Error

0h: Not Affected

1h: Command Timeout Error Status is set

6.6.4.31 MMCSD0_ADMA_ERR_STATUS Register (Offset = 54h) [reset = 0h]

MMCSD0_ADMA_ERR_STATUS is shown in Figure 12-2345 and described in Table 12-4540.

Return to Summary Table.

When the ADMA Error interrupt occur, this register holds the ADMA State (MMCSD0_ADMA_ERR_STATUS[1-0] ADMA_ERR_STATE) and the MMCSD0_ADMA_SYS_ADDRESS register holds address around the error descriptor.

Table 12-4539 MMCSD0_ADMA_ERR_STATUS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0054h
Figure 12-2345 MMCSD0_ADMA_ERR_STATUS Register
7 6 5 4 3 2 1 0
RESERVED ADMA_LENGTH_ERR ADMA_ERR_STATE
R-0h R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4540 MMCSD0_ADMA_ERR_STATUS Register Field Descriptions
Bit Field Type Reset Description
7-3 RESERVED R 0h

Reserved
2 ADMA_LENGTH_ERR R 0h

ADMA Length Mismatch Error

This error occurs in the following 2 cases.

While the MMCSD0_TRANSFER_MODE[1] BLK_CNT_ENA bit being set, the total data length specified by the Descriptor table is different from that specified by the Block Count and Block Length. Total data length can not be divided by the block length.

0h: No Error

1h: Error
1-0 ADMA_ERR_STATE R 0h

ADMA Error State

This field indicates the state of ADMA when error is occurred during ADMA data transfer. This field never indicates "2h" because ADMA never stops in this state.

D01 - D00: ADMA Error State when error occurred

Contents of SYS_SDR register

0h: ST_STOP (Stop DMA) Points to next of the error descriptor

1h: ST_FDS (Fetch Descriptor) Points to the error descriptor

2h: Never set this state (Not used)

3h: ST_TFR (Transfer Data) Points to the next of the error descriptor

6.6.4.32 MMCSD0_ADMA_SYS_ADDRESS Register (Offset = 58h) [reset = Xh]

MMCSD0_ADMA_SYS_ADDRESS is shown in Figure 12-2346 and described in Table 12-4542.

Return to Summary Table.

This register contains the physical address used for ADMA data transfer.

Table 12-4541 MMCSD0_ADMA_SYS_ADDRESS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0058h
Figure 12-2346 MMCSD0_ADMA_SYS_ADDRESS Register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
ADMA_ADDR
R/W-Xh
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADMA_ADDR
R/W-Xh
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4542 MMCSD0_ADMA_SYS_ADDRESS Register Field Descriptions
Bit Field Type Reset Description
63-0 ADMA_ADDR R/W Xh

ADMA System Address

The 32-bit addressing Host Driver uses lower 32-bit of this register (upper 32-bit should be set to 0h) and shall program Descriptor Table on 32-bit boundary and set 32-bit boundary address to this register. DMA2/3 ignores lower 2-bit of this register and assumes it to be 0h.

DMA in 64-bit addressing. The 64-bit addressing Host Driver uses all bits of this register and shall program Descriptor Table on 64-bit boundary and set 64-bit boundary address to this register. DMA2/3 ignores lower 3-bit of this register andassumes it to be 0h.

SDMA

If the MMCSD0_HOST_CONTROL2[12] HOST_VER40_ENA bit is set to 1h, SDMA use this register to indicate System Address of data location instead of using SDMA System Address register (MMCSD0_SDMA_SYS_ADDR_LO/MMCSD0_SDMA_SYS_ADDR_HI). SDMA can be used in 32-bit and 64-bit addressing in Version 4.00.

ADMA2

This register holds byte address of executing command of the Descriptor table. At the start of ADMA2, the Host Driver shall set start address of the Descriptor table. The ADMA increments this register address, which points to next line, when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this register shall hold the Descriptor address depending on the ADMA state.

ADMA3

This register is set by ADMA3. Host Driver is not necessary to set this register. The ADMA3 increments address of this register, which points to next line, when every time fetching a Descriptor line. When Error Interrupt is generated, this register shall hold the Descriptor address depending on the ADMA state.

Register Value - 00000000_xxxxxxxxh

Addressing Mode - 32-bit System Address

Register Value - xxxxxxxx_xxxxxxxxh

Addressing Mode - 64-bit System Address

6.6.4.33 MMCSD0_PRESET_VALUE0 Register (Offset = 60h) [reset = 100h]

MMCSD0_PRESET_VALUE0 is shown in Figure 12-2347 and described in Table 12-4545.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

When the MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA bit is set to 1h, SDCLK/RCLK Frequency Select and Clock Generator Select in the MMCSD0_CLOCK_CONTROL register, and Driver Strength Select in the MMCSD0_HOST_CONTROL2 register are automatically set based on the Selected Bus Speed Mode (see Table 12-4543). This means the Host Driver needs not set these fields when preset is enabled.

Before starting the initialization sequence, the Host Driver needs to set a clock preset value to SDCLK/RCLK Frequency Select in the MMCSD0_CLOCK_CONTROL register. The MMCSD0_HOST_CONTROL2[15] PRESET_VALUE_ENA bit can be set after initialization completed.

Table 12-4543 shows the conditions to select one of preset value registers.

Table 12-4543 Preset Value Register Select Condition
Selected Bus Speed Mode 1.8 V Signaling Enable (Host Control 2) High Speed Enable (Host Control 1) UHS-1 Mode Selection (Host Control 2)
Default Speed 0 0 don't care
High Speed 0 1 don't care
SDR12 1 don't care 0h
SDR25 1 don't care 1h
SDR50 1 don't care 2h
SDR104 1 don't care 3h
DDR50 1 don't care 4h
HS400 1 don't care 5h
Reserved Not determined don't care 6h
UHS-II 0 don't care 7h
Table 12-4544 MMCSD0_PRESET_VALUE0 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0060h
Figure 12-2347 MMCSD0_PRESET_VALUE0 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-100h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-100h
LEGEND: R = Read Only; -n = value after reset
Table 12-4545 MMCSD0_PRESET_VALUE0 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 100h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

6.6.4.34 MMCSD0_PRESET_VALUE1 Register (Offset = 62h) [reset = 4h]

MMCSD0_PRESET_VALUE1 is shown in Figure 12-2348 and described in Table 12-4547.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 12-4546 MMCSD0_PRESET_VALUE1 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0062h
Figure 12-2348 MMCSD0_PRESET_VALUE1 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-4h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-4h
LEGEND: R = Read Only; -n = value after reset
Table 12-4547 MMCSD0_PRESET_VALUE1 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 4h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

6.6.4.35 MMCSD0_PRESET_VALUE2 Register (Offset = 64h) [reset = 2h]

MMCSD0_PRESET_VALUE2 is shown in Figure 12-2349 and described in Table 12-4549.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 12-4548 MMCSD0_PRESET_VALUE2 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0064h
Figure 12-2349 MMCSD0_PRESET_VALUE2 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-2h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-2h
LEGEND: R = Read Only; -n = value after reset
Table 12-4549 MMCSD0_PRESET_VALUE2 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 2h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

6.6.4.36 MMCSD0_PRESET_VALUE3 Register (Offset = 66h) [reset = 4h]

MMCSD0_PRESET_VALUE3 is shown in Figure 12-2350 and described in Table 12-4551.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 12-4550 MMCSD0_PRESET_VALUE3 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0066h
Figure 12-2350 MMCSD0_PRESET_VALUE3 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-4h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-4h
LEGEND: R = Read Only; -n = value after reset
Table 12-4551 MMCSD0_PRESET_VALUE3 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 4h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

6.6.4.37 MMCSD0_PRESET_VALUE4 Register (Offset = 68h) [reset = 2h]

MMCSD0_PRESET_VALUE4 is shown in Figure 12-2351 and described in Table 12-4553.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 12-4552 MMCSD0_PRESET_VALUE4 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0068h
Figure 12-2351 MMCSD0_PRESET_VALUE4 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-2h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-2h
LEGEND: R = Read Only; -n = value after reset
Table 12-4553 MMCSD0_PRESET_VALUE4 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 2h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

6.6.4.38 MMCSD0_PRESET_VALUE5 Register (Offset = 6Ah) [reset = 1h]

MMCSD0_PRESET_VALUE5 is shown in Figure 12-2352 and described in Table 12-4555.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 12-4554 MMCSD0_PRESET_VALUE5 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 006Ah
Figure 12-2352 MMCSD0_PRESET_VALUE5 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-1h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-1h
LEGEND: R = Read Only; -n = value after reset
Table 12-4555 MMCSD0_PRESET_VALUE5 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 1h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

6.6.4.39 MMCSD0_PRESET_VALUE6 Register (Offset = 6Ch) [reset = 0h]

MMCSD0_PRESET_VALUE6 is shown in Figure 12-2353 and described in Table 12-4557.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 12-4556 MMCSD0_PRESET_VALUE6 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 006Ch
Figure 12-2353 MMCSD0_PRESET_VALUE6 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4557 MMCSD0_PRESET_VALUE6 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 0h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

6.6.4.40 MMCSD0_PRESET_VALUE7 Register (Offset = 6Eh) [reset = 2h]

MMCSD0_PRESET_VALUE7 is shown in Figure 12-2354 and described in Table 12-4559.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 12-4558 MMCSD0_PRESET_VALUE7 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 006Eh
Figure 12-2354 MMCSD0_PRESET_VALUE7 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-2h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-2h
LEGEND: R = Read Only; -n = value after reset
Table 12-4559 MMCSD0_PRESET_VALUE7 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 2h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

6.6.4.41 MMCSD0_PRESET_VALUE8 Register (Offset = 72h) [reset = 1h]

MMCSD0_PRESET_VALUE8 is shown in Figure 12-2355 and described in Table 12-4561.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 12-4560 MMCSD0_PRESET_VALUE8 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0072h
Figure 12-2355 MMCSD0_PRESET_VALUE8 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-1h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-1h
LEGEND: R = Read Only; -n = value after reset
Table 12-4561 MMCSD0_PRESET_VALUE8 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 1h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

6.6.4.42 MMCSD0_PRESET_VALUE10 Register (Offset = 74h) [reset = 0h]

MMCSD0_PRESET_VALUE10 is shown in Figure 12-2356 and described in Table 12-4563.

Return to Summary Table.

This register is used to read the SDCLK Frequency Select Value, Clock Generator Select Value, Driver Strength Select Value.

Table 12-4562 MMCSD0_PRESET_VALUE10 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0074h
Figure 12-2356 MMCSD0_PRESET_VALUE10 Register
15 14 13 12 11 10 9 8
DRIVER_STRENGTH_SEL RESERVED CLOCK_GENSEL SDCLK_FRQSEL
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
SDCLK_FRQSEL
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4563 MMCSD0_PRESET_VALUE10 Register Field Descriptions
Bit Field Type Reset Description
15-14 DRIVER_STRENGTH_SEL R 0h

Driver Strength Select Value (UHS-I Only)

Driver Strength is supported by 1.8 V signaling bus speed modes. This field is meaningless for 3.3 V signaling.

0h: Driver Type D is Selected

1h: Driver Type C is Selected

2h: Driver Type A is Selected

3h: Driver Type B is Selected
13-11 RESERVED R 0h

Reserved
10 CLOCK_GENSEL R 0h

Clock Generator Select Value

This bit is effective when Host Controller supports programmable clock generator.

0h: Host Controller Version 2.00 Compatible Clock Generator

1h: Programmable Clock Generator
9-0 SDCLK_FRQSEL R 0h

SDCLK Frequency Select Value

10-bit preset value to set the MMCSD0_CLOCK_CONTROL[15-8] SDCLK_FRQSEL bit field is described by a host system.

6.6.4.43 MMCSD0_ADMA3_DESC_ADDRESS Register (Offset = 78h) [reset = Xh]

MMCSD0_ADMA3_DESC_ADDRESS is shown in Figure 12-2357 and described in Table 12-4565.

Return to Summary Table.

The start address of Integrated DMA Descriptor is set to this register.

Table 12-4564 MMCSD0_ADMA3_DESC_ADDRESS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0078h
Figure 12-2357 MMCSD0_ADMA3_DESC_ADDRESS Register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
INTG_DESC_ADDR
R/W-Xh
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTG_DESC_ADDR
R/W-Xh
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4565 MMCSD0_ADMA3_DESC_ADDRESS Register Field Descriptions
Bit Field Type Reset Description
63-0 INTG_DESC_ADDR R/W Xh

ADMA3 Integrated Descriptor Address

The start address of Integrated DMA Descriptor is set to this register. Writing to a specific address starts ADMA3 depends on 32-bit/64-bit address-ing. The ADMA3 fetches one Descriptor Address and increments this field to indicate the next Descriptor address.

The 32-bit addressing Host Driver uses lower 32-bit of this register and shall program Descriptor Table on 32-bit boundary. ADMA3 ignores lower 2-bit of this register and assumes it to be 0h. Writing to 07Bh starts ADMA3 data transfer.

The 64-bit addressing Host Driver uses all 64-bit of this register and shall program Descriptor Table on 64-bit boundary. ADMA3 ignores lower 3-bit of this register and assumes it to be 0h. Writing to 07Fh starts ADMA3 data transfer.

Register Value - 00000000_xxxxxxxxh Addressing Mode - 32-bit System Address

Register Value - xxxxxxxx_xxxxxxxxh Addressing Mode - 64-bit System Address

6.6.4.44 MMCSD0_UHS2_BLOCK_SIZE Register (Offset = 80h) [reset = 0h]

MMCSD0_UHS2_BLOCK_SIZE is shown in Figure 12-2358 and described in Table 12-4567.

Return to Summary Table.

This register is used to configure the number of bytes in a data block.

Table 12-4566 MMCSD0_UHS2_BLOCK_SIZE Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0080h
Figure 12-2358 MMCSD0_UHS2_BLOCK_SIZE Register
15 14 13 12 11 10 9 8
RESERVED SDMA_BUF_BOUNDARY XFER_BLK_SIZE
R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
XFER_BLK_SIZE
R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4567 MMCSD0_UHS2_BLOCK_SIZE Register Field Descriptions
Bit Field Type Reset Description
15 RESERVED R 0h

Reserved
14-12 SDMA_BUF_BOUNDARY R/W 0h

UHS-II SDMA Buffer Boundary (SDMA only)

When system memory is managed by paging, SDMA data transfer is performed in unit of paging. A page size of system memory management is set to this field.

Host Controller generates the DMA Interrupt at the page boundary and requests the Host Driver to update the MMCSD0_ADMA_SYS_ADDRESS register. SDMA waits until the MMCSD0_ADMA_SYS_ADDRESS register is written.

At the end of transfer, the Host Controller may issue or may not issue DMA Interrupt. In particular, DMA Interrupt shall not be issued after Transfer Complete Interrupt is issued (see MMCSD0_NORMAL_INTR_STS[1] XFER_COMPLETE).

These bits shall be supported when the MMCSD0_CAPABILITIES[22] SDMA_SUPPORT bit is set to 1h and this function is active when the MMCSD0_UHS2_XFER_MODE[0] DMA_ENA bit register is set to 1h. ADMA does not use this field.

0h: 4K bytes (Detects A11 carry out)

1h: 8K bytes (Detects A12 carry out)

2h: 16K Bytes (Detects A13 carry out)

3h: 32K Bytes (Detects A14 carry out)

4h: 64K bytes (Detects A15 carry out)

5h: 128K Bytes (Detects A16 carry out)

6h: 256K Bytes (Detects A17 carry out)

7h: 512K Bytes (Detects A18 carry out)
11-0 XFER_BLK_SIZE R/W 0h

UHS-II Block Size

This bit field specifies the block size of data packet. SD Memory Card uses a fixed block size of 512 bytes.

Variable block size may be used for SDIO. The maximum value is 2048 Bytes because CRC16 covers up to 2048 bytes. This bit field is effective when the MMCSD0_UHS2_COMMAND[5] DATA_PRESENT bit is set to 1h.

0000h - No data transfer

0001h - 1 Byte

0002h - 2 Bytes

0003h - 3 Bytes

... ...

01FFh - 511 Bytes

0200h - 512 Bytes

... ...

0800h - 2048 Bytes

6.6.4.45 MMCSD0_UHS2_BLOCK_COUNT Register (Offset = 84h) [reset = 0h]

MMCSD0_UHS2_BLOCK_COUNT is shown in Figure 12-2359 and described in Table 12-4569.

Return to Summary Table.

This register is used to configure the number of data blocks.

Table 12-4568 MMCSD0_UHS2_BLOCK_COUNT Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0084h
Figure 12-2359 MMCSD0_UHS2_BLOCK_COUNT Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XFER_BLK_COUNT
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4569 MMCSD0_UHS2_BLOCK_COUNT Register Field Descriptions
Bit Field Type Reset Description
31-0 XFER_BLK_COUNT R/W 0h

UHS-II Block Count

This register is effective when the MMCSD0_UHS2_COMMAND[5] DATA_PRESENT bit is set to 1h and is enabled when the MMCSD0_UHS2_XFER_MODE[1] BLK_CNT_ENA bit is set to 1h and the MMCSD0_UHS2_XFER_MODE[5] BYTE_MODE bit is set to 0h. Data transfer stops when the count reaches zero. Setting the block count to 0h results in no data blocks is transferred.

This register should be accessed only when no transaction is executing (after transactions are stopped). During data transfer, read operations on this register may return an invalid value and write operations are ignored.

00000000h: Stop Count

00000001h: 1 block

00000002h: 2 blocks

... ...

FFFFFFFFh: 4G blocks - 1

6.6.4.46 MMCSD0_UHS2_COMMAND_PKT_0 to MMCSD0_UHS2_COMMAND_PKT_19 Register (Offset = 88h to 9Bh) [reset = 0h]

MMCSD0_UHS2_COMMAND_PKT_0 to MMCSD0_UHS2_COMMAND_PKT_19 is shown in Figure 12-2360 and described in Table 12-4572.

Return to Summary Table.

UHS-II Command Packet image is set to this register. The maximum length is 20 bytes (see Table 12-4570). The command length varies depends on a Command Packet type. The length is specified by the MMCSD0_UHS2_COMMAND register.

Table 12-4570 UHS-II Command Packet Register
Offset Preset Value Registers
088h Command Packet Byte 0
089h Command Packet Byte 1
08Ah Command Packet Byte 2
.... ....
09Bh Command Packet Byte 19
Table 12-4571 MMCSD0_UHS2_COMMAND_PKT_0 to MMCSD0_UHS2_COMMAND_PKT_19 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0088h to 04F8 009Bh
Figure 12-2360 MMCSD0_UHS2_COMMAND_PKT_0 to MMCSD0_UHS2_COMMAND_PKT_19 Register
7 6 5 4 3 2 1 0
CMD_PKT_BYTE
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4572 MMCSD0_UHS2_COMMAND_PKT_0 to MMCSD0_UHS2_COMMAND_PKT_19 Register Field Descriptions
Bit Field Type Reset Description
7-0 CMD_PKT_BYTE R/W 0h

Command Packet Byte

UHS-II Command Packet image is set to this register. The command length varies depends on a Command Packet type.

6.6.4.47 MMCSD0_UHS2_XFER_MODE Register (Offset = 9Ch) [reset = 0h]

MMCSD0_UHS2_XFER_MODE is shown in Figure 12-2361 and described in Table 12-4574.

Return to Summary Table.

This register is used to control the operations of data transfers.

On issuing a Command Packet, a Command Packet image is set to UHS-II Command Packet register (see MMCSD0_UHS2_COMMAND_PKT_0 - MMCSD0_UHS2_COMMAND_PKT_19) but Host Controller does not analyze the setting of UHS-II Command Packet register. Instead, Host Controller refers setting of this register to issue a Command Packet to make the control easy. Setting of these registers shall be correspondent.

Table 12-4573 MMCSD0_UHS2_XFER_MODE Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 009Ch
Figure 12-2361 MMCSD0_UHS2_XFER_MODE Register
15 14 13 12 11 10 9 8
DUPLEX_SELECT EBSY_WAIT RESERVED RESP_INTR_DIS
R/W-0h R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
RESP_ERR_CHK_ENA RESP_TYPE BYTE_MODE DATA_XFER_DIR RESERVED BLK_CNT_ENA DMA_ENA
R/W-0h R/W-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4574 MMCSD0_UHS2_XFER_MODE Register Field Descriptions
Bit Field Type Reset Description
15 DUPLEX_SELECT R/W 0h

Half/Full Select

Use of 2 lane half duplex mode is determined by Host Driver.

0h: Full Duplex Mode

1h: 2 Lane Half Duplex Mode
14 EBSY_WAIT R/W 0h

EBSY Wait

This bit is set when issuing a command which is accompanied by EBSY packet to indicate end of command execution. Busy is expected for CCMD with R1b/R5b type and DCMD with data transfer.

If this bit is set to 1h, Host Controller waits receiving of EBSY packet and on receiving EBSY packet, the MMCSD0_NORMAL_INTR_STS[1] XFER_COMPLETE bit is set to 1h to indicate end of busy. If an error is indicated in EBSY packet (for example: Memory Error), the MMCSD0_UHS2_ERR_INTR_STS[8] EBSY bit is set to 1h.

Setting of the MMCSD0_UHS2_ERR_INTR_STS[8] EBSY bit also sets the MMCSD0_NORMAL_INTR_STS[15] ERROR_INTR bit to 1h. The MMCSD0_NORMAL_INTR_STS[15] ERROR_INTR and MMCSD0_NORMAL_INTR_STS[1] XFER_COMPLETE bits shall be set together.

0h: Issue a command without busy

1h: Wait EBSY
13-9 RESERVED R 0h

Reserved
8 RESP_INTR_DIS R/W 0h

Response Interrupt Disable

Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.

If Host Driver checks response error, sets this bit to 0h and waits the MMCSD0_NORMAL_INTR_STS[0] CMD_COMPLETE bit and then check the response register (MMCSD0_RESPONSE_0 - MMCSD0_RESPONSE_7). If Host Controller checks response error, sets this bit to 1h and sets the MMCSD0_UHS2_XFER_MODE[7] RESP_ERR_CHK_ENA bit to 1h. The MMCSD0_NORMAL_INTR_STS[0] CMD_COMPLETE bit is disabled by this bit regardless of MMCSD0_NORMAL_INTR_SIG_ENA[0] CMD_COMPLETE bit.

0h: Response Interrupt is enabled

1h: Response Interrupt is disabled
7 RESP_ERR_CHK_ENA R/W 0h

Response Error Check Enable

Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver. Only R1 or R5 can be checked.

If Host Driver checks response error, this bit is set to 0h and the MMCSD0_UHS2_XFER_MODE[8] RESP_INTR_DIS bit is set to 0h. If Host Controller checks response error, sets this bit to 1h and sets the MMCSD0_UHS2_XFER_MODE[8] RESP_INTR_DIS bit to 1h. Response Type R1/R5 selects either R1 or R5 response type. If an error is detected, RES Packet Error Interrupt is generated in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Response Error Check is disabled

1h: Response Error Check is enabled
6 RESP_TYPE R/W 0h

Response Type R1/R5

When response error check is enabled, this bit selects either R1 or R5 response types.

Two types of response checks are supported: R1 for memory and R5 for SDIO.

Error Statuses Checked in R1:

Bit31 OUT_OF_RANGE

Bit30 ADDRESS_ERROR

Bit29 BLOCK_LEN_ERROR

Bit26 WP_VIOLATION

Bit25 CARD_IS_LOCKED

Bit23 COM_CRC_ERROR

Bit21 CARD_ECC_FAILED

Bit20 CC_ERROR

Bit19 ERROR

Response Flags Checked in R5:

Bit07 COM_CRC_ERROR

Bit03 ERROR

Bit01 FUNCTION_NUMBER

Bit00 OUT_OF_RANGE

0h: R1 (Memory)

1h: R5 (SDIO)
5 BYTE_MODE R/W 0h

Block/Byte Mode

This bit specifies whether data transfer is in byte mode or block mode when the MMCSD0_UHS2_COMMAND[5] DATA_PRESENT bit is set to 1h. This bit is effective to a command with data transfer.

0h: Block Mode

1h: Byte Mode
4 DATA_XFER_DIR R/W 0h

Data Transfer Direction

This bit specifies direction of data transfer when the MMCSD0_UHS2_COMMAND[5] DATA_PRESENT bit is set to 1h. This bit is effective to a command with data transfer.

0h: Read (Card to Host)

1h: Write (Host to Card)
3-2 RESERVED R 0h

Reserved
1 BLK_CNT_ENA R/W 0h

Block Count Enable

This bit specifies whether data transfer uses the MMCSD0_UHS2_BLOCK_COUNT register. If this bit is set to 1h, data transfer is terminated by Block Count. Setting to the MMCSD0_UHS2_BLOCK_COUNT register shall be equivalent to TLEN in UHS-II Command Packet register (MMCSD0_UHS2_COMMAND_PKT_0 - MMCSD0_UHS2_COMMAND_PKT_19).

0h: Block Count Disabled

1h: Block Count Enabled
0 DMA_ENA R/W 0h

DMA Enable

This bit selects whether DMA is used or not and is effective to a command with data transfer. One of DMA types is selected by the MMCSD0_HOST_CONTROL1[4-3] DMA_SELECT bit field.

0h: DMA is disabled

1h: DMA is enabled

6.6.4.48 MMCSD0_UHS2_COMMAND Register (Offset = 9Eh) [reset = 0h]

MMCSD0_UHS2_COMMAND is shown in Figure 12-2362 and described in Table 12-4576.

Return to Summary Table.

This register is used to program the Command for host controller.

Table 12-4575 MMCSD0_UHS2_COMMAND Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 009Eh
Figure 12-2362 MMCSD0_UHS2_COMMAND Register
15 14 13 12 11 10 9 8
RESERVED PKT_LENGTH
R-0h R/W-0h
7 6 5 4 3 2 1 0
CMD_TYPE DATA_PRESENT RESERVED SUB_COMMAND RESERVED
R/W-0h R/W-0h R-0h R/W-0h R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4576 MMCSD0_UHS2_COMMAND Register Field Descriptions
Bit Field Type Reset Description
15-13 RESERVED R 0h

Reserved
12-8 PKT_LENGTH R/W 0h

UHS-II Command Packet Length

A command packet length, which is set in the UHS-II Command Packet register (MMCSD0_UHS2_COMMAND_PKT_0 - MMCSD0_UHS2_COMMAND_PKT_19), is set to this bit field.

00011b – 00000b: 3-0 Bytes (Not used)

00100b: 4 Bytes

.... ....

10100b: 20 Bytes

11111b – 10101b
7-6 CMD_TYPE R/W 0h

Command Type

This field is used to distinguish a specific command like abort command. If this field is set to 0h, the UHS-II RES Packet is stored in UHS-II Response register (MMCSD0_UHS2_RESPONSE_0 - MMCSD0_UHS2_RESPONSE_19). To avoid overwriting the UHS-II Response register, when this field is set to 1h, the RES Packet (4 bytes length) of TRANS_ABORT CCMD is stored in the Response register (04F8 0010h - 04F8 0013h) and when this field is set to 2h, the RES Packet (8 bytes length) of memory or SDIO abort command (CMD12 or SDIO Abort command) is stored in the Response register (04F8 0018h - 04F8 001Fh). When this field is set to 3h, Host Controller controls lane to go into dormant state.

0h: Normal Command

1h: TRANS_ABORT CCMD

3h: CMD12 or SDIO Abort command

4h: Go Dormant Command
5 DATA_PRESENT R/W 0h

Data Present

This bit specifies whether the command is accompanied by data packet.

0h: No Data Present

1h: Data Present
4-3 RESERVED R 0h

Reserved
2 SUB_COMMAND R/W 0h

Sub Command Flag

This bit is added from Version 4.10 to distinguish a main command or sub command .

When issuing a main command, this bit is set to 0h and when issuing a sub command, this bit is set to 1h. Setting of this bit is checked by the MMCSD0_PRESENTSTATE[28] SUB_COMMAND_STS bit.

0h: Sub Command

1h: Main Command
1-0 RESERVED R 0h

Reserved

6.6.4.49 MMCSD0_UHS2_RESPONSE_0 to MMCSD0_UHS2_RESPONSE_19 Register (Offset = A0h to B3h) [reset = 0h]

MMCSD0_UHS2_RESPONSE_0 to MMCSD0_UHS2_RESPONSE_19 is shown in Figure 12-2363 and described in Table 12-4578.

Return to Summary Table.

This register is used to store received UHS-II RES Packet image.

Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command, which is specified by setting 1h or 2h to the MMCSD0_UHS2_COMMAND[7-6] CMD_TYPE bit field. The maximum response length is 20 bytes.

Table 12-4577 MMCSD0_UHS2_RESPONSE_0 to UHS2_RESPONSE_19 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00A0h to 04F8 00B3h
Figure 12-2363 MMCSD0_UHS2_RESPONSE_0 to MMCSD0_UHS2_RESPONSE_19 Register
7 6 5 4 3 2 1 0
RESP_PKT_BYTE
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4578 MMCSD0_UHS2_RESPONSE_0 to UHS2_RESPONSE_19 Register Field Descriptions
Bit Field Type Reset Description
7-0 RESP_PKT_BYTE R 0h

Response Packet Byte

Host Controller saves received UHS-II RES Packet image to this register except the response of an abort command.

Table 12-4579 shows UHS-II Response Register offsets.

Table 12-4579 UHS-II Response Register
Offset Preset Value Registers
04F8 0A0h Response Packet Byte 0
04F8 0A1h Response Packet Byte 1
04F8 0A2h Response Packet Byte 2
.... .... .... ....
04F8 0B3h Response Packet Byte 19

6.6.4.50 MMCSD0_UHS2_MESSAGE_SELECT Register (Offset = B4h) [reset = 0h]

MMCSD0_UHS2_MESSAGE_SELECT is shown in Figure 12-2364 and described in Table 12-4581.

Return to Summary Table.

This register is used to access internal buffer.

Table 12-4580 MMCSD0_UHS2_MESSAGE_SELECT Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00B4h
Figure 12-2364 MMCSD0_UHS2_MESSAGE_SELECT Register
7 6 5 4 3 2 1 0
RESERVED MSG_SEL
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4581 MMCSD0_UHS2_MESSAGE_SELECT Register Field Descriptions
Bit Field Type Reset Description
7-2 RESERVED R 0h

Reserved
1-0 MSG_SEL R/W 0h

UHS-II MSG Select

Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs can be read from the MMCSD0_UHS2_MESSAGE register (04F8 00BBh - 04F8 00B8h) by setting this register

(assumed for debug usage).

0h: The latest MSG

1h: One MSG before

2h: Two MSGs before

3h: Three MSGs before

6.6.4.51 MMCSD0_UHS2_MESSAGE Register (Offset = B8h) [reset = 0h]

MMCSD0_UHS2_MESSAGE is shown in Figure 12-2365 and described in Table 12-4583.

Return to Summary Table.

This register is used to access internal buffer.

Table 12-4582 MMCSD0_UHS2_MESSAGE Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00B8h
Figure 12-2365 MMCSD0_UHS2_MESSAGE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MSG_BYTE3 MSG_BYTE2
R-0h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSG_BYTE1 MSG_BYTE0
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4583 MMCSD0_UHS2_MESSAGE Register Field Descriptions
Bit Field Type Reset Description
31-24 MSG_BYTE3 R 0h

UHS II MSG

Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the MMCSD0_UHS2_MESSAGE_SELECT register. Usually 2 duplicate MSG packets are sent from/to UHS-II card. One of these 2 MSG packets which Host Controller recognizes as valid one is stored in the MMCSD0_UHS2_MESSAGE Register.
23-16 MSG_BYTE2 R 0h

UHS II MSG

Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the MMCSD0_UHS2_MESSAGE_SELECT register. Usually 2 duplicate MSG packets are sent from/to UHS-II card. One of these 2 MSG packets which Host Controller recognizes as valid one is stored in the MMCSD0_UHS2_MESSAGE Register.
15-8 MSG_BYTE1 R 0h

UHS II MSG

Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the MMCSD0_UHS2_MESSAGE_SELECT register. Usually 2 duplicate MSG packets are sent from/to UHS-II card. One of these 2 MSG packets which Host Controller recognizes as valid one is stored in the MMCSD0_UHS2_MESSAGE Register.
7-0 MSG_BYTE0 R 0h

UHS II MSG

Host Controller holds 4 MSG packets in FIFO buffer. One of 4 MSGs (length is 4 bytes) can be read from this register by setting the MMCSD0_UHS2_MESSAGE_SELECT register. Usually 2 duplicate MSG packets are sent from/to UHS-II card. One of these 2 MSG packets which Host Controller recognizes as valid one is stored in the MMCSD0_UHS2_MESSAGE Register.

6.6.4.52 MMCSD0_UHS2_DEVICE_INTR_STATUS Register (Offset = BCh) [reset = 0h]

MMCSD0_UHS2_DEVICE_INTR_STATUS is shown in Figure 12-2366 and described in Table 12-4585.

Return to Summary Table.

This register shows receipt of INT MSG from which device.

Table 12-4584 MMCSD0_UHS2_DEVICE_INTR_STATUS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00BCh
Figure 12-2366 MMCSD0_UHS2_DEVICE_INTR_STATUS Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_INT_STS
R/W1C-0h
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-4585 MMCSD0_UHS2_DEVICE_INTR_STATUS Register Field Descriptions
Bit Field Type Reset Description
15-0 DEV_INT_STS R/W1C 0h

UHS-II Device Interrupt Status

This register shows receipt of INT MSG from which device and is effective when the MMCSD0_UHS2_DEVICE_SELECT[7] INT_MSG_ENA bit is set to 1h. On receiving INT MSG from a device, Host Controller saves the INT MSG to MMCSD0_UHS2_DEVICE_INT_CODE register. A bit of this register, which is correspondent to Device ID, is set to 1h and generate Card Interrupt in Normal Interrupt Status register (see MMCSD0_NORMAL_INTR_STS[8] CARD_INTR).

Writing a bit to 1h clears the status bit (interrupt is treated) and writing a bit to 0h keeps the status value (interrupt is untreated). If the MMCSD0_UHS2_DEVICE_SELECT[7] INT_MSG_ENA bit is set to 0h, this register is cleared to 0h and Host Controller ignores receipt of INT MSG.

Effective bit range of this register is determined by the MMCSD0_UHS2_GEN_CAP[21-18] CORECFG_UHS2_MAX_DEVICES bit field. If N devices are supported, bits 1 to N are effective. Then Device ID is supposed to be assigned from 1 sequentially at the UHS-II Initialization. A bit of unsupported Device ID in this register shall be indicated to 0h.

D00 - Not used (Reserved)

D01 - Setting 1h means INT MSG is received from Device ID 1

D02 - Setting 1h means INT MSG is received from Device ID 2

.... .....

D15 - Setting 1h means INT MSG is received from Device ID 15

6.6.4.53 MMCSD0_UHS2_DEVICE_SELECT Register (Offset = BEh) [reset = 0h]

MMCSD0_UHS2_DEVICE_SELECT is shown in Figure 12-2367 and described in Table 12-4587.

Return to Summary Table.

UHS-II Device Select Register.

Table 12-4586 MMCSD0_UHS2_DEVICE_SELECT Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00BEh
Figure 12-2367 MMCSD0_UHS2_DEVICE_SELECT Register
7 6 5 4 3 2 1 0
INT_MSG_ENA RESERVED DEV_SEL
R/W-0h R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4587 MMCSD0_UHS2_DEVICE_SELECT Register Field Descriptions
Bit Field Type Reset Description
7 INT_MSG_ENA R/W 0h

INT MSG Enable (Optional)

This bit enables receipt of INT MSG. If this bit is set to 1h, receipt of INT MSG is informed by the MMCSD0_NORMAL_INTR_STS[8] CARD_INTR bit. If this bit is set to 0h, Host Controller ignores receipt of INT MSG and may not set the MMCSD0_UHS2_DEVICE_INT_CODE register.

Support of INT MSG Interrupt is optional. If trying to set this bit to 1h but still this bit is read 0, INT MSG Interrupt is not supported by the Host Controller. In this case, the MMCSD0_UHS2_DEVICE_INTR_STATUS register always shall be read 0 and the MMCSD0_UHS2_DEVICE_INT_CODE register may not be implemented.

0h: Disabled

1h: Enabled
6-4 RESERVED R 0h

Reserved
3-0 DEV_SEL R/W 0h

UHS-II Device Select

Host Controller holds an INT MSG packet per device. One of INT MSGs (up to 15) can be selected by this field and read from the MMCSD0_UHS2_DEVICE_INT_CODE. This field is effective when the MMCSD0_UHS2_DEVICE_SELECT[7] INT_MSG_ENA bit is set to 1h.

The number of devices implemented in the Host Controller is indicated by the MMCSD0_UHS2_GEN_CAP[21-18] CORECFG_UHS2_MAX_DEVICES bit field.

0h: Unselected (Default)

1h: INT MSG of Device ID 1 is selected

2h: INT MSG of Device ID 2 is selected

..... .....

Fh: INT MSG of Device ID 15 is selected

6.6.4.54 MMCSD0_UHS2_DEVICE_INT_CODE Register (Offset = BFh) [reset = 0h]

MMCSD0_UHS2_DEVICE_INT_CODE is shown in Figure 12-2368 and described in Table 12-4589.

Return to Summary Table.

This register is effective when the MMCSD0_UHS2_DEVICE_SELECT[7] INT_MSG_ENA bit is set to 1h.

Table 12-4588 MMCSD0_UHS2_DEVICE_INT_CODE Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00BFh
Figure 12-2368 MMCSD0_UHS2_DEVICE_INT_CODE Register
7 6 5 4 3 2 1 0
DEV_INTR
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4589 MMCSD0_UHS2_DEVICE_INT_CODE Register Field Descriptions
Bit Field Type Reset Description
7-0 DEV_INTR R 0h

UHS II Device Interrupt

This register is effective when the MMCSD0_UHS2_DEVICE_SELECT[7] INT_MSG_ENA bit is set to 1h. Host Controller holds an INT MSG packet per device. One of INT MSGs (Code length is 1 byte) up to 15 can be read from this register by selecting UHS-II Device Select (MMCSD0_UHS2_DEVICE_SELECT[3-0] DEV_SEL).

The number of the registers to hold INT MSGs is determined by the MMCSD0_UHS2_GEN_CAP[21-18] CORECFG_UHS2_MAX_DEVICES bit field. Device ID is supposed to be assigned from 1 sequentially at the UHS-II Initialization.

6.6.4.55 MMCSD0_UHS2_SOFTWARE_RESET Register (Offset = C0h) [reset = 0h]

MMCSD0_UHS2_SOFTWARE_RESET is shown in Figure 12-2369 and described in Table 12-4591.

Return to Summary Table.

UHS-II Software Reset Register.

Table 12-4590 MMCSD0_UHS2_SOFTWARE_RESET Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00C0h
Figure 12-2369 MMCSD0_UHS2_SOFTWARE_RESET Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED HOST_SDTRAN_RESET HOST_FULL_RESET
R-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4591 MMCSD0_UHS2_SOFTWARE_RESET Register Field Descriptions
Bit Field Type Reset Description
15-2 RESERVED R 0h

Reserved
1 HOST_SDTRAN_RESET R/W 0h

Host SD-TRAN Reset

Host Driver set this bit to 1h to reset SD-TRAN layer when CMD0 is issued to Device or data transfer error occurs. This bit is cleared automatically at completion of SD-TRAN reset. If CMD0 is issued, SD-TRAN Initialization sequence from CMD8 is required to use UHS-II mode. Assuming that bus power is maintained and CM-TRAN Initialization is not required.

Host Controller requires to do followings:

(1) SD Clock Enable is maintained (continue to provide RCLK).

(2) All setting register is maintained.

(3) Internal sequencers are reset to just after power on be able to issue a command.

(4) All Interrupt Status, Status Enable and Signal Enable are cleared.

(5) Data transfer is terminated and data in buffer is discarded.

0h: Not Affected

1h: Reset SD-TRAN
0 HOST_FULL_RESET R/W 0h

Host Full Reset

On issuing FULL_RESET CCMD, Host Driver set this bit to 1h to reset Host Controller. This bit is cleared automatically at completion of Host Controller reset. Initialization sequence from PHY Initialization is required to use UHS-II mode. Assuming that bus power is maintained.

Host Controller requires to do followings:

(1) SD Clock Enable is cleared (internal Clock is still synchronized).

(2) All setting register is cleared.

(3) Internal sequencers are reset to just after power on.

(4) All Interrupt Status, Status Enable and Signal Enable are cleared.

0h: Not Affected

1h: Reset Host Controller

6.6.4.56 MMCSD0_UHS2_TIMER_CONTROL Register (Offset = C2h) [reset = 0h]

MMCSD0_UHS2_TIMER_CONTROL is shown in Figure 12-2370 and described in Table 12-4593.

Return to Summary Table.

UHS-II Timeout Control Register.

Table 12-4592 MMCSD0_UHS2_TIMER_CONTROL Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00C2h
Figure 12-2370 MMCSD0_UHS2_TIMER_CONTROL Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
DEADLOCK_TIMEOUT_CTR CMDRESP_TIMEOUT_CTR
R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4593 MMCSD0_UHS2_TIMER_CONTROL Register Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R 0h

Reserved
7-4 DEADLOCK_TIMEOUT_CTR R/W 0h

Timeout Counter Value for Deadlock

This value determines the deadlock period while host expecting to receive a packet (1 second). Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register, prevent inadvertent timeout events by clearing the Timeout for Deadlock (in the MMCSD0_UHS2_ERR_INTR_STS_ENA register).

Fh: Reserved

Eh: TMCLK x 227

.... ....

1h: TMCLK x 214

0h: TMCLK x 213
3-0 CMDRESP_TIMEOUT_CTR R/W 0h

Timeout Counter Value for CMD_RES

This value determines the interval between command packet and response packet (5 ms). Timeout clock frequency will be generated by dividing the base clock TMCLK value by this value. When setting this register, prevent inadvertent timeout events by clearing the Timeout for CMD_RES (in the MMCSD0_UHS2_ERR_INTR_STS_ENA register).

Fh: Reserved

Eh: TMCLK x 227

.... ....

1h: TMCLK x 214

0h: TMCLK x 213

6.6.4.57 MMCSD0_UHS2_ERR_INTR_STS Register (Offset = C4h) [reset = 0h]

MMCSD0_UHS2_ERR_INTR_STS is shown in Figure 12-2371 and described in Table 12-4595.

Return to Summary Table.

This register gives the status of all UHS-II interrupts.

Table 12-4594 MMCSD0_UHS2_ERR_INTR_STS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00C4h
Figure 12-2371 MMCSD0_UHS2_ERR_INTR_STS Register
31 30 29 28 27 26 25 24
VENDOR_SPECFIC_ERR RESERVED
R/W1C-0h R-0h
23 22 21 20 19 18 17 16
RESERVED DEADLOCK_TIMEOUT CMD_RESP_TIMEOUT
R-0h R/W1C-0h R/W1C-0h
15 14 13 12 11 10 9 8
ADMA2_ADMA3 RESERVED EBSY
R/W1C-0h R-0h R/W1C-0h
7 6 5 4 3 2 1 0
UNRECOVERABLE RESERVED TID FRAMING CRC RETRY_EXPIRED RESP_PKT HEADER
R/W1C-0h R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-4595 MMCSD0_UHS2_ERR_INTR_STS Register Field Descriptions
Bit Field Type Reset Description
31-27 VENDOR_SPECFIC_ERR R/W1C 0h

Vendor Specific Error

Vendor may use this field for vendor specific error status.

0h: Interrupt is not generated

1h: Vendor Specific Error
26-18 RESERVED R 0h

Reserved
17 DEADLOCK_TIMEOUT R/W1C 0h

Timeout for Deadlock

Setting of this bit means that deadlock timeout occurs. Host expects to receive a packet but not received in a specified timeout (1 second). Timeout value is determined by the setting of the MMCSD0_UHS2_TIMER_CONTROL[7-4] DEADLOCK_TIMEOUT_CTR bit field.

0h: Interrupt is not generated

1h: Deadlock Error
16 CMD_RESP_TIMEOUT R/W1C 0h

Timeout for CMD_RES

Setting of this bit means that RES Packet timeout occurs. Host expects to receive RES packet but not received in a specified timeout (5 ms). Timeout value is determined by the setting of the MMCSD0_UHS2_TIMER_CONTROL[3-0] CMDRESP_TIMEOUT_CTR bit field.

0h: Interrupt is not generated

1h: RES Packet Timeout Error
15 ADMA2_ADMA3 R/W1C 0h

ADMA2/3 Error

Setting of this bit means that ADMA2/3 Error occurs in UHS-II mode. ADMA2/3 Error Status is indicated to the MMCSD0_ADMA_ERR_STATUS register, which is defined in the Host spec 3.00.

0h: Interrupt is not generated

1h: ADMA2/3 Error
14-9 RESERVED R 0h

Reserved
8 EBSY R/W1C 0h

EBSY Error

On receiving EBSY packet, if the packet indicates an error, this bit is set to 1h. Setting of this bit also sets Error Interrupt and Transfer Completer together in the MMCSD0_NORMAL_INTR_STS register. This error check is effective for a command with setting the MMCSD0_UHS2_XFER_MODE[14] EBSY_WAIT bit.

0h: Interrupt is not generated

1h: EBSY Error (Backend Error)
7 UNRECOVERABLE R/W1C 0h

Unrecoverable Error

Setting of this bit means that Unrecoverable Error is set in a packet from a device.

0h: Interrupt is not generated

1h: Device Unrecoverable Error
6 RESERVED R 0h

Reserved
5 TID R/W1C 0h

TID Error

Setting of this bit means that TID Error occurs.

0h: Interrupt is not generated

1h: TID Error
4 FRAMING R/W1C 0h

Framing Error

Setting of this bit means that Framing Error occurs during a packet receiving.

0h: Interrupt is not generated

1h: Framing Error
3 CRC R/W1C 0h

CRC Error

Setting of this bit means that CRC Error occurs during a packet receiving.

0h: Interrupt is not generated

1h: CRC Error
2 RETRY_EXPIRED R/W1C 0h

Retry Expired

Setting of this bit means that Retry Counter Expired Error occurs during data transfer. If this bit is set, either Framing Error or CRC Error in this register shall be set.

0h: Interrupt is not generated

1h: Retry Expired Error
1 RESP_PKT R/W1C 0h

RES Packet Error

Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If the MMCSD0_UHS2_XFER_MODE[7] RESP_ERR_CHK_ENA bit is set to 1h, Host Controller Checks R1 or R5 response. If an error is detected in a response, this bit is set to 1h.

0h: Interrupt is not generated

1h: RES Packet Error
0 HEADER R/W1C 0h

Header Error

Setting of this bit means that Header Error occurs in a received packet.

0h: Interrupt is not generated

1h: Header Error

6.6.4.58 MMCSD0_UHS2_ERR_INTR_STS_ENA Register (Offset = C8h) [reset = 0h]

MMCSD0_UHS2_ERR_INTR_STS_ENA is shown in Figure 12-2372 and described in Table 12-4597.

Return to Summary Table.

This register is used to enable the MMCSD0_UHS2_ERR_INTR_STS register fields.

Table 12-4596 MMCSD0_UHS2_ERR_INTR_STS_ENA Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00C8h
Figure 12-2372 MMCSD0_UHS2_ERR_INTR_STS_ENA Register
31 30 29 28 27 26 25 24
VENDOR_SPECFIC RESERVED
R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED DEADLOCK_TIMEOUT CMD_RESP_TIMEOUT
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
ADMA2_ADMA3 RESERVED EBSY
R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
UNRECOVERABLE RESERVED TID FRAMING CRC RETRY_EXPIRED RESP_PKT HEADER
R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4597 MMCSD0_UHS2_ERR_INTR_STS_ENA Register Field Descriptions
Bit Field Type Reset Description
31-27 VENDOR_SPECFIC R/W 0h

Vendor Specific Error

Setting this bit to 1h enables setting of Vendor Specific Error bit in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
26-18 RESERVED R 0h

Reserved
17 DEADLOCK_TIMEOUT R/W 0h

Timeout for Deadlock

Setting this bit to 1h enables setting of Timeout for Dead lock bit in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
16 CMD_RESP_TIMEOUT R/W 0h

Timeout for CMD_RES

Setting this bit to 1h enables setting of Timeout for CMD_RES bit in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
15 ADMA2_ADMA3 R/W 0h

ADMA2/3 Error

Setting this bit to 1h enables setting of ADMA2/3 Error bit in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
14-9 RESERVED R 0h

Reserved
8 EBSY R/W 0h

EBSY Error

Setting this bit to 1h enables setting of EBSY Error bit in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
7 UNRECOVERABLE R/W 0h

Unrecoverable Error

Setting this bit to 1h enables setting of Unrecoverable Error bit in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
6 RESERVED R 0h

Reserved
5 TID R/W 0h

TID Error

Setting this bit to 1h enables setting of TID Error bit in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
4 FRAMING R/W 0h

Framing Error

Setting this bit to 1h enables setting of Framing Error bit in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
3 CRC R/W 0h

CRC Error

Setting this bit to 1h enables setting of CRC Error bit in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
2 RETRY_EXPIRED R/W 0h

Retry Expired

Setting this bit to 1h enables setting of Retry Expired bit in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
1 RESP_PKT R/W 0h

RES Packet Error

Setting this bit to 1h enables setting of RES Packet Error bit in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled
0 HEADER R/W 0h

Header Error

Setting this bit to 1h enables setting of Header Error bit in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Status is Disabled

1h: Status is Enabled

6.6.4.59 MMCSD0_UHS2_ERR_INTR_SIG_ENA Register (Offset = CCh) [reset = 0h]

MMCSD0_UHS2_ERR_INTR_SIG_ENA is shown in Figure 12-2373 and described in Table 12-4599.

Return to Summary Table.

This register is used to generate UHS-II Interrupt signals.

Table 12-4598 MMCSD0_UHS2_ERR_INTR_SIG_ENA Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00CCh
Figure 12-2373 MMCSD0_UHS2_ERR_INTR_SIG_ENA Register
31 30 29 28 27 26 25 24
VENDOR_SPECFIC RESERVED
R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED DEADLOCK_TIMEOUT CMD_RESP_TIMEOUT
R-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
ADMA2_ADMA3 RESERVED EBSY
R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
UNRECOVERABLE RESERVED TID FRAMING CRC RETRY_EXPIRED_SIG_ENA RESP_PKT HEADER
R/W-0h R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4599 MMCSD0_UHS2_ERR_INTR_SIG_ENA Register Field Descriptions
Bit Field Type Reset Description
31-27 VENDOR_SPECFIC R/W 0h

Vendor Specific Error

Setting of a bit to 1h in this field enables generating interrupt signal when correspondent bit of Vendor Specific Error is set in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
26-18 RESERVED R 0h

Reserved
17 DEADLOCK_TIMEOUT R/W 0h

Timeout for Deadlock

Setting this bit to 1h enables generating interrupt signal when Timeout for Dead lock bit is set in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
16 CMD_RESP_TIMEOUT R/W 0h

Timeout for CMD_RES

Setting this bit to 1h enables generating interrupt signal when Timeout for CMD_RES bit is set in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
15 ADMA2_ADMA3 R/W 0h

ADMA2/3 Error

Setting this bit to 1h enables generating interrupt signal when ADMA2/3 Error bit is set in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
14-9 RESERVED R 0h

Reserved
8 EBSY R/W 0h

EBSY Error

Setting this bit to 1h enables generating interrupt signal when EBSY Error bit is set in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
7 UNRECOVERABLE R/W 0h

Unrecoverable Error

Setting this bit to 1h enables generating interrupt signal when Unrecoverable Error bit is set in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
6 RESERVED R 0h

Reserved
5 TID R/W 0h

TID Error

Setting this bit to 1h enables generating interrupt signal when TID Error bit is set in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
4 FRAMING R/W 0h

Framing Error

Setting this bit to 1h enables generating interrupt signal when Framing Error bit is set in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
3 CRC R/W 0h

CRC Error

Setting this bit to 1h enables generating interrupt signal when CRC Error bit is set in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
2 RETRY_EXPIRED_SIG_ENA R/W 0h

Retry Expired

Setting this bit to 1h enables generating interrupt signal when Retry Expired bit is set in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
1 RESP_PKT R/W 0h

RES Packet Error

Setting this bit to 1h enables generating interrupt signal when RES Packet Error bit is set in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled
0 HEADER R/W 0h

Header Error

Setting this bit to 1h enables generating interrupt signal when Header Error bit is set in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Interrupt Signal is Disabled

1h: Interrupt Signal is Enabled

6.6.4.60 MMCSD0_UHS2_SETTINGS_PTR Register (Offset = E0h) [reset = 100h]

MMCSD0_UHS2_SETTINGS_PTR is shown in Figure 12-2374 and described in Table 12-4601.

Return to Summary Table.

This register is pointer for UHS-II settings.

Table 12-4600 MMCSD0_UHS2_SETTINGS_PTR Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00E0h
Figure 12-2374 MMCSD0_UHS2_SETTINGS_PTR Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UHS2_SETTINGS_PTR
R-100h
LEGEND: R = Read Only; -n = value after reset
Table 12-4601 MMCSD0_UHS2_SETTINGS_PTR Register Field Descriptions
Bit Field Type Reset Description
15-0 UHS2_SETTINGS_PTR R 100h

Pointer for UHS-II Settings Register

6.6.4.61 MMCSD0_UHS2_CAPABILITIES_PTR Register (Offset = E2h) [reset = 110h]

MMCSD0_UHS2_CAPABILITIES_PTR is shown in Figure 12-2375 and described in Table 12-4603.

Return to Summary Table.

This register is pointer for UHS-II Capabilities Register.

Table 12-4602 MMCSD0_UHS2_CAPABILITIES_PTR Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00E2h
Figure 12-2375 MMCSD0_UHS2_CAPABILITIES_PTR Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UHS2_CAPABILITIES_PTR
R-110h
LEGEND: R = Read Only; -n = value after reset
Table 12-4603 MMCSD0_UHS2_CAPABILITIES_PTR Register Field Descriptions
Bit Field Type Reset Description
15-0 UHS2_CAPABILITIES_PTR R 110h

Pointer for UHS-II Capabilities Register

6.6.4.62 MMCSD0_UHS2_TEST_PTR Register (Offset = E4h) [reset = 120h]

MMCSD0_UHS2_TEST_PTR is shown in Figure 12-2376 and described in Table 12-4605.

Return to Summary Table.

This register is pointer for UHS-II Test Register.

Table 12-4604 MMCSD0_UHS2_TEST_PTR Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00E4h
Figure 12-2376 MMCSD0_UHS2_TEST_PTR Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UHS2_TEST_PTR
R-120h
LEGEND: R = Read Only; -n = value after reset
Table 12-4605 MMCSD0_UHS2_TEST_PTR Register Field Descriptions
Bit Field Type Reset Description
15-0 UHS2_TEST_PTR R 120h

Pointer for UHS-II Test Register

6.6.4.63 MMCSD0_SHARED_BUS_CTRL_PTR Register (Offset = E6h) [reset = 130h]

MMCSD0_SHARED_BUS_CTRL_PTR is shown in Figure 12-2377 and described in Table 12-4607.

Return to Summary Table.

This register is pointer for UHS-II Shared Bus Control Register.

Table 12-4606 MMCSD0_SHARED_BUS_CTRL_PTR Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00E6h
Figure 12-2377 MMCSD0_SHARED_BUS_CTRL_PTR Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SHARED_BUS_CTRL_PTR
R-130h
LEGEND: R = Read Only; -n = value after reset
Table 12-4607 MMCSD0_SHARED_BUS_CTRL_PTR Register Field Descriptions
Bit Field Type Reset Description
15-0 SHARED_BUS_CTRL_PTR R 130h

Pointer for Shared Bus Control Register

6.6.4.64 MMCSD0_VENDOR_SPECFIC_PTR Register (Offset = E8h) [reset = 140h]

MMCSD0_VENDOR_SPECFIC_PTR is shown in Figure 12-2378 and described in Table 12-4609.

Return to Summary Table.

This register is pointer for UHS-II Vendor Specific Register.

Table 12-4608 MMCSD0_VENDOR_SPECFIC_PTR Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00E8h
Figure 12-2378 MMCSD0_VENDOR_SPECFIC_PTR Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VENDOR_SPECFIC_PTR
R-140h
LEGEND: R = Read Only; -n = value after reset
Table 12-4609 MMCSD0_VENDOR_SPECFIC_PTR Register Field Descriptions
Bit Field Type Reset Description
15-0 VENDOR_SPECFIC_PTR R 140h

Pointer for Vendor Specific Area

6.6.4.65 MMCSD0_BOOT_TIMEOUT_CONTROL Register (Offset = F4h) [reset = 0h]

MMCSD0_BOOT_TIMEOUT_CONTROL is shown in Figure 12-2379 and described in Table 12-4611.

Return to Summary Table.

This is used to program the boot timeout value counter.

Table 12-4610 MMCSD0_BOOT_TIMEOUT_CONTROL Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00F4h
Figure 12-2379 MMCSD0_BOOT_TIMEOUT_CONTROL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA_TIMEOUT_CNT
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4611 MMCSD0_BOOT_TIMEOUT_CONTROL Register Field Descriptions
Bit Field Type Reset Description
31-0 DATA_TIMEOUT_CNT R/W 0h

Boot Data Timeout Counter Value

This value determines the interval by which DAT line timeouts are detected during boot operation for eMMC4.4 card.

The value is in number of SD clock.

6.6.4.66 MMCSD0_VENDOR_REGISTER Register (Offset = F8h) [reset = 4E20h]

MMCSD0_VENDOR_REGISTER is shown in Figure 12-2380 and described in Table 12-4613.

Return to Summary Table.

Vendor register added for Auto Gate SD CLK, CMD11 Power Down Timer, Enhanced Strobe and eMMC Hardware Reset.

Table 12-4612 MMCSD0_VENDOR_REGISTER Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00F8h
Figure 12-2380 MMCSD0_VENDOR_REGISTER Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED AUTOGATE_SDCLK
R-0h R/W-0h
15 14 13 12 11 10 9 8
CMD11_PD_TIMER
R/W-1388h
7 6 5 4 3 2 1 0
CMD11_PD_TIMER EMMC_HW_RESET ENHANCED_STROBE
R/W-1388h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4613 MMCSD0_VENDOR_REGISTER Register Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h

Reserved
16 AUTOGATE_SDCLK R/W 0h

Auto Gate SD CLK

If this bit is set, SD CLK will be gated automatically when there is no transfer.

This is applicable only for Embedded Device.

0h: Disable

1h: Enable
15-2 CMD11_PD_TIMER R/W 1388h

CMD11 Power Down Timer Value
1 EMMC_HW_RESET R/W 0h

eMMC Hardware Reset

Hardware reset signal is generared for eMMC card when this bit is set.

0h: De-sassert hardware reset pin

1h: Drives the hardware reset pin as ZERO (Active LOW to eMMC card)
0 ENHANCED_STROBE R/W 0h

Enhanced Strobe

This bit enables the enhanced strobe logic of the Host Controller.

6.6.4.67 MMCSD0_SLOT_INT_STS Register (Offset = FCh) [reset = 0h]

MMCSD0_SLOT_INT_STS is shown in Figure 12-2381 and described in Table 12-4615.

Return to Summary Table.

This register is used to read the interrupt signal for each slot.

Table 12-4614 MMCSD0_SLOT_INT_STS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00FCh
Figure 12-2381 MMCSD0_SLOT_INT_STS Register
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
INTR_SIG
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4615 MMCSD0_SLOT_INT_STS Register Field Descriptions
Bit Field Type Reset Description
15-8 RESERVED R 0h

Reserved
7-0 INTR_SIG R 0h

Interrupt Signal for Slot#0

These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot.

6.6.4.68 MMCSD0_HOST_CONTROLLER_VER Register (Offset = FEh) [reset = 1004h]

MMCSD0_HOST_CONTROLLER_VER is shown in Figure 12-2382 and described in Table 12-4617.

Return to Summary Table.

This register is used to read the vendor version number and specification version number.

Table 12-4616 MMCSD0_HOST_CONTROLLER_VER Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 00FEh
Figure 12-2382 MMCSD0_HOST_CONTROLLER_VER Register
15 14 13 12 11 10 9 8
VEN_VER_NUM
R-10h
7 6 5 4 3 2 1 0
SPEC_VER_NUM
R-4h
LEGEND: R = Read Only; -n = value after reset
Table 12-4617 MMCSD0_HOST_CONTROLLER_VER Register Field Descriptions
Bit Field Type Reset Description
15-8 VEN_VER_NUM R 10h

Vendor Version Number

The Vendor Version Number is set to 10h (1.0)
7-0 SPEC_VER_NUM R 4h

Specification Version Number

This status indicates the Host Controller Specification Version. The upper and lower 4-bits indicate the version.

0h: SD Host Controller Specification Version 1.00

1h: SD Host Controller Specification Version 2.00 Including the feature of the ADMA and Test Register

2h: SD Host Controller Specification Version 3.00

3h: SD Host Controller Specification Version 4.00

4h: SD Host Controller Specification Version 4.10

Others: Reserved

6.6.4.69 MMCSD0_UHS2_GEN_SETTINGS Register (Offset = 100h) [reset = 0h]

MMCSD0_UHS2_GEN_SETTINGS is shown in Figure 12-2383 and described in Table 12-4619.

Return to Summary Table.

Start Address of General settings is pointed by the MMCSD0_UHS2_SETTINGS_PTR Register.

Table 12-4618 MMCSD0_UHS2_GEN_SETTINGS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0100h
Figure 12-2383 MMCSD0_UHS2_GEN_SETTINGS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED NUMLANES
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED POWER_MODE
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4619 MMCSD0_UHS2_GEN_SETTINGS Register Field Descriptions
Bit Field Type Reset Description
31-14 RESERVED R 0h

Reserved
13-8 NUMLANES R/W 0h

Number of Lanes and Functionalities

The lane configuration of a Host System is set to this field depends on the capability among Host Controller and connected devices. 2 Lanes FD mode is mandatory and the others modes are optional.

0h: 2 Lanes FD or 2L-HD

1h: Not Used

2h: 3 Lanes 2D1U-FD (Embedded)

3h: 3 Lanes 1D2U-FD (Embedded)

4h: 4 Lanes 2D2U-FD (Embedded)

Others: Reserved
7-1 RESERVED R 0h

Reserved
0 POWER_MODE R/W 0h

Power Mode

This field determines either Fast mode or Low Power mode. Host and all devices connected to the host shall be set to the same mode.

0h: Fast Mode

1h: Low Power Mode

6.6.4.70 MMCSD0_UHS2_PHY_SETTINGS Register (Offset = 104h) [reset = 0h]

MMCSD0_UHS2_PHY_SETTINGS is shown in Figure 12-2384 and described in Table 12-4621.

Return to Summary Table.

Start Address of PHY settings is pointed by the MMCSD0_UHS2_SETTINGS_PTR Register.

Table 12-4620 MMCSD0_UHS2_PHY_SETTINGS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0104h
Figure 12-2384 MMCSD0_UHS2_PHY_SETTINGS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
N_LSS_DIR N_LSS_SYN
R/W-0h R/W-0h
15 14 13 12 11 10 9 8
HIBERNATE_ENA RESERVED
R/W-0h R-0h
7 6 5 4 3 2 1 0
SPEED_RANGE RESERVED
R/W-0h R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4621 MMCSD0_UHS2_PHY_SETTINGS Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h

Reserved
23-20 N_LSS_DIR R/W 0h

Host N_LSS_DIR

The largest value of N_LSS_DIR capabilities among the Host Controller and Connected Devices is set to this field.

0h: 8 x 16 LSS

1h: 8 x 1 LSS

2h: 8 x 2 LSS

3h: 8 x 3 LSS

.... ....

Fh: 8 x 15 LSS
19-16 N_LSS_SYN R/W 0h

Host N_LSS_SYN

The largest value of N_LSS_SYN capabilities among the Host Controller and Connected Devices is set to this field.

0h: 4 x 16 LSS

1h: 4 x 1 LSS

2h: 4 x 2 LSS 3h - 4 x 3 LSS

.... ....

Fh: 4 x 15 LSS
15 HIBERNATE_ENA R/W 0h

Hibernate Enable

After checking card capability of Hibernate mode, if all devices support Hibernate mode, this bit may be set. This bit determines whether Host remains in Dormant state or goes to Hibernate state. In Hibernate mode, VDD1 Power may be off.

0h: Hibernate Disabled

1h: Hibernate Enabled
14-8 RESERVED R 0h

Reserved
7-6 SPEED_RANGE R/W 0h

Speed Range

PLL multiplier is selected by this field. Change of PLL Multiplier is not effective immediately and is applied from exiting Dormant State.

0h: Range A (Defalt)

1h: Range B

2h: Reserved

3h: Reserved
5-0 RESERVED R 0h

Reserved

6.6.4.71 MMCSD0_UHS2_LNK_TRN_SETTINGS Register (Offset = 108h) [reset = 0h]

MMCSD0_UHS2_LNK_TRN_SETTINGS is shown in Figure 12-2385 and described in Table 12-4623.

Return to Summary Table.

Start Address of LINK/TRAN settings is pointed by the MMCSD0_UHS2_SETTINGS_PTR Register.

Table 12-4622 MMCSD0_UHS2_LNK_TRN_SETTINGS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0108h
Figure 12-2385 MMCSD0_UHS2_LNK_TRN_SETTINGS Register
63 62 61 60 59 58 57 56
RESERVED
R-0h
55 54 53 52 51 50 49 48
RESERVED
R-0h
47 46 45 44 43 42 41 40
RESERVED
R-0h
39 38 37 36 35 34 33 32
N_DATA_GAP
R/W-0h
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED RETRY_COUNT
R-0h R/W-0h
15 14 13 12 11 10 9 8
HOST_NFCU
R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4623 MMCSD0_UHS2_LNK_TRN_SETTINGS Register Field Descriptions
Bit Field Type Reset Description
63-40 RESERVED R 0h

Reserved
39-32 N_DATA_GAP R/W 0h

Host N_DATA_GAP

The largest value of N_DATA_GAP capabilities among the Host Controller and Connected Devices is set to this field.

00h: No Gap

01h: 1 LSS

02h: 2 LSS

03h: 3 LSS

.... ....

FFh: 255 LSS
31-18 RESERVED R 0h

Reserved
17-16 RETRY_COUNT R/W 0h

Retry Count

Data Burst retry count is set to this field.

00h: Retry Disabled

01h: 1 time

02h: 2 times

03h: 3 times
15-8 HOST_NFCU R/W 0h

Host N_FCU

Host Driver sets the number of blocks in Data Burst (Flow Control) to this field.

The value shall be smaller than or equal to N_FCU capabilities among the Host Controller and connected card and devices. Setting 1 to 4 blocks is recommended considering buffer size.

00h: 256 Blocks

01h: 1 Block

02h: 2 Blocks

03h: 3 Blocks

.... ....

FFh: 255 Blocks
7-0 RESERVED R 0h

Reserved

6.6.4.72 MMCSD0_UHS2_GEN_CAP Register (Offset = 110h) [reset = 44F11h]

MMCSD0_UHS2_GEN_CAP is shown in Figure 12-2386 and described in Table 12-4625.

Return to Summary Table.

Start Address of General Capabilities is pointed by the MMCSD0_UHS2_GEN_CAP Register.

Table 12-4624 MMCSD0_UHS2_GEN_CAP Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0110h
Figure 12-2386 MMCSD0_UHS2_GEN_CAP Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
CORECFG_UHS2_BUS_TOPLOGY CORECFG_UHS2_MAX_DEVICES DEVICE_TYPE
R-0h R-1h R-0h
15 14 13 12 11 10 9 8
RESERVED CFG_64BIT_ADDRESSING NUM_LANES
R-0h R-1h R-Fh
7 6 5 4 3 2 1 0
GAP DAP
R-1h R-1h
LEGEND: R = Read Only; -n = value after reset
Table 12-4625 MMCSD0_UHS2_GEN_CAP Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h

Reserved
23-22 CORECFG_UHS2_BUS_TOPLOGY R 0h

Bus Topology

This field indicates one of bus topologies configured by a Host system.

0h: P2P Connection

1h: Ring Connection

2h: HUB Connection

3h: HUB is Connected in Ring
21-18 CORECFG_UHS2_MAX_DEVICES R 1h

Number of Devices Supported

This field indicates the maximum number of devices supported by the Host Controller.

0h: Not used

1h: 1 Devices

2h: 2 Devices

.... ....

Fh: 15 Devices
17-16 DEVICE_TYPE R 0h

Removable/Embedded

This field indicates device type configured by a Host system.

0h: Removable Card (P2P)

1h: Embedded Devices

2h: Embedded Devices + Removable Card

3h: Reserved
15 RESERVED R 0h

Reserved
14 CFG_64BIT_ADDRESSING R 1h

64-bit Addressing

This field indicates support of 64-bit addressing by the Host Controller.

0h: 32-bit Addressing is supported

1h: 32-bit and 64-bit Addressing is supported
13-8 NUM_LANES R Fh

Number of Lanes and Functionalities

This field indicates support of lanes by the Host Controller.

0 mean not supported and 1 means supported.

D08: 2L-HD

D09: 2D1U-FD

D10: 1D2U-FD

D11: 2D2U-FD

D12: Reserved

D13: Reserved
7-4 GAP R 1h

GAP (Group Allocation Power)

This field indicates the maximum capability of host power supply for a group configured by a Host system. This field is used to set the argument of DEVICE_INIT CCM.

0h: Not used

1h: 360 mW

2h: 720 mW

.... ....

Fh: 360 x 15 mW
3-0 DAP R 1h

DAP (Device Allocation Power)

This field indicates the maximum capability of host power supply for a device configured by a Host system. This field is used to set the argument of DEVICE_INIT CCMD.

0h: 360 mW (Default)

1h: 360 mW

2h: 720 mW

.... ....

Fh: 360 x 15 mW

6.6.4.73 MMCSD0_UHS2_PHY_CAP Register (Offset = 114h) [reset = 110000h]

MMCSD0_UHS2_PHY_CAP is shown in Figure 12-2387 and described in Table 12-4627.

Return to Summary Table.

Start Address of PHY Capabilities is pointed by the MMCSD0_UHS2_CAPABILITIES_PTR Register.

Table 12-4626 MMCSD0_UHS2_PHY_CAP Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0114h
Figure 12-2387 MMCSD0_UHS2_PHY_CAP Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
N_LSS_DIR N_LSS_SYN
R-1h R-1h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
SPEED_RANGE RESERVED
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4627 MMCSD0_UHS2_PHY_CAP Register Field Descriptions
Bit Field Type Reset Description
31-24 RESERVED R 0h

Reserved
23-20 N_LSS_DIR R 1h

Host N_LSS_DIR

This field indicates the minimum N_LSS_DIR required by the Host Controller.

0h: 4 x 16 LSS

1h: 4 x 1 LSS

2h: 4 x 2 LSS

3h: 4 x 3 LSS

.... ....

Fh: 4 x 15 LSS
19-16 N_LSS_SYN R 1h

Host N_LSS_SYN

This field indicates the minimum N_LSS_SYN required by the Host Controller.

0h: 4 x 16 LSS

1h: 4 x 1 LSS

2h: 4 x 2 LSS

3h: 4 x 3 LSS

.... ....

Fh: 4 x 15 LSS
15-8 RESERVED R 0h

Reserved
7-6 SPEED_RANGE R 0h

Speed Range

This field indicates supported Speed Range by the Host Controller.

0h: Range A (Default)

1h: Range A and Range B

2h: Reserved

3h: Reserved
5-0 RESERVED R 0h

Reserved

6.6.4.74 MMCSD0_UHS2_LNK_TRN_CAP Register (Offset = 118h) [reset = 8120000100h]

MMCSD0_UHS2_LNK_TRN_CAP is shown in Figure 12-2388 and described in Table 12-4629.

Return to Summary Table.

Start Address of LINK/TRAN settings is pointed by the MMCSD0_UHS2_CAPABILITIES_PTR Register.

Table 12-4628 MMCSD0_UHS2_LNK_TRN_CAP Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0118h
Figure 12-2388 MMCSD0_UHS2_LNK_TRN_CAP Register
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
RESERVED
R-0h
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
RESERVED N_DATA_GAP
R-0h R-81h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAX_BLK_LENGTH RESERVED
R-200h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
N_FCU RESERVED
R-1h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4629 MMCSD0_UHS2_LNK_TRN_CAP Register Field Descriptions
Bit Field Type Reset Description
63-40 RESERVED R 0h

Reserved
39-32 N_DATA_GAP R 81h

Host N_DATA_GAP

This field indicates the minimum number of data gap (DIDL) supported by the Host Controller.

00h: No Gap

01h: 1 LSS

02h: 2 LSS

03h: 3 LSS

.... ....

FFh: 255 LSS
31-20 MAX_BLK_LENGTH R 200h

Host Maximum Block Length

This field indicates maximum block length by the Host Controller.

000h: Not Used

001h: 1 byte

002h: 2 bytes

.... ....

200h: 512 bytes

.... ....

800h: 2048 bytes

801h - FFFh: Not Used
19-16 RESERVED R 0h

Reserved
15-8 N_FCU R 1h

Host N_FCU

This field indicates maximum the number of blocks in a Flow Control unit by the Host Controller. This value is determined by supported buffer size.

00h: 256 Blocks

01h: 1 Block

02h: 2 Block

03h: 3 Block

.... ....

FFh: 255 Blocks
7-0 RESERVED R 0h

Reserved

6.6.4.75 MMCSD0_FORCE_UHSII_ERR_INT_STS Register (Offset = 120h) [reset = 0h]

MMCSD0_FORCE_UHSII_ERR_INT_STS is shown in Figure 12-2389 and described in Table 12-4631.

Return to Summary Table.

This register is not physically implemented, rather it is an address where the MMCSD0_UHS2_ERR_INTR_STS register can be written.

Table 12-4630 MMCSD0_FORCE_UHSII_ERR_INT_STS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0120h
Figure 12-2389 MMCSD0_FORCE_UHSII_ERR_INT_STS Register
31 30 29 28 27 26 25 24
VENDOR_SPECIFIC RESERVED
W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED TIMEOUT_DEADLOCK TIMEOUT_CMD_RES
R-0h W-0h W-0h
15 14 13 12 11 10 9 8
ADMA RESERVED EBSY
W-0h R-0h W-0h
7 6 5 4 3 2 1 0
UNRECOVERABLE RESERVED TID FRAMING CRC RETRY_EXPIRED RES_PKT HEADER
W-0h R-0h W-0h W-0h W-0h W-0h W-0h W-0h
LEGEND: R = Read Only; W = Write Only; -n = value after reset
Table 12-4631 MMCSD0_FORCE_UHSII_ERR_INT_STS Register Field Descriptions
Bit Field Type Reset Description
31-27 VENDOR_SPECIFIC W 0h

Force Event for Vendor Specific Error

0h: Not Affected

1h: Vendor Specific Error Status is set
26-18 RESERVED R 0h

Reserved
17 TIMEOUT_DEADLOCK W 0h

Force Event for Timeout for Deadlock

Setting this bit forces the Host Controller to set Timeout for Deadlock in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: Timeout for Deadlock Error status is set
16 TIMEOUT_CMD_RES W 0h

Force Event for Timeout for CMD_RES

Setting this bit forces the Host Controller to set Timeout for CMD_RES in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: Timout for CMD_RES Status is set
15 ADMA W 0h

Force Event for ADMA Error

Setting this bit forces the Host Controller to set ADMA Error in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: ADMA Error Status is set
14-9 RESERVED R 0h

Reserved
8 EBSY W 0h

Force Event for EBSY Error

Setting this bit forces the Host Controller to set EBSY Error in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: EBSY Error Status is set
7 UNRECOVERABLE W 0h

Force Event for Unrecoverable Error

Setting this bit forces the Host Controller to set Unrecoverable Error in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: Unrecoverable Error Status is set
6 RESERVED R 0h

Reserved
5 TID W 0h

Force Event for TID Error

Setting this bit forces the Host Controller to set TID Error in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: TID Error Status is set
4 FRAMING W 0h

Force Event for Framing Error

Setting this bit forces the Host Controller to set Framing Error in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: Framing Error Status is set
3 CRC W 0h

Force Event for CRC Error

Setting this bit forces the Host Controller to set CRC Error in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: CRC Error Status is set
2 RETRY_EXPIRED W 0h

Force Event for Retry Expired

Setting this bit forces the Host Controller to set Retry Expired in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: Retry expired error status is set
1 RES_PKT W 0h

Force Event for RES Packet Error

Setting this bit forces the Host Controller to set RES Packet Error in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: RES packet error status is set
0 HEADER W 0h

Force Event for Header Error

Setting this bit forces the Host Controller to set Header Error in the MMCSD0_UHS2_ERR_INTR_STS register.

0h: Not affected

1h: Header error status is set

6.6.4.76 MMCSD0_CQ_VERSION Register (Offset = 200h) [reset = 510h]

MMCSD0_CQ_VERSION is shown in Figure 12-2390 and described in Table 12-4633.

Return to Summary Table.

This register provides information about the version of the eMMC CQ (Command Queueing) standard which is 285 implemented by the CQE, in BCD format. The current version is rev 5.1.

The following table describes the CQBASE+00h: Command Queueing Version.

Table 12-4632 MMCSD0_CQ_VERSION Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0200h
Figure 12-2390 MMCSD0_CQ_VERSION Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED EMMC_MAJOR_VER_NUM
R-0h R-5h
7 6 5 4 3 2 1 0
EMMC_MINOR_VER_NUM EMMC_VERSION_SUFFIX
R-1h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4633 MMCSD0_CQ_VERSION Register Field Descriptions
Bit Field Type Reset Description
31-12 RESERVED R 0h

Reserved
11-8 EMMC_MAJOR_VER_NUM R 5h

eMMC Major Version Number (digit left of decimal point), in BCD format
7-4 EMMC_MINOR_VER_NUM R 1h

eMMC Minor Version Number (digit right of decimal point), in BCD format
3-0 EMMC_VERSION_SUFFIX R 0h

eMMC Version Suffix (2nd digit right of decimal point), in BCD format

6.6.4.77 MMCSD0_CQ_CAPABILITIES Register (Offset = 204h) [reset = 30C8h]

MMCSD0_CQ_CAPABILITIES is shown in Figure 12-2391 and described in Table 12-4635.

Return to Summary Table.

This register is reserved for capability indication.

Table 12-4634 MMCSD0_CQ_CAPABILITIES Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0204h
Figure 12-2391 MMCSD0_CQ_CAPABILITIES Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
CF_MUL RESERVED CF_VAL
R-3h R-0h R-C8h
7 6 5 4 3 2 1 0
CF_VAL
R-C8h
LEGEND: R = Read Only; -n = value after reset
Table 12-4635 MMCSD0_CQ_CAPABILITIES Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h

Reserved
15-12 CF_MUL R 3h

Internal Timer Clock Frequency Multiplier (ITCFMUL)

ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the SQS polling period. See ITCFVAL definition for details (MMCSD0_CQ_CAPABILITIES[9-0] CF_VAL).

Field Value Description:

0h: 0.001 MHz

1h: 0.01 MHz

2h: 0.1 MHz

3h: 1 MHz

4h: 10 MHz

Other values are reserved
11-10 RESERVED R 0h

Reserved
9-0 CF_VAL R C8h

Internal Timer Clock Frequency Value (ITCFVAL)

ITCFMUL and ITCFVAL indicate the frequency of the clock used for interrupt coalescing timer and for determining the polling period when using periodic SEND_QUEUE_STATUS (CMD13) polling.

The clock frequency is calculated as ITCFVAL × ITCFMUL.

For example, to encode 19.2 MHz ITCFVAL shall be
C0h (= 192 decimal) and ITCFMUL shall be 2h (0.1 MHz).

192 × 0.1 MHz = 19.2 MHz

6.6.4.78 MMCSD0_CQ_CONFIG Register (Offset = 208h) [reset = 0h]

MMCSD0_CQ_CONFIG is shown in Figure 12-2392 and described in Table 12-4637.

Return to Summary Table.

This register controls CQE behavior affecting the general operation of command queueing 290 module or operation of multiple tasks in the same time.

Table 12-4636 MMCSD0_CQ_CONFIG Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0208h
Figure 12-2392 MMCSD0_CQ_CONFIG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED DCMD_ENA RESERVED TASK_DESC_SIZE
R-0h R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED CQ_ENABLE
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4637 MMCSD0_CQ_CONFIG Register Field Descriptions
Bit Field Type Reset Description
31-13 RESERVED R 0h

Reserved
12 DCMD_ENA R/W 0h

Direct Command (DCMD) Enable

This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a Data Transfer Task Descriptor, or a Direct Command Task Descriptor. CQE uses this bit when a task is issued in slot #31, to determine how to decode the Task Descriptor.

Bit Value Description

0h: Task descriptor in slot #31 is a Data Transfer Task Descriptor

1h: Task descriptor in slot #31 is a DCMD Task Descriptor
11-9 RESERVED R 0h

Reserved
8 TASK_DESC_SIZE R/W 0h

Task Descriptor Size

This bit indicates whether the task descriptor size is 128 bits or 64 bits . This bit can only be configured when the MMCSD0_CQ_CONFIG[0] CQ_ENABLE bit is 0hh (command queueing is disabled).

Bit Value Description

0h: Task descriptor size is 64 bits

1h: Task descriptor size is 128 bits
7-1 RESERVED R 0h

Reserved
0 CQ_ENABLE R/W 0h

Command Queueing Enable

Software shall write 1h to this bit when in order to enable command queueing mode (enable CQE).

When this bit is 0h, CQE is disabled and software controls the eMMC bus using the legacy eMMC host controller.

Before software writes 1h to this bit, software shall verify that the eMMC host controller is in idle state and there are no commands or data transfers ongoing.

When software wants to exit command queueing mode, it shall clear all previous tasks if such exist before setting this bit to 0h.

6.6.4.79 MMCSD0_CQ_CONTROL Register (Offset = 20Ch) [reset = 0h]

MMCSD0_CQ_CONTROL is shown in Figure 12-2393 and described in Table 12-4639.

Return to Summary Table.

This register controls CQE behavior affecting the general operation of command queueing 293 module or operation of multiple tasks in the same time.

Table 12-4638 MMCSD0_CQ_CONTROL Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 020Ch
Figure 12-2393 MMCSD0_CQ_CONTROL Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED CLEAR_ALL_TASKS
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED HALT_BIT
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4639 MMCSD0_CQ_CONTROL Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R 0h

Reserved
8 CLEAR_ALL_TASKS R/W 0h

Clear All Tasks

Software shall write 1h to this bit when it wants to clear all the tasks sent to the device.

This bit can only be written when CQE is in halt state (Halt bit is 1h).

When software writes 1h, the value of the register is updated to 1h, and CQE shall reset the MMCSD0_CQ_TASK_DOOR_BELL register and all other context information for all unfinished tasks. Then CQE will clear this bit.

Software should poll on this bit until it is set to back 0 and may then resume normal operation, by clearing the Halt bit.

CQE does not communicate to the device that the tasks were cleared. It is softwares responsibility to order the device to discard the tasks in its queue using CMDQ_TASK_MGMT command.

Writing 0h to this register shall have no effect.
7-1 RESERVED R 0h

Reserved
0 HALT_BIT R/W 0h

Halt

Host software shall write 1h to the bit when it wants to acquire software control over the eMMC bus and disable CQE from issuing commands on the bus.

For example, issuing a Discard Task command (CMDQ_TASK_MGMT).

When software writes 1h, CQE shall complete the ongoing task if such a task is in progress.

Once the task is completed and CQE is in idle state, CQE shall not issue new commands and shall indicate so to software by setting this bit to 1h.

Software may poll on this bit until it is set to 1h, and may only then send commands on the eMMC bus.

In order to exit halt state (resume CQE activity), software shall clear this bit (write 0h). Writing 0h when the value is already 0h shall have no effect.

6.6.4.80 MMCSD0_CQ_INTR_STS Register (Offset = 210h) [reset = 0h]

MMCSD0_CQ_INTR_STS is shown in Figure 12-2394 and described in Table 12-4641.

Return to Summary Table.

This register indicates pending interrupts that require service. Each bit in this registers is asserted 296 in response a specific event, only if the respective bit is set in the MMCSD0_CQ_INTR_STS_ENA register.

Table 12-4640 MMCSD0_CQ_INTR_STS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0210h
Figure 12-2394 MMCSD0_CQ_INTR_STS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED TASK_ERROR TASK_CLEARED RESP_ERR_DET TASK_COMPLETE HALT_COMPLETE
R-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h R/W1C-0h
LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-4641 MMCSD0_CQ_INTR_STS Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h

Reserved
4 TASK_ERROR R/W1C 0h

Task Error Interrupt (TERR)

This bit is asserted when task error is detected due to invalid task descriptor.
3 TASK_CLEARED R/W1C 0h

Task Cleared (TCL)

This status bit is asserted (if MMCSD0_CQ_INTR_STS_ENA[3] TASK_CLEARED = 1h) when a task clear operation is completed by CQE. The completed task clear operation is either an individual task clear (MMCSD0_CQ_TASK_CLEAR) or clearing of all tasks (MMCSD0_CQ_CONTROL).
2 RESP_ERR_DET R/W1C 0h

Response Error Detected Interrupt (RED)

This status bit is asserted (if MMCSD0_CQ_INTR_STS_ENA[2] RESP_ERR_DET = 1h) when a response is received with an error bit set in the device status field.

Software uses the MMCSD0_CQ_RESP_ERR_MASK register to configure which device status bit fields may trigger an interrupt, and which are masked.
1 TASK_COMPLETE R/W1C 0h

Task Complete Interrupt (TCC)

This status bit is asserted (if MMCSD0_CQ_INTR_STS_ENA[1] TASK_COMPLETE = 1h) when at least one of the following two conditions are met:

(1) A task is completed and the INT bit is set in its Task Descriptor

(2) Interrupt caused by Interrupt Coalescing logic

0 HALT_COMPLETE R/W1C 0h

Halt Complete Interrupt (HAC)

This status bit is asserted (if MMCSD0_CQ_INTR_STS_ENA[0] HALT_COMPLETE = 1h) when the MMCSD0_CQ_CONTROL[0] HALT_BIT bit transitions from 0h to 1h indicating that host controller has completed its current ongoing task and has entered halt state.

6.6.4.81 MMCSD0_CQ_INTR_STS_ENA Register (Offset = 214h) [reset = 0h]

MMCSD0_CQ_INTR_STS_ENA is shown in Figure 12-2395 and described in Table 12-4643.

Return to Summary Table.

This register enables and disables the reporting of the corresponding interrupt to host software in 299 MMCSD0_CQ_INTR_STS register. When a bit is set (1h) and the corresponding interrupt condition is active, then the 300 bit in the MMCSD0_CQ_INTR_STS register is asserted. Interrupt sources that are disabled (0h) are not indicated in the MMCSD0_CQ_INTR_STS 301 register. This register is bit-index matched to the MMCSD0_CQ_INTR_STS register.

Table 12-4642 MMCSD0_CQ_INTR_STS_ENA Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0214h
Figure 12-2395 MMCSD0_CQ_INTR_STS_ENA Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED TASK_ERROR TASK_CLEARED RESP_ERR_DET TASK_COMPLETE HALT_COMPLETE
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4643 MMCSD0_CQ_INTR_STS_ENA Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h

Reserved
4 TASK_ERROR R/W 0h

Task Error Interrupt Status Enable (TERR)

1h: MMCSD0_CQ_INTR_STS[4] TASK_ERROR bit will be set when its interrupt condition is active

0h: MMCSD0_CQ_INTR_STS[4] TASK_ERROR bit is disabled
3 TASK_CLEARED R/W 0h

Task Cleared Status Enable (TCL)

1h: MMCSD0_CQ_INTR_STS[3] TASK_CLEARED bit will be set when its interrupt condition is active

0h: MMCSD0_CQ_INTR_STS[3] TASK_CLEARED bit is disabled
2 RESP_ERR_DET R/W 0h

Response Error Detected Status Enable (RED)

1h: MMCSD0_CQ_INTR_STS[2] RESP_ERR_DET bit will be set when its interrupt condition is active

0h: MMCSD0_CQ_INTR_STS[2] RESP_ERR_DET bit is disabled
1 TASK_COMPLETE R/W 0h

Task Complete Status Enable (TCC)

1h: MMCSD0_CQ_INTR_STS[1] TASK_COMPLETE bit will be set when its interrupt condition is active

0h: MMCSD0_CQ_INTR_STS[1] TASK_COMPLETE bit is disabled
0 HALT_COMPLETE R/W 0h

Halt Complete Status Enable (HAC)

1h: MMCSD0_CQ_INTR_STS[0] HALT_COMPLETE bit will be set when its interrupt condition is active

0h: MMCSD0_CQ_INTR_STS[0] HALT_COMPLETE bit is disabled

6.6.4.82 MMCSD0_CQ_INTR_SIG_ENA Register (Offset = 218h) [reset = 0h]

MMCSD0_CQ_INTR_SIG_ENA is shown in Figure 12-2396 and described in Table 12-4645.

Return to Summary Table.

This register enables and disables the generation of interrupts to host software. When a bit is set 304 (1h) and the corresponding bit in the MMCSD0_CQ_INTR_STS register is set, then an interrupt is generated. Interrupt sources 305 that are disabled (0h) are still indicated in the MMCSD0_CQ_INTR_STS register. This register is bit-index matched 306 to the MMCSD0_CQ_INTR_STS register.

Table 12-4644 MMCSD0_CQ_INTR_SIG_ENA Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0218h
Figure 12-2396 MMCSD0_CQ_INTR_SIG_ENA Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED TASK_ERROR TASK_CLEARED RESP_ERR_DET TASK_COMPLETE HALT_COMPLETE
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4645 MMCSD0_CQ_INTR_SIG_ENA Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h

Reserved
4 TASK_ERROR R/W 0h

Task Error Interrupt Signal Enable (TERR)

When set and the MMCSD0_CQ_INTR_STS[4] TASK_ERROR bit is asserted, the CQE shall generate an interrupt.
3 TASK_CLEARED R/W 0h

Task Cleared Signal Enable (TCL)

When set and the MMCSD0_CQ_INTR_STS[3] TASK_CLEARED bit is asserted, the CQE shall generate an interrupt.
2 RESP_ERR_DET R/W 0h

Response Error Detected Signal Enable (RED)

When set and the MMCSD0_CQ_INTR_STS[2] RESP_ERR_DET bit is asserted, the CQE shall generate an interrupt.
1 TASK_COMPLETE R/W 0h

Task Complete Signal Enable (TCC)

When set and the MMCSD0_CQ_INTR_STS[1] TASK_COMPLETE bit is asserted, the CQE shall generate an interrupt.
0 HALT_COMPLETE R/W 0h

Halt Complete Signal Enable (HAC)

When set and the MMCSD0_CQ_INTR_STS[0] HALT_COMPLETE bit is asserted, the CQE shall generate an interrupt.

6.6.4.83 MMCSD0_CQ_INTR_COALESCING Register (Offset = 21Ch) [reset = 0h]

MMCSD0_CQ_INTR_COALESCING is shown in Figure 12-2397 and described in Table 12-4647.

Return to Summary Table.

This register controls the interrupt coalescing feature.

Table 12-4646 MMCSD0_CQ_INTR_COALESCING Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 021Ch
Figure 12-2397 MMCSD0_CQ_INTR_COALESCING Register
31 30 29 28 27 26 25 24
CQINTCOALESC_ENABLE RESERVED
R/W-0h R-0h
23 22 21 20 19 18 17 16
RESERVED IC_STATUS RESERVED
R-0h R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED CTR_THRESHOLD
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED TIMEOUT_VAL
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4647 MMCSD0_CQ_INTR_COALESCING Register Field Descriptions
Bit Field Type Reset Description
31 CQINTCOALESC_ENABLE R/W 0h

Interrupt Coalescing Enable/Disable:

When set to 0h by software, command responses are neither counted nor timed. Interrupts are still triggered by completion of tasks with INT = 1 in the Task Descriptor.

When set to 1h, the interrupt coalescing mechanism is enabled and coalesced interrupts are generated.
30-21 RESERVED R 0h

Reserved
20 IC_STATUS R 0h

Interrupt Coalescing Status Bit (ICSB):

This bit indicates to software whether any tasks (with INT = 0) have completed and counted towards interrupt coalescing (ICSB is set if and only if IC counter > 0).

Bit Value Description

0h: No task completions have occurred since last counter reset (IC counter = 0)

1h: At least one task completion has been counted (IC counter > 0)
19-13 RESERVED R 0h

Reserved
12-8 CTR_THRESHOLD R/W 0h

Interrupt Coalescing Counter Threshold (ICCTH):

Software uses this field to configure the number of task completions (only tasks with INT = 0 in the Task Descriptor) which are required in order to generate an interrupt.

Counter Operation: As data transfer tasks with INT = 0 complete, they are counted by CQE. The counter is reset by software during the interrupt service routine.

The counter stops counting when it reaches the value configured in ICCTH.

The maximum allowed value is 31.

Note: When ICCTH is 0h, task completions are not counted, and counting-based interrupts are not generated.
7 RESERVED R 0h

Reserved
6-0 TIMEOUT_VAL R/W 0h

Interrupt Coalescing Timeout Value (ICTOVAL):

Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt.

Timer Operation: The timer is reset by software during the interrupt service routine.

It starts running when a data transfer task with INT = 0 is completed, after the timer was reset. When the timer reaches the value configured in ICTOVAL field it generates an interrupt and stops.

The timers unit is equal to 1024 clock periods of the clock whose frequency is specified in the Internal Timer Clock Frequency field in the MMCSD0_CQ_CAPABILITIES register.

The minimum value is 1h (1024 clock periods) and the maximum value is 7Fh (127 × 1024 clock periods).

For example, a MMCSD0_CQ_CAPABILITIES field value of 0h indicates a 19.2 MHz clock frequency (period = 52.08 ns). If the setting in ICTOVAL is 10h, the calculated polling period is 16 × 1024 × 52.08 ns = 853.33 µs

Note: When ICTOVAL is 0h, the timer is not running, and timer-based interrupts are not generated.

6.6.4.84 MMCSD0_CQ_TDL_BASE_ADDR Register (Offset = 220h) [reset = 0h]

MMCSD0_CQ_TDL_BASE_ADDR is shown in Figure 12-2398 and described in Table 12-4649.

Return to Summary Table.

This register is used for configuring the lower 32 bits of the byte address of the head of the Task 312 Descriptor List in the host memory.

Table 12-4648 MMCSD0_CQ_TDL_BASE_ADDR Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0220h
Figure 12-2398 MMCSD0_CQ_TDL_BASE_ADDR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQTDLBA_LO
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4649 MMCSD0_CQ_TDL_BASE_ADDR Register Field Descriptions
Bit Field Type Reset Description
31-0 CQTDLBA_LO R/W 0h

Task Descriptor List Base Address (TDLBA)

This register stores the LSB bits (bits 31-0) of the byte address of the head of the Task Descriptor List in system memory.

The size of the task descriptor list is 32 × (Task Descriptor size + Transfer Descriptor size) as configured by Host driver.

This address shall be set on Byte1 KByte boundary.

The lower 10 bits of this register shall be set to 0h by software and shall be ignored by CQE.

6.6.4.85 MMCSD0_CQ_TDL_BASE_ADDR_UPBITS Register (Offset = 224h) [reset = 0h]

MMCSD0_CQ_TDL_BASE_ADDR_UPBITS is shown in Figure 12-2399 and described in Table 12-4651.

Return to Summary Table.

This register is used for configuring the upper 32 bits of the byte address of the head of the Task 316 Descriptor List in the host memory.

Table 12-4650 MMCSD0_CQ_TDL_BASE_ADDR_UPBITS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0224h
Figure 12-2399 MMCSD0_CQ_TDL_BASE_ADDR_UPBITS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQTDLBA_HI
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4651 MMCSD0_CQ_TDL_BASE_ADDR_UPBITS Register Field Descriptions
Bit Field Type Reset Description
31-0 CQTDLBA_HI R/W 0h

Task Descriptor List Base Address (TDLBA)

This register stores the MSB bits (bits 63-32) of the byte address of the head of the Task Descriptor List in system memory.

The size of the task descriptor list is 32 × (Task Descriptor size + Transfer Descriptor size) as configured by Host driver.

This register is reserved when using 32-bit addressing mode.

6.6.4.86 MMCSD0_CQ_TASK_DOOR_BELL Register (Offset = 228h) [reset = 0h]

MMCSD0_CQ_TASK_DOOR_BELL is shown in Figure 12-2400 and described in Table 12-4653.

Return to Summary Table.

Using this register, software triggers CQE to process a new task.

Table 12-4652 MMCSD0_CQ_TASK_DOOR_BELL Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0228h
Figure 12-2400 MMCSD0_CQ_TASK_DOOR_BELL Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQTDB_VAL
W1S-0h
LEGEND: W1S = Write 1 to Set Bit; -n = value after reset
Table 12-4653 MMCSD0_CQ_TASK_DOOR_BELL Register Field Descriptions
Bit Field Type Reset Description
31-0 CQTDB_VAL W1S 0h

Command Queueing Task Doorbell

Software shall configure the MMCSD0_CQ_TDL_BASE_ADDR[31-0] CQTDLBA_LO and MMCSD0_CQ_TDL_BASE_ADDR_UPBITS[31-0] CQTDLBA_HI bit fields, and enable CQE in the MMCSD0_CQ_CONFIG register before using this register.

Writing 1h to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL.

CQE always processes tasks in-order according to the order submitted to the list by the MMCSD0_CQ_TASK_DOOR_BELL register write transactions.

CQE processes Data Transfer tasks by reading the Task Descriptor and sending QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) commands to the device.

CQE processes DCMD tasks (in slot #31, when enabled) by reading the Task Descriptor, and generating the command encoded by its index and argument.

The corresponding bit is cleared to 0h by CQE in one of the following events:

(a) When a task execution is completed (with success or error)

(b) The task is cleared using MMCSD0_CQ_TASK_CLEAR register

(c) All tasks are cleared using MMCSD0_CQ_CONTROL register

(d) CQE is disabled using MMCSD0_CQ_CONFIG register

Software may initiate multiple tasks at the same time (batch submission) by writing 1h to multiple bits of this register in the same transaction.

In the case of batch submission:

CQE shall process the tasks in order of the task index, starting with the lowest index.

If one or more tasks in the batch are marked with QBR, the ordering of execution will be based on said processing order.

Writing 0h by software shall have no impact on the hardware, and will not change the value of the register bit.

6.6.4.87 MMCSD0_CQ_TASK_COMP_NOTIF Register (Offset = 22Ch) [reset = 0h]

MMCSD0_CQ_TASK_COMP_NOTIF is shown in Figure 12-2401 and described in Table 12-4655.

Return to Summary Table.

This register is used by CQE to notify software about completed tasks.

Table 12-4654 MMCSD0_CQ_TASK_COMP_NOTIF Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 022Ch
Figure 12-2401 MMCSD0_CQ_TASK_COMP_NOTIF Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQTCN_VAL
R/W1C-0h
LEGEND: R/W1C = Read/Write 1 to Clear Bit; -n = value after reset
Table 12-4655 MMCSD0_CQ_TASK_COMP_NOTIF Register Field Descriptions
Bit Field Type Reset Description
31-0 CQTCN_VAL R/W1C 0h

Task Complete Notification

CQE shall set bit n of this register (at the same time it clears bit n of the MMCSD0_CQ_TASK_DOOR_BELL register) when a task execution is completed (with success or error).

When receiving interrupt for task completion, software may read this register to know which tasks have finished. After reading this register, software may clear the relevant bit fields by writing 1h to the corresponding bits.

6.6.4.88 MMCSD0_CQ_DEV_QUEUE_STATUS Register (Offset = 230h) [reset = 0h]

MMCSD0_CQ_DEV_QUEUE_STATUS is shown in Figure 12-2402 and described in Table 12-4657.

Return to Summary Table.

This register stores the most recent value of the device's queue status.

Table 12-4656 MMCSD0_CQ_DEV_QUEUE_STATUS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0230h
Figure 12-2402 MMCSD0_CQ_DEV_QUEUE_STATUS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQDQ_STS
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4657 MMCSD0_CQ_DEV_QUEUE_STATUS Register Field Descriptions
Bit Field Type Reset Description
31-0 CQDQ_STS R 0h

Device Queue Status

Every time the Host controller receives a queue status register (QSR) from the device, it updates this register with the response of status command (the device's queue status).

6.6.4.89 MMCSD0_CQ_DEV_PENDING_TASKS Register (Offset = 234h) [reset = 0h]

MMCSD0_CQ_DEV_PENDING_TASKS is shown in Figure 12-2403 and described in Table 12-4659.

Return to Summary Table.

This register indicates to software which tasks are queued in the device, awaiting execution.

Table 12-4658 MMCSD0_CQ_DEV_PENDING_TASKS Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0234h
Figure 12-2403 MMCSD0_CQ_DEV_PENDING_TASKS Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQDP_TSKS
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4659 MMCSD0_CQ_DEV_PENDING_TASKS Register Field Descriptions
Bit Field Type Reset Description
31-0 CQDP_TSKS R 0h

Device Pending Tasks

Bit n of this register is set if and only if QUEUED_TASK_PARAMS (CMD44) and QUEUED_TASK_ADDRESS (CMD45) were sent for this specific task and if this task hasnt been executed yet.

CQE shall set this bit after receiving a successful response for CMD45. CQE shall clear this bit after the task has completed execution.

Software needs to read this register in the task-discard procedure, when the controller is halted, to determine if the task is queued in the device. If the task is queued, the driver sends a CMDQ_TASK_MGMT (CMD48) to the device ordering it to discard the task. Then software clears the task in the CQE. Only then the software orders CQE to resume its operation using MMCSD0_CQ_CONTROL register.

6.6.4.90 MMCSD0_CQ_TASK_CLEAR Register (Offset = 238h) [reset = 0h]

MMCSD0_CQ_TASK_CLEAR is shown in Figure 12-2404 and described in Table 12-4661.

Return to Summary Table.

This register is used for removing an outstanding task in the CQE 327. The register should be used only when CQE is in Halt state.

Table 12-4660 MMCSD0_CQ_TASK_CLEAR Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0238h
Figure 12-2404 MMCSD0_CQ_TASK_CLEAR Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQTCLR
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 12-4661 MMCSD0_CQ_TASK_CLEAR Register Field Descriptions
Bit Field Type Reset Description
31-0 CQTCLR R/W 0h

Command Queueing Task Clear

Writing 1h to bit n of this register orders CQE to clear a task which software has previously issued.

This bit can only be written when CQE is in Halt state as indicated in the MMCSD0_CQ_CONTROL register Halt bit.

When software writes 1h to a bit in this register, CQE updates the value to 1h, and starts clearing the data structures related to the task. CQE clears the bit fields (sets a value of 0h) in the MMCSD0_CQ_TASK_CLEAR and in MMCSD0_CQ_TASK_DOOR_BELL registers once clear operation is complete.

Software should poll on the MMCSD0_CQ_TASK_CLEAR register until it is cleared to verify clear operation was complete.

Writing to this register only clears the task in the CQE and does not have impact on the device. In order to discard the task in the device, host software shall send CMDQ_TASK _MGMT while CQE is still in Halt state.

Host driver is not allowed to use this register to clear multiple tasks at the same time. Clearing multiple tasks can be done using MMCSD0_CQ_CONTROL register.

Writing 0h to a register bit shall have no impact.

6.6.4.91 MMCSD0_CQ_SEND_STS_CONFIG1 Register (Offset = 240h) [reset = 11000h]

MMCSD0_CQ_SEND_STS_CONFIG1 is shown in Figure 12-2405 and described in Table 12-4663.

Return to Summary Table.

The register controls when the SEND_QUEUE_STATUS commands are sent.

Table 12-4662 MMCSD0_CQ_SEND_STS_CONFIG1 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0240h
Figure 12-2405 MMCSD0_CQ_SEND_STS_CONFIG1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED CMD_BLK_CNTR
R-0h R/W-1h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD_IDLE_TIMER
R/W-1000h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4663 MMCSD0_CQ_SEND_STS_CONFIG1 Register Field Descriptions
Bit Field Type Reset Description
31-20 RESERVED R 0h

Reserved
19-16 CMD_BLK_CNTR R/W 1h

Send Status Command Block Counter

This field indicates to CQE when to send SEND_QUEUE_STATUS (CMD13) command to inquire the status of the devices task queue.

A value of n means CQE shall send status command on the CMD line, during the transfer of data block BLOCK_CNT-n, on the data lines, where BLOCK_CNT is the number of blocks in the current transaction.

A value of 0h means that SEND_QUEUE_STATUS (CMD13) command shall not be sent during the transaction. Instead it will be sent only when the data lines are idle.

A value of 1 means that STATUS command is to be sent during the last block of the transaction.
15-0 CMD_IDLE_TIMER R/W 1000h

Send Status Command Idle Timer

This field indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS (CMD13) polling.

Periodic polling is used when tasks are pending in the device, but no data transfer is in progress. When a SEND_QUEUE_STATUS response indicating that no task is ready for execution, CQE counts the configured time until it issues the next SEND_QUEUE_STATUS.

Timer units are clock periods of theclock whose frequency is specified in the Internal Timer Clock Frequency field in the MMCSD0_CQ_CAPABILITIES register.

The minimum value is 1h (1 clock period) and the maximum value is FFFFh (65535 clock periods). Default interval is: 4096 clock periods.

For example, a MMCSD0_CQ_CAPABILITIES field value of 0h indicates a 19.2 MHz clock frequency (period = 52.08 ns).

6.6.4.92 MMCSD0_CQ_SEND_STS_CONFIG2 Register (Offset = 244h) [reset = 0h]

MMCSD0_CQ_SEND_STS_CONFIG2 is shown in Figure 12-2406 and described in Table 12-4665.

Return to Summary Table.

This register is used for 333 configuring RCA field in SEND_QUEUE_STATUS command argument.

Table 12-4664 MMCSD0_CQ_SEND_STS_CONFIG2 Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0244h
Figure 12-2406 MMCSD0_CQ_SEND_STS_CONFIG2 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED QUEUE_RCA
R-0h R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 12-4665 MMCSD0_CQ_SEND_STS_CONFIG2 Register Field Descriptions
Bit Field Type Reset Description
31-16 RESERVED R 0h

Reserved
15-0 QUEUE_RCA R/W 0h

Send Queue RCA

This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument.

CQE shall copy this field to bits 31-16 of the argument when transmitting SEND_QUEUE_STATUS (CMD13) command.

6.6.4.93 MMCSD0_CQ_DCMD_RESPONSE Register (Offset = 248h) [reset = 0h]

MMCSD0_CQ_DCMD_RESPONSE is shown in Figure 12-2407 and described in Table 12-4667.

Return to Summary Table.

This register is used for passing the response of a DCMD task to software.

Table 12-4666 MMCSD0_CQ_DCMD_RESPONSE Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0248h
Figure 12-2407 MMCSD0_CQ_DCMD_RESPONSE Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST_RESP
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4667 MMCSD0_CQ_DCMD_RESPONSE Register Field Descriptions
Bit Field Type Reset Description
31-0 LAST_RESP R 0h

Direct Command Last Response

This register contains the response of the command generated by the last direct command (DCMD) task which was sent.

CQE shall update this register when it receives the response for a DCMD task.

This register is considered valid only after bit 31 of the MMCSD0_CQ_TASK_DOOR_BELL register is cleared by CQE.

6.6.4.94 MMCSD0_CQ_RESP_ERR_MASK Register (Offset = 250h) [reset = FDF9A080h]

MMCSD0_CQ_RESP_ERR_MASK is shown in Figure 12-2408 and described in Table 12-4669.

Return to Summary Table.

This register controls the generation of Response Error Detection (RED) interrupt.

Table 12-4668 MMCSD0_CQ_RESP_ERR_MASK Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0250h
Figure 12-2408 MMCSD0_CQ_RESP_ERR_MASK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CQRMEM
R-FDF9A080h
LEGEND: R = Read Only; -n = value after reset
Table 12-4669 MMCSD0_CQ_RESP_ERR_MASK Register Field Descriptions
Bit Field Type Reset Description
31-0 CQRMEM R FDF9A080h

Response Mode Error Mask

This bit is used as in interrupt mask on the device status field which is received in R1/R1b responses.

Bit Value Description (for any bit i):

1h: When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated

0h: When a R1/R1b response is received, bit i in the device status is ignored

The reset value of this register is set to trigger an interrupt on all "Error" type bits in the device status.

Note: Responses to CMD13 (SQS) encode the QSR, so they are ignored by this logic.

6.6.4.95 MMCSD0_CQ_TASK_ERR_INFO Register (Offset = 254h) [reset = 0h]

MMCSD0_CQ_TASK_ERR_INFO is shown in Figure 12-2409 and described in Table 12-4671.

Return to Summary Table.

This register is updated by CQE when an error occurs on data or command related to a task activity. When such error is detected by CQE or indicated by the eMMC controller CQE stores in the MMCSD0_CQ_TASK_ERR_INFO register the task IDs and the command indices of the commands which were executed on the 343 command line and data lines when the error occurred.

Software is expected to use this information in the error recovery procedure.

Table 12-4670 MMCSD0_CQ_TASK_ERR_INFO Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0254h
Figure 12-2409 MMCSD0_CQ_TASK_ERR_INFO Register
31 30 29 28 27 26 25 24
DATERR_VALID RESERVED DATERR_TASK_ID
R-0h R-0h R-0h
23 22 21 20 19 18 17 16
RESERVED DATERR_CMD_INDEX
R-0h R-0h
15 14 13 12 11 10 9 8
RESP_MODE_VALID RESERVED RESP_MODE_TASK_ID
R-0h R-0h R-0h
7 6 5 4 3 2 1 0
RESERVED RESP_MODE_CMD_INDEX
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4671 MMCSD0_CQ_TASK_ERR_INFO Register Field Descriptions
Bit Field Type Reset Description
31 DATERR_VALID R 0h

Data Transfer Error Fields Valid

This bit is updated when an error is detected by CQE, or indicated by eMMC controller.

If a data transfer is in progress when the error is detected/indicated, the bit is set to 1h.

If a no data transfer is in progress when the error is detected/indicated, the bit is cleared to 0h.
30-29 RESERVED R 0h

Reserved
28-24 DATERR_TASK_ID R 0h

Data Transfer Error Task ID

This field indicates the ID of the task which was executed on the data lines when an error occurred.

The field is updated if a data transfer is in progress when an error is detected by CQE, or indicated by eMMC controller.
23-22 RESERVED R 0h

Reserved
21-16 DATERR_CMD_INDEX R 0h

Data Transfer Error Command Index

This field indicates the index of the command which was executed on the data lines when an error occurred.

The index shall be set to EXECUTE_READ_TASK (CMD46) or EXECUTE_WRITE_TASK (CMD47) according to the data direction.

The field is updated if a data transfer is in progress when an error is detected by CQE, or indicated by eMMC controller.
15 RESP_MODE_VALID R 0h

Response Mode Error Fields Valid

This bit is updated when an error is detected by CQE, or indicated by eMMC controller.

If a command transaction is in progress when the error is detected/indicated, the bit is set to 1h.

If a no command transaction is in progress when the error is detected/indicated, the bit is cleared to 0h.
14-13 RESERVED R 0h

Reserved
12-8 RESP_MODE_TASK_ID R 0h

Response Mode Error Task ID

This field indicates the ID of the task which was executed on the command line when an error occurred.

The field is updated if a command transaction is in progress when an error is detected by CQE, or indicated by eMMC controller.
7-6 RESERVED R 0h

Reserved
5-0 RESP_MODE_CMD_INDEX R 0h

Response Mode Error Command Index

This field indicates the index of the command which was executed on the command line when an error occurred.

The field is updated if a command transaction is in progress when an error is detected by CQE, or indicated by eMMC controller.

6.6.4.96 MMCSD0_CQ_CMD_RESP_INDEX Register (Offset = 258h) [reset = 0h]

MMCSD0_CQ_CMD_RESP_INDEX is shown in Figure 12-2410 and described in Table 12-4673.

Return to Summary Table.

This register stores the index of the last received command response.

Table 12-4672 MMCSD0_CQ_CMD_RESP_INDEX Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0258h
Figure 12-2410 MMCSD0_CQ_CMD_RESP_INDEX Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED LAST_CRI
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4673 MMCSD0_CQ_CMD_RESP_INDEX Register Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h

Reserved
5-0 LAST_CRI R 0h

Last Command Response Index

This field stores the index of the last received command response. CQE shall update the value every time a command response is received.

6.6.4.97 MMCSD0_CQ_CMD_RESP_ARG Register (Offset = 25Ch) [reset = 0h]

MMCSD0_CQ_CMD_RESP_ARG is shown in Figure 12-2411 and described in Table 12-4675.

Return to Summary Table.

This register stores the index of the last received command response.

Table 12-4674 MMCSD0_CQ_CMD_RESP_ARG Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 025Ch
Figure 12-2411 MMCSD0_CQ_CMD_RESP_ARG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LAST_CRA
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4675 MMCSD0_CQ_CMD_RESP_ARG Register Field Descriptions
Bit Field Type Reset Description
31-0 LAST_CRA R 0h

Last Command Response Argument

This field stores the argument of the last received command. CQE shall update the value every time a command response is received.

6.6.4.98 MMCSD0_CQ_ERROR_TASK_ID Register (Offset = 260h) [reset = 0h]

MMCSD0_CQ_ERROR_TASK_ID is shown in Figure 12-2412 and described in Table 12-4677.

Return to Summary Table.

CQ Error Task ID Register

Table 12-4676 MMCSD0_CQ_ERROR_TASK_ID Instances
Instance Physical Address
MMCSD0_CTL_CFG 04F8 0260h
Figure 12-2412 MMCSD0_CQ_ERROR_TASK_ID Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TERR_ID
R-0h R-0h
LEGEND: R = Read Only; -n = value after reset
Table 12-4677 MMCSD0_CQ_ERROR_TASK_ID Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h

Reserved
4-0 TERR_ID R 0h

Task Error ID