SPRUIU1C July   2020  – February 2024 DRA821U , DRA821U-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Related Documentation From Texas Instruments
    3.     Support Resources
    4.     Glossary
    5.     Export Control Notice
    6.     Trademarks
  3. 1 Introduction
    1. 1.1 Device Overview
    2. 1.2 Device Block Diagram
    3. 1.3 Device Main Domain
      1. 1.3.1  Arm Cortex-A72 Subsystem
      2. 1.3.2  Arm Cortex-R5F Processor
      3. 1.3.3  Navigator Subsystem
      4. 1.3.4  Region-based Address Translation Module
      5. 1.3.5  Multicore Shared Memory Controller
      6. 1.3.6  DDR Subsystem
      7. 1.3.7  General Purpose Input/Output Interface
      8. 1.3.8  Inter-Integrated Circuit Interface
      9. 1.3.9  Improved Inter-Integrated Circuit Interface
      10. 1.3.10 Multi-channel Serial Peripheral Interface
      11. 1.3.11 Universal Asynchronous Receiver/Transmitter
      12. 1.3.12 Gigabit Ethernet Switch
      13. 1.3.13 Peripheral Component Interconnect Express Subsystem
      14. 1.3.14 Universal Serial Bus (USB) Subsystem
      15. 1.3.15 SerDes
      16. 1.3.16 General Purpose Memory Controller with Error Location Module
      17. 1.3.17 Multimedia Card/Secure Digital Interface
      18. 1.3.18 Enhanced Capture Module
      19. 1.3.19 Enhanced Pulse-Width Modulation Module
      20. 1.3.20 Enhanced Quadrature Encoder Pulse Module
      21. 1.3.21 Controller Area Network
      22. 1.3.22 Audio Tracking Logic
      23. 1.3.23 Multi-channel Audio Serial Port
      24. 1.3.24 Timers
      25. 1.3.25 Internal Diagnostics Modules
    4. 1.4 Device MCU Domain
      1. 1.4.1  MCU Arm Cortex-R5F Processor
      2. 1.4.2  MCU Region-based Address Translation Module
      3. 1.4.3  MCU Navigator Subsystem
      4. 1.4.4  MCU Analog-to-Digital Converter
      5. 1.4.5  MCU Inter-Integrated Circuit Interface
      6. 1.4.6  MCU Improved Inter-Integrated Circuit Interface
      7. 1.4.7  MCU Multi-channel Serial Peripheral Interface
      8. 1.4.8  MCU Universal Asynchronous Receiver/Transmitter
      9. 1.4.9  MCU Gigabit Ethernet Switch
      10. 1.4.10 MCU Octal Serial Peripheral Interface and HyperBus Memory Controller as a Flash Subsystem
      11. 1.4.11 MCU Controller Area Network
      12. 1.4.12 MCU Timers
      13. 1.4.13 MCU Internal Diagnostics Modules
    5. 1.5 Device WKUP Domain
      1. 1.5.1 WKUP Device Management and Security Controller
      2. 1.5.2 WKUP General Purpose Input/Output Interface
      3. 1.5.3 WKUP Inter-Integrated Circuit Interface
      4. 1.5.4 WKUP Universal Asynchronous Receiver/Transmitter
      5. 1.5.5 WKUP Internal Diagnostics Modules
    6. 1.6 Device Identification
  4. 2 Memory Map
    1. 2.1 MAIN Domain Memory Map
    2. 2.2 MCU Domain Memory Map
    3. 2.3 WKUP Domain Memory Map
    4. 2.4 Processors View Memory Map
    5. 2.5 Region-based Address Translation
  5. 3 System Interconnect
    1. 3.1 System Interconnect Overview
    2. 3.2 System Interconnect Integration
      1. 3.2.1 Interconnect Integration in WKUP Domain
      2. 3.2.2 Interconnect Integration in MCU Domain
      3. 3.2.3 Interconnect Integration in MAIN Domain
    3. 3.3 System Interconnect Functional Description
      1. 3.3.1 Master-Slave Connections
      2. 3.3.2 Quality of Service (QoS)
      3. 3.3.3 Route ID
      4. 3.3.4 Initiator-Side Security Controls and Firewalls
        1. 3.3.4.1 Initiator-Side Security Controls (ISC)
          1. 3.3.4.1.1 Special System Level Priv-ID
          2. 3.3.4.1.2 Priv ID and ISC Assignment
        2. 3.3.4.2 Firewalls (FW)
          1. 3.3.4.2.1 Peripheral Firewalls (FW)
          2. 3.3.4.2.2 Memory or Region-based Firewalls
            1. 3.3.4.2.2.1 Region Based Firewall Functional Description
          3. 3.3.4.2.3 Channelized Firewalls
            1. 3.3.4.2.3.1 Channelized Firewall Functional Description
      5. 3.3.5 Null Error Reporting
      6. 3.3.6 VBUSM_TIMEOUT_GASKET (MCU_TIMEOUT_64B2)
        1. 3.3.6.1 Overview and Feature List
          1. 3.3.6.1.1 Features Supported
          2. 3.3.6.1.2 Features Not Supported
        2. 3.3.6.2 Functional Description
          1. 3.3.6.2.1 Functional Operation
            1. 3.3.6.2.1.1  Overview
            2. 3.3.6.2.1.2  FIFOs
            3. 3.3.6.2.1.3  ID Allocator
            4. 3.3.6.2.1.4  Timer
            5. 3.3.6.2.1.5  Timeout Queue
            6. 3.3.6.2.1.6  Write Scoreboard
            7. 3.3.6.2.1.7  Read Scoreboard
            8. 3.3.6.2.1.8  Flush Mode
            9. 3.3.6.2.1.9  Flushing
            10. 3.3.6.2.1.10 Timeout Error Reporting
            11. 3.3.6.2.1.11 Command Timeout Error Reporting
            12. 3.3.6.2.1.12 Unexpected Response Reporting
            13. 3.3.6.2.1.13 Latency and Stalls
            14. 3.3.6.2.1.14 Bypass
            15. 3.3.6.2.1.15 Safety
        3. 3.3.6.3 Interrupt Conditions
          1. 3.3.6.3.1 Transaction Error Interrupt
            1. 3.3.6.3.1.1 Transaction Timeout
            2. 3.3.6.3.1.2 Unexpected Response
            3. 3.3.6.3.1.3 Command Timeout
        4. 3.3.6.4 Memory Map
          1. 3.3.6.4.1  Revision Register (Base Address + 0x00)
          2. 3.3.6.4.2  Configuration Register (Base Address + 0x04)
          3. 3.3.6.4.3  Info Register (Base Address + 0x08)
          4. 3.3.6.4.4  Enable Register (Base Address + 0x0C)
          5. 3.3.6.4.5  Flush Register (Base Address + 0x10)
          6. 3.3.6.4.6  Timeout Value Register (Base Address + 0x14)
          7. 3.3.6.4.7  Timer Register (Base Address + 0x18)
          8. 3.3.6.4.8  Error Interrupt Raw Status/Set Register (Base Address + 0x20)
          9. 3.3.6.4.9  Error Interrupt Enabled Status/Clear Register (Base Address + 0x24)
          10. 3.3.6.4.10 Error Interrupt Mask Set Register (Base Address + 0x28)
          11. 3.3.6.4.11 Error Interrupt Mask Clear Register (Base Address + 0x2C)
          12. 3.3.6.4.12 Timeout Error Info Register (Base Address + 0x30)
          13. 3.3.6.4.13 Unexpected Response Info Register (Base Address + 0x34)
          14. 3.3.6.4.14 Error Transaction Valid/Dir/RouteID Register (Base Address + 0x38)
          15. 3.3.6.4.15 Error Transaction Tag/CommandID Register (Base Address + 0x3C)
          16. 3.3.6.4.16 Error Transaction Bytecnt Register (Base Address + 0x40)
          17. 3.3.6.4.17 Error Transaction Upper Address Register (Base Address + 0x44)
          18. 3.3.6.4.18 Error Transaction Lower Address Register (Base Address + 0x48)
        5. 3.3.6.5 Integration Overview
          1. 3.3.6.5.1 Parameterization Requirements
        6. 3.3.6.6 I/O Description
          1. 3.3.6.6.1 Clockstop Idle
          2. 3.3.6.6.2 Flush
          3. 3.3.6.6.3 Module I/O
        7. 3.3.6.7 User’s Guide
          1. 3.3.6.7.1 Programmer’s Guide
            1. 3.3.6.7.1.1 Initialization
            2. 3.3.6.7.1.2 Software Flush
      7. 3.3.7 Timeout Gasket (TOG)
    4. 3.4 System Interconnect Registers
      1. 3.4.1 QoS Registers
      2. 3.4.2 Firewall Exception Registers
      3. 3.4.3 Firewall Region Registers
      4. 3.4.4 Null Error Reporting Registers
  6. 4 Initialization
    1. 4.1 Initialization Overview
      1. 4.1.1 ROM Code Overview
      2. 4.1.2 Bootloader Modes
      3. 4.1.3 Terminology
    2. 4.2 Boot Process
      1. 4.2.1 MCU ROM Code Architecture
        1. 4.2.1.1 Main Module
        2. 4.2.1.2 X509 Module
        3. 4.2.1.3 Buffer Manager Module
        4. 4.2.1.4 Log and Trace Module
        5. 4.2.1.5 System Module
        6. 4.2.1.6 Protocol Module
        7. 4.2.1.7 Driver Module
      2. 4.2.2 DMSC ROM Description
      3. 4.2.3 Boot Process Flow
      4. 4.2.4 MCU Only vs Normal Boot
    3. 4.3 Boot Mode Pins
      1. 4.3.1  MCU_BOOTMODE Pin Mapping
      2. 4.3.2  BOOTMODE Pin Mapping
        1. 4.3.2.1 Primary Boot Mode Selection
        2. 4.3.2.2 Backup Boot Mode Selection When MCU Only = 0
        3. 4.3.2.3 Primary Boot Mode Configuration
        4. 4.3.2.4 Backup Boot Mode Configuration
      3. 4.3.3  No-boot/Dev-boot Configuration
      4. 4.3.4  Hyperflash Boot Device Configuration
      5. 4.3.5  OSPI Boot Device Configuration
      6. 4.3.6  QSPI Boot Device Configuration
      7. 4.3.7  SPI Boot Device Configuration
      8. 4.3.8  xSPI Boot Device Configuration
      9. 4.3.9  I2C Boot Device Configuration
      10. 4.3.10 MMC/SD Card Boot Device Configuration
      11. 4.3.11 eMMC Boot Device Configuration
      12. 4.3.12 Ethernet Boot Device Configuration
      13. 4.3.13 USB Boot Device Configuration
      14. 4.3.14 PCIe Boot Device Configuration
      15. 4.3.15 UART Boot Device Configuration
      16. 4.3.16 PLL Configuration
        1. 4.3.16.1 MCU_PLL0, MCU_PLL2, Main PLL0, and Main PLL3
        2. 4.3.16.2 MCU_PLL1
        3. 4.3.16.3 Main PLL1
        4. 4.3.16.4 Main PLL2
        5. 4.3.16.5 HSDIV Values
        6. 4.3.16.6 190
    4. 4.4 Boot Parameter Tables
      1. 4.4.1  Common Header
      2. 4.4.2  PLL Setup
      3. 4.4.3  PCIe Boot Parameter Table
      4. 4.4.4  I2C Boot Parameter Table
      5. 4.4.5  OSPI/QSPI/SPI Boot Parameter Table
      6. 4.4.6  Ethernet Boot Parameter Table
      7. 4.4.7  USB Boot Parameter Table
      8. 4.4.8  MMCSD Boot Parameter Table
      9. 4.4.9  UART Boot Parameter Table
      10. 4.4.10 Hyperflash Boot Parameter Table
    5. 4.5 Boot Image Format
      1. 4.5.1 Overall Structure
      2. 4.5.2 X.509 Certificate
      3. 4.5.3 Organizational Identifier (OID)
      4. 4.5.4 X.509 Extensions Specific to Boot
        1. 4.5.4.1 Boot Info (OID 1.3.6.1.4.1.294.1.1)
        2. 4.5.4.2 Image Integrity (OID 1.3.6.1.4.1.294.1.2)
      5. 4.5.5 Extended Boot Info Extension
        1. 4.5.5.1 Impact on HS Device
        2. 4.5.5.2 Extended Boot Info Details
        3. 4.5.5.3 Certificate / Component Types
        4. 4.5.5.4 Extended Boot Encryption Info
        5. 4.5.5.5 Component Ordering
        6. 4.5.5.6 Memory Load Sections Overlap with Executable Components
        7. 4.5.5.7 Device Type and Extended Boot Extension
      6. 4.5.6 Generating X.509 Certificates
        1. 4.5.6.1 Key Generation
          1. 4.5.6.1.1 Degenerate RSA Keys
        2. 4.5.6.2 Configuration Script
      7. 4.5.7 Image Data
    6. 4.6 Boot Modes
      1. 4.6.1 I2C Bootloader Operation
        1. 4.6.1.1 I2C Initialization Process
          1. 4.6.1.1.1 Block Size
          2. 4.6.1.1.2 226
        2. 4.6.1.2 I2C Loading Process
          1. 4.6.1.2.1 Loading a Boot Image From EEPROM
      2. 4.6.2 SPI Bootloader Operation
        1. 4.6.2.1 SPI Initialization Process
        2. 4.6.2.2 SPI Loading Process
      3. 4.6.3 QSPI Bootloader Operation
        1. 4.6.3.1 QSPI Initialization Process
        2. 4.6.3.2 QSPI Loading Process
      4. 4.6.4 OSPI Bootloader Operation
        1. 4.6.4.1 OSPI Initialization Process
        2. 4.6.4.2 OSPI Loading Process
      5. 4.6.5 PCIe Bootloader Operation
        1. 4.6.5.1 PCIe Initialization Process
        2. 4.6.5.2 PCIe Loading Process
      6. 4.6.6 Ethernet Bootloader Operation
        1. 4.6.6.1 Ethernet Initialization Process
        2. 4.6.6.2 Ethernet Loading Process
          1. 4.6.6.2.1 Ethernet Boot Data Formats
            1. 4.6.6.2.1.1 Limitations
            2. 4.6.6.2.1.2 BOOTP Request
              1. 4.6.6.2.1.2.1 MAC Header (DIX)
              2. 4.6.6.2.1.2.2 IPv4 Header
              3. 4.6.6.2.1.2.3 UDP Header
              4. 4.6.6.2.1.2.4 BOOTP Payload
              5. 4.6.6.2.1.2.5 TFTP
        3. 4.6.6.3 Ethernet Hand Over Process
      7. 4.6.7 USB Bootloader Operation
        1. 4.6.7.1 USB-Specific Attributes
          1. 4.6.7.1.1 DFU Device Mode
      8. 4.6.8 MMCSD Bootloader Operation
      9. 4.6.9 UART Bootloader Operation
        1. 4.6.9.1 Initialization Process
        2. 4.6.9.2 UART Loading Process
          1. 4.6.9.2.1 UART XMODEM
        3. 4.6.9.3 UART Hand-Over Process
    7. 4.7 Boot Memory Maps
      1. 4.7.1 Memory Layout/MPU
      2. 4.7.2 Global Memory Addresses Used by ROM Code
      3. 4.7.3 Memory Reserved by ROM Code
  7. 5 Device Configuration
    1. 5.1 Control Module (CTRL_MMR)
      1. 5.1.1 WKUP_CTRL_MMR0
        1. 5.1.1.1 WKUP_CTRL_MMR0 Overview
        2. 5.1.1.2 WKUP_CTRL_MMR0 Integration
        3. 5.1.1.3 WKUP_CTRL_MMR0 Functional Description
          1. 5.1.1.3.1 Description for WKUP_CTRL_MMR0 Register Types
            1. 5.1.1.3.1.1  Pad Configuration Registers
            2. 5.1.1.3.1.2  Kick Protection Registers
            3. 5.1.1.3.1.3  WKUP_CTRL_MMR0 Module Interrupts
            4. 5.1.1.3.1.4  Clock Selection Registers
            5. 5.1.1.3.1.5  Device Feature Registers
            6. 5.1.1.3.1.6  POK Module Registers
            7. 5.1.1.3.1.7  Power and Reset Related Registers
            8. 5.1.1.3.1.8  PRG Related Registers
            9. 5.1.1.3.1.9  Voltage Glitch Detect Control and Status Registers
            10. 5.1.1.3.1.10 I/O Debounce Control Registers
        4. 5.1.1.4 WKUP_CTRL_MMR0 Registers
      2. 5.1.2 MCU_CTRL_MMR0
        1. 5.1.2.1 MCU_CTRL_MMR0 Overview
        2. 5.1.2.2 MCU_CTRL_MMR0 Integration
        3. 5.1.2.3 MCU_CTRL_MMR0 Functional Description
          1. 5.1.2.3.1 Description for MCU_CTRL_MMR0 Register Types
            1. 5.1.2.3.1.1 Kick Protection Registers
            2. 5.1.2.3.1.2 MCU_CTRL_MMR0 Module Interrupts
            3. 5.1.2.3.1.3 Inter-processor Communication Registers
            4. 5.1.2.3.1.4 Timer I/O Muxing Control Registers
            5. 5.1.2.3.1.5 Clock Muxing and Division Registers
            6. 5.1.2.3.1.6 MCU_CPSW0 MAC Address Registers
        4. 5.1.2.4 MCU_CTRL_MMR0 Registers
        5. 5.1.2.5 MCU_SEC_MMR0_DBG_CTRL Registers
        6. 5.1.2.6 MCU_SEC_MMR0_BOOT_CTRL Registers
      3. 5.1.3 CTRL_MMR0
        1. 5.1.3.1 CTRL_MMR0 Overview
        2. 5.1.3.2 CTRL_MMR0 Integration
        3. 5.1.3.3 CTRL_MMR0 Functional Description
          1. 5.1.3.3.1 Description for CTRL_MMR0 Register Types
            1. 5.1.3.3.1.1  Pad Configuration Registers
            2. 5.1.3.3.1.2  Kick Protection Registers
            3. 5.1.3.3.1.3  CTRL_MMR0 Module Interrupts
            4. 5.1.3.3.1.4  Inter-processor Communication Registers
            5. 5.1.3.3.1.5  Timer I/O Muxing Control Registers
            6. 5.1.3.3.1.6  EHRPWM/EQEP Control and Status Registers
            7. 5.1.3.3.1.7  Clock Muxing and Division Registers
            8. 5.1.3.3.1.8  Ethernet Port Operation Control Registers
            9. 5.1.3.3.1.9  SERDES Lane Function Control Registers
            10. 5.1.3.3.1.10 DDRSS Dynamic Frequency Change Registers
        4. 5.1.3.4 CTRL_MMR0 Registers
        5. 5.1.3.5 SEC_MMR0_DBG_CTRL Registers
        6. 5.1.3.6 SEC_MMR0_BOOT_CTRL Registers
    2. 5.2 Power
      1. 5.2.1 Power Management Overview
      2. 5.2.2 Power Management Subsystems
        1. 5.2.2.1 Power Subsystems Overview
          1. 5.2.2.1.1 POK Overview
          2. 5.2.2.1.2 PRG / PRG_PP Overview
          3. 5.2.2.1.3 POR Overview
          4. 5.2.2.1.4 POK / PRG(_PP) /POR Overview
          5. 5.2.2.1.5 Timing
          6. 5.2.2.1.6 Restrictions
        2. 5.2.2.2 Power System Modules
          1. 5.2.2.2.1 Power OK (POK) Modules
            1. 5.2.2.2.1.1 POK Programming Model
              1. 5.2.2.2.1.1.1 POK Threshold Setting Programming Sequence
          2. 5.2.2.2.2 Power on Reset (POR) Module
            1. 5.2.2.2.2.1 POR Overview
            2. 5.2.2.2.2.2 POR Integration
            3. 5.2.2.2.2.3 POR Programming Model
          3. 5.2.2.2.3 PoR/Reset Generator (PRG_PP) Modules
            1. 5.2.2.2.3.1 PRG_PP Overview
            2. 5.2.2.2.3.2 PRG_PP Integration
            3. 5.2.2.2.3.3 PRG_PP Programming Model
          4. 5.2.2.2.4 Power Glitch Detect (PGD) Modules
          5. 5.2.2.2.5 Voltage and Thermal Manager (VTM)
            1. 5.2.2.2.5.1 VTM Overview
              1. 5.2.2.2.5.1.1 VTM Features
              2. 5.2.2.2.5.1.2 VTM Not Supported Features
            2. 5.2.2.2.5.2 VTM Integration
            3. 5.2.2.2.5.3 VTM Functional Description
              1. 5.2.2.2.5.3.1 VTM Temperature Status and Thermal Management
                1. 5.2.2.2.5.3.1.1 10-bit Temperature Values Versus Temperature
              2. 5.2.2.2.5.3.2 VTM Temperature Driven Alerts and Interrupts
              3. 5.2.2.2.5.3.3 VTM VID Voltage Domains
              4. 5.2.2.2.5.3.4 VTM Clocking
              5. 5.2.2.2.5.3.5 VTM Retention Interface
              6. 5.2.2.2.5.3.6 VTM ECC Aggregator
              7. 5.2.2.2.5.3.7 VTM Programming Model
                1. 5.2.2.2.5.3.7.1 VTM Maximum Temperature Outrange Alert
                2. 5.2.2.2.5.3.7.2 Temperature Monitor during Low Power Modes
                3. 5.2.2.2.5.3.7.3 Sensors Programming Sequences
              8. 5.2.2.2.5.3.8 AVS-Class0
          6. 5.2.2.2.6 Distributed Power Clock and Reset Controller (DPCR)
        3. 5.2.2.3 Power Control Modules
          1. 5.2.2.3.1 Power Sleep Controller and Local Power Sleep Controllers
            1. 5.2.2.3.1.1 PSC Terminology
            2. 5.2.2.3.1.2 PSC Features
            3. 5.2.2.3.1.3 PSC: Device Power-Management Layout
              1. 5.2.2.3.1.3.1 WKUP_PSC0 Device-Specific Information
              2. 5.2.2.3.1.3.2 PSC0 Device-Specific Information
              3. 5.2.2.3.1.3.3 LPSC Dependences Overview
            4. 5.2.2.3.1.4 PSC: Power Domain and Module States
              1. 5.2.2.3.1.4.1 Power Domain States
              2. 5.2.2.3.1.4.2 Module States
              3. 5.2.2.3.1.4.3 Local Reset
            5. 5.2.2.3.1.5 PSC: Executing State Transitions
              1. 5.2.2.3.1.5.1 Power Domain State Transitions
              2. 5.2.2.3.1.5.2 Module State Transitions
              3. 5.2.2.3.1.5.3 Concurrent Power Domain/Module State Transitions
              4. 5.2.2.3.1.5.4 Recommendations for Power Domain/Module Sequencing
            6. 5.2.2.3.1.6 PSC: Emulation Support in the PSC
            7. 5.2.2.3.1.7 PSC: A72SS, MSMC, MCU Cortex-R5F, C71SS0, and C66SS Subsystem Power-Up and Power-Down Sequences
              1. 5.2.2.3.1.7.1 ARMi_COREn Power State Transition
              2. 5.2.2.3.1.7.2 A72SS Power State Transition
              3. 5.2.2.3.1.7.3 GIC0 Sequencing to Support A72SS Power Management
              4. 5.2.2.3.1.7.4 MSMC0 Clkstop/Powerdown/Disconnect Sequencing
              5. 5.2.2.3.1.7.5 MCU Cortex-R5F Power Modes
          2. 5.2.2.3.2 Integrated Power Management (DMSC)
            1. 5.2.2.3.2.1 DMSC Power Management Overview
              1. 5.2.2.3.2.1.1 DMSC Power Management Features
      3. 5.2.3 Device Power States
        1. 5.2.3.1 Overview of Device Low-Power Modes
        2. 5.2.3.2 Voltage Domains
        3. 5.2.3.3 Power Domains
        4. 5.2.3.4 Clock Sources States
        5. 5.2.3.5 Wake-up Sources
        6. 5.2.3.6 Device Power States and Transitions
          1. 5.2.3.6.1 LPM Entry Sequences
          2. 5.2.3.6.2 LPM Exit Sequences
          3. 5.2.3.6.3 IO Retention
          4. 5.2.3.6.4 DDRSS Self-Refresh
      4. 5.2.4 Dynamic Power Management
        1. 5.2.4.1 AVS Support
        2. 5.2.4.2 Dynamic Frequency Scaling (DFS) Operations
      5. 5.2.5 Thermal Management
      6. 5.2.6 Registers
        1. 5.2.6.1 WKUP_VTM0 Registers
        2. 5.2.6.2 PSC Registers
    3. 5.3 Reset
      1. 5.3.1 Reset Overview
      2. 5.3.2 Reset Sources
      3. 5.3.3 Reset Status
      4. 5.3.4 Reset Control
      5. 5.3.5 BOOTMODE Pins
      6. 5.3.6 Reset Sequences
        1. 5.3.6.1 MCU_PORz Overview
        2. 5.3.6.2 MCU_PORz Sequence
        3. 5.3.6.3 MCU_RESETz Sequence
        4. 5.3.6.4 PORz Sequence
        5. 5.3.6.5 RESET_REQz Sequence
      7. 5.3.7 PLL Behavior on Reset
    4. 5.4 Clocking
      1. 5.4.1 Overview
      2. 5.4.2 Clock Inputs
        1. 5.4.2.1 Overview
        2. 5.4.2.2 Mapping of Clock Inputs
      3. 5.4.3 Clock Outputs
        1. 5.4.3.1 Observation Clock Pins
          1. 5.4.3.1.1 MCU_OBSCLK0 Pin
          2. 5.4.3.1.2 424
          3. 5.4.3.1.3 OBSCLK0, OBSCLK1, and OBSCLK2 Pins
        2. 5.4.3.2 System Clock Pins
          1. 5.4.3.2.1 MCU_SYSCLKOUT0
          2. 5.4.3.2.2 SYSCLKOUT0
      4. 5.4.4 Device Oscillators
        1. 5.4.4.1 Device Oscillators Integration
          1. 5.4.4.1.1 Oscillators with External Crystal
          2. 5.4.4.1.2 Internal RC Oscillator
        2. 5.4.4.2 Oscillator Clock Loss Detection
      5. 5.4.5 PLLs
        1. 5.4.5.1 WKUP and MCU Domains PLL Overview
        2. 5.4.5.2 MAIN Domain PLLs Overview
        3. 5.4.5.3 PLL Reference Clocks
          1. 5.4.5.3.1 PLLs in MCU Domain
          2. 5.4.5.3.2 PLLs in MAIN Domain
        4. 5.4.5.4 Generic PLL Overview
          1. 5.4.5.4.1 PLLs Output Clocks Parameters
            1. 5.4.5.4.1.1 PLLs Input Clocks
            2. 5.4.5.4.1.2 PLL Output Clocks
              1. 5.4.5.4.1.2.1 PLLTS16FFCLAFRAC2 Type Output Clocks
              2. 5.4.5.4.1.2.2 PLLTS16FFCLAFRACF Type Output Clocks
              3. 5.4.5.4.1.2.3 PLL Lock
              4. 5.4.5.4.1.2.4 HSDIVIDER
              5. 5.4.5.4.1.2.5 ICG Module
              6. 5.4.5.4.1.2.6 PLL Power Down
              7. 5.4.5.4.1.2.7 PLL Calibration
          2. 5.4.5.4.2 PLL Spread Spectrum Modulation Module
            1. 5.4.5.4.2.1 Definition of SSMOD
            2. 5.4.5.4.2.2 SSMOD Configuration
        5. 5.4.5.5 PLLs Device-Specific Information
          1. 5.4.5.5.1 SSMOD Related Bitfields Table
          2. 5.4.5.5.2 Clock Synthesis Inputs to the PLLs
          3. 5.4.5.5.3 Clock Output Parameter
          4. 5.4.5.5.4 Calibration Related Bitfields
        6. 5.4.5.6 PLL and PLL Controller Connection
        7. 5.4.5.7 PLL, PLLCTRL, and HSDIV Controllers Programming Guide
          1. 5.4.5.7.1 PLL Initialization
            1. 5.4.5.7.1.1 Kick Protection Mechanism
            2. 5.4.5.7.1.2 PLL Initialization to PLL Mode
            3. 5.4.5.7.1.3 PLL Programming Requirements
          2. 5.4.5.7.2 HSDIV PLL Programming
          3. 5.4.5.7.3 PLL Controllers Programming - Dividers PLLDIVn and GO Operation
            1. 5.4.5.7.3.1 GO Operation
            2. 5.4.5.7.3.2 Software Steps to Modify PLLDIV Ratios
          4. 5.4.5.7.4 Entire Sequence for Programming PLLCTRL, HSDIV, and PLL
      6. 5.4.6 Registers
        1. 5.4.6.1 MCU_PLL0_CFG Registers
        2. 5.4.6.2 PLL0_CFG Registers
        3. 5.4.6.3 PLLCTRL0 Registers
  8. 6 Processors and Accelerators
    1. 6.1 Compute Cluster
      1. 6.1.1 Compute Cluster Overview
      2. 6.1.2 Compute Cluster Functional Description
        1. 6.1.2.1 Compute Cluster Memory Regions
        2. 6.1.2.2 Compute Cluster Firewalls
        3. 6.1.2.3 Compute Cluster ECC Aggregators
      3. 6.1.3 Compute Cluster Registers
    2. 6.2 Dual-A72 MPU Subsystem
      1. 6.2.1 A72SS Overview
        1. 6.2.1.1 A72SS Introduction
        2. 6.2.1.2 A72SS Features
      2. 6.2.2 A72SS Integration
      3. 6.2.3 A72SS Functional Description
        1. 6.2.3.1  A72SS Block Diagram
        2. 6.2.3.2  A72SS A72 Cluster
        3. 6.2.3.3  A72SS Interfaces and Async Bridges
        4. 6.2.3.4  A72SS Interrupts
          1. 6.2.3.4.1 A72SS Interrupt Inputs
          2. 6.2.3.4.2 A72SS Interrupt Outputs
        5. 6.2.3.5  A72SS Power Management, Clocking and Reset
          1. 6.2.3.5.1 A72SS Power Management
          2. 6.2.3.5.2 A72SS Clocking
        6. 6.2.3.6  A72SS Debug Support
        7. 6.2.3.7  A72SS Timestamps
        8. 6.2.3.8  A72SS Watchdog
        9. 6.2.3.9  A72SS Internal Diagnostics
          1. 6.2.3.9.1 A72SS ECC Aggregators During Low Power States
          2. 6.2.3.9.2 A72SS CBASS Diagnostics
          3. 6.2.3.9.3 A72SS SRAM Diagnostics
          4. 6.2.3.9.4 A72SS SRAM ECC Aggregator Configurations
        10. 6.2.3.10 A72SS Cache Pre-Warming
        11. 6.2.3.11 A72SS Boot
        12. 6.2.3.12 A72SS IPC with Other CPUs
      4. 6.2.4 A72SS Registers
        1. 6.2.4.1 Arm A72 Cluster Registers
        2. 6.2.4.2 A72SS ECC Aggregator Registers
          1. 6.2.4.2.1 A72SS CLUSTER ECC Registers
          2. 6.2.4.2.2 A72SS CORE0 ECC Registers
          3. 6.2.4.2.3 A72SS CORE1 ECC Registers
    3. 6.3 Dual-R5F MCU Subsystem
      1. 6.3.1 R5FSS Overview
        1. 6.3.1.1 R5FSS Features
        2. 6.3.1.2 R5FSS Not Supported Features
      2. 6.3.2 R5FSS Integration
        1. 6.3.2.1 R5FSS Integration in MCU Domain
        2. 6.3.2.2 R5FSS Integration in MAIN Domain
      3. 6.3.3 R5FSS Functional Description
        1. 6.3.3.1  R5FSS Block Diagram
        2. 6.3.3.2  R5FSS Cortex-R5F Core
          1. 6.3.3.2.1 L1 Caches
          2. 6.3.3.2.2 Tightly-Coupled Memories (TCMs)
          3. 6.3.3.2.3 R5FSS Special Signals
        3. 6.3.3.3  R5FSS Interfaces
          1. 6.3.3.3.1 R5FSS Master Interfaces
          2. 6.3.3.3.2 R5FSS Slave Interfaces
        4. 6.3.3.4  R5FSS Power, Clocking and Reset
          1. 6.3.3.4.1 R5FSS Power
          2. 6.3.3.4.2 R5FSS Clocking
            1. 6.3.3.4.2.1 Changing MCU_R5FSS0 CPU Clock Frequency
          3. 6.3.3.4.3 R5FSS Reset
        5. 6.3.3.5  R5FSS Lockstep Error Detection Logic
          1. 6.3.3.5.1 CPU Output Compare Block
            1. 6.3.3.5.1.1 Operating Modes
            2. 6.3.3.5.1.2 Compare Block Active Mode
            3. 6.3.3.5.1.3 Self Test Mode
            4. 6.3.3.5.1.4 Compare Match Test
            5. 6.3.3.5.1.5 Compare Mismatch Test
            6. 6.3.3.5.1.6 Error Forcing Mode
            7. 6.3.3.5.1.7 Self Test Error Forcing Mode
          2. 6.3.3.5.2 Inactivity Monitor Block
            1. 6.3.3.5.2.1 Operating Modes
            2. 6.3.3.5.2.2 Compare Block Active Mode
            3. 6.3.3.5.2.3 Self Test Mode
            4. 6.3.3.5.2.4 Compare Match Test
            5. 6.3.3.5.2.5 Compare Mismatch Test
            6. 6.3.3.5.2.6 Error Forcing Mode
            7. 6.3.3.5.2.7 Self Test Error Forcing Mode
          3. 6.3.3.5.3 Polarity Inversion Logic
        6. 6.3.3.6  R5FSS Vectored Interrupt Manager (VIM)
          1. 6.3.3.6.1 VIM Overview
          2. 6.3.3.6.2 VIM Interrupt Inputs
          3. 6.3.3.6.3 VIM Interrupt Outputs
          4. 6.3.3.6.4 VIM Interrupt Vector Table (VIM RAM)
          5. 6.3.3.6.5 VIM Interrupt Prioritization
          6. 6.3.3.6.6 VIM ECC Support
          7. 6.3.3.6.7 VIM Lockstep Mode
          8. 6.3.3.6.8 VIM IDLE State
          9. 6.3.3.6.9 VIM Interrupt Handling
            1. 6.3.3.6.9.1 Servicing IRQ Through Vector Interface
            2. 6.3.3.6.9.2 Servicing IRQ Through MMR Interface
            3. 6.3.3.6.9.3 Servicing IRQ Through MMR Interface (Alternative)
            4. 6.3.3.6.9.4 Servicing FIQ
            5. 6.3.3.6.9.5 Servicing FIQ (Alternative)
        7. 6.3.3.7  R5FSS Region Address Translation (RAT)
          1. 6.3.3.7.1 RAT Overview
          2. 6.3.3.7.2 RAT Operation
          3. 6.3.3.7.3 RAT Error Logging
          4. 6.3.3.7.4 RAT Protection
        8. 6.3.3.8  R5FSS ECC Support
        9. 6.3.3.9  R5FSS Memory View
        10. 6.3.3.10 R5FSS Debug and Trace
        11. 6.3.3.11 R5FSS Boot Options
        12. 6.3.3.12 R5FSS Core Memory ECC Events
      4. 6.3.4 R5FSS Registers
        1. 6.3.4.1 R5FSS_CCMR5 Registers
        2. 6.3.4.2 R5FSS_CPU0_ECC_AGGR_CFG_REGS Registers
        3. 6.3.4.3 R5FSS_CPU1_ECC_AGGR_CFG_REGS Registers
        4. 6.3.4.4 R5FSS_VIM Registers
        5. 6.3.4.5 R5FSS_RAT Registers
        6. 6.3.4.6 R5FSS_EVNT_BUS_VBUSP_MMRS Registers
  9. 7 Interprocessor Communication
    1. 7.1 Mailbox
      1. 7.1.1 Mailbox Overview
        1. 7.1.1.1 Mailbox Features
        2. 7.1.1.2 Mailbox Parameters
        3. 7.1.1.3 Mailbox Not Supported Features
      2. 7.1.2 Mailbox Integration
        1. 7.1.2.1 System Mailbox Integration
      3. 7.1.3 Mailbox Functional Description
        1. 7.1.3.1 Mailbox Block Diagram
        2. 7.1.3.2 Mailbox Software Reset
        3. 7.1.3.3 Mailbox Power Management
        4. 7.1.3.4 Mailbox Interrupt Requests
        5. 7.1.3.5 Mailbox Assignment
          1. 7.1.3.5.1 Description
        6. 7.1.3.6 Sending and Receiving Messages
          1. 7.1.3.6.1 Description
        7. 7.1.3.7 Example of Communication
      4. 7.1.4 Mailbox Programming Guide
        1. 7.1.4.1 Mailbox Low-level Programming Models
          1. 7.1.4.1.1 Global Initialization
            1. 7.1.4.1.1.1 Surrounding Modules Global Initialization
            2. 7.1.4.1.1.2 Mailbox Global Initialization
              1. 7.1.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
          2. 7.1.4.1.2 Mailbox Operational Modes Configuration
            1. 7.1.4.1.2.1 Mailbox Processing modes
              1. 7.1.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
              2. 7.1.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
              3. 7.1.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
              4. 7.1.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
          3. 7.1.4.1.3 Mailbox Events Servicing
            1. 7.1.4.1.3.1 Events Servicing in Sending Mode
            2. 7.1.4.1.3.2 Events Servicing in Receiving Mode
    2. 7.2 Spinlock
      1. 7.2.1 Spinlock Overview
        1. 7.2.1.1 Spinlock Not Supported Features
      2. 7.2.2 Spinlock Integration
      3. 7.2.3 Spinlock Functional Description
        1. 7.2.3.1 Spinlock Software Reset
        2. 7.2.3.2 Spinlock Power Management
        3. 7.2.3.3 About Spinlocks
        4. 7.2.3.4 Spinlock Functional Operation
      4. 7.2.4 Spinlock Programming Guide
        1. 7.2.4.1 Spinlock Low-level Programming Models
          1. 7.2.4.1.1 Surrounding Modules Global Initialization
          2. 7.2.4.1.2 Basic Spinlock Operations
            1. 7.2.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
            2. 7.2.4.1.2.2 Take and Release Spinlock
  10. 8 Memory Controllers
    1. 8.1 Multicore Shared Memory Controller (MSMC)
      1. 8.1.1 MSMC Overview
        1. 8.1.1.1 MSMC Not Supported Features
      2. 8.1.2 MSMC Integration
        1. 8.1.2.1 MSMC Integration in MAIN Domain
        2. 8.1.2.2 639
      3. 8.1.3 MSMC Functional Description
        1. 8.1.3.1  MSMC Block Diagram
        2. 8.1.3.2  MSMC On-Chip Memory Banking
        3. 8.1.3.3  MSMC Snoop Filter and Data Cache
          1. 8.1.3.3.1 Way Partitioning
          2. 8.1.3.3.2 Cache Size Configuration and Associativity
        4. 8.1.3.4  MSMC Access Protection Checks
        5. 8.1.3.5  MSMC Null Slave
        6. 8.1.3.6  MSMC Resource Arbitration
        7. 8.1.3.7  MSMC Error Detection and Correction
          1. 8.1.3.7.1 On-chip SRAM and Pipeline Data Protection
          2. 8.1.3.7.2 On-chip SRAM L3 Cache Tag and Snoop Filter Protection
          3. 8.1.3.7.3 On-chip SRAM Memory Mapped SRAM Snoop Filter Protection
          4. 8.1.3.7.4 Background Parity Refresh (Scrubbing)
        8. 8.1.3.8  MSMC Interrupts
          1. 8.1.3.8.1 Raw Interrupt Registers
          2. 8.1.3.8.2 Interrupt Enable Registers
          3. 8.1.3.8.3 Triggered and Enabled Interrupts
        9. 8.1.3.9  MSMC Memory Regions
        10. 8.1.3.10 MSMC Hardware Coherence
          1. 8.1.3.10.1 Snoop Filter Broadcast Mode
        11. 8.1.3.11 MSMC Quality-of-Service
        12. 8.1.3.12 MSMC Memory Regions Protection
        13. 8.1.3.13 MSMC Cache Tag View
      4. 8.1.4 MSMC Registers
    2. 8.2 DDR Subsystem (DDRSS)
      1. 8.2.1 DDRSS Overview
        1. 8.2.1.1 DDRSS Not Supported Features
      2. 8.2.2 DDRSS Environment
      3. 8.2.3 DDRSS Integration
        1. 8.2.3.1 DDRSS Integration in MAIN Domain
      4. 8.2.4 DDRSS Functional Description
        1. 8.2.4.1 DDRSS MSMC2DDR Bridge
          1. 8.2.4.1.1 VBUSM.C Threads
          2. 8.2.4.1.2 Class of Service (CoS)
          3. 8.2.4.1.3 AXI Write Data All-Strobes
          4. 8.2.4.1.4 Inline ECC for SDRAM Data
            1. 8.2.4.1.4.1 ECC Cache
            2. 8.2.4.1.4.2 ECC Statistics
          5. 8.2.4.1.5 Opcode Checking
          6. 8.2.4.1.6 Address Alias Prevention
          7. 8.2.4.1.7 Data Error Detection and Correction
          8. 8.2.4.1.8 AXI Bus Timeout
        2. 8.2.4.2 DDRSS Interrupts
        3. 8.2.4.3 DDRSS Memory Regions
        4. 8.2.4.4 DDRSS ECC Support
        5. 8.2.4.5 DDRSS Dynamic Frequency Change Interface
        6. 8.2.4.6 DDR Controller Functional Description
          1. 8.2.4.6.1  DDR PHY Interface (DFI)
          2. 8.2.4.6.2  Command Queue
            1. 8.2.4.6.2.1 Placement Logic
            2. 8.2.4.6.2.2 Command Selection Logic
          3. 8.2.4.6.3  Low Power Control
          4. 8.2.4.6.4  Transaction Processing
          5. 8.2.4.6.5  BIST Engine
          6. 8.2.4.6.6  ECC Engine
          7. 8.2.4.6.7  Address Mapping
          8. 8.2.4.6.8  Paging Policy
          9. 8.2.4.6.9  DDR Controller Initialization
          10. 8.2.4.6.10 Programming LPDDR4 Memories
            1. 8.2.4.6.10.1 Frequency Set Point (FSP)
              1. 8.2.4.6.10.1.1 FSP Mode Register Programming During Initialization
              2. 8.2.4.6.10.1.2 FSP Mode Register Programming During Normal Operation
              3. 8.2.4.6.10.1.3 FSP Mode Register Programming During Dynamic Frequency Scaling
            2. 8.2.4.6.10.2 Data Bus Inversion (DBI)
            3. 8.2.4.6.10.3 On-Die Termination
              1. 8.2.4.6.10.3.1 LPDDR4 DQ ODT
              2. 8.2.4.6.10.3.2 LPDDR4 CA ODT
            4. 8.2.4.6.10.4 Byte Lane Swapping
            5. 8.2.4.6.10.5 DQS Interval Oscillator
              1. 8.2.4.6.10.5.1 Oscillator State Machine
            6. 8.2.4.6.10.6 Per-Bank Refresh (PBR)
              1. 8.2.4.6.10.6.1 Normal Operation
              2. 8.2.4.6.10.6.2 Continuous Refresh Request Mode
        7. 8.2.4.7 DDR PHY Functional Description
          1. 8.2.4.7.1  Data Slice
          2. 8.2.4.7.2  Address Slice
            1. 8.2.4.7.2.1 Address Swapping
          3. 8.2.4.7.3  Address/Control Slice
          4. 8.2.4.7.4  Clock Slice
          5. 8.2.4.7.5  DDR PHY Initialization
          6. 8.2.4.7.6  DDR PHY Dynamic Frequency Scaling (DFS)
          7. 8.2.4.7.7  Chip Select and Frequency Based Register Settings
          8. 8.2.4.7.8  Low-Power Modes
          9. 8.2.4.7.9  Training Support
            1. 8.2.4.7.9.1 Write Leveling
            2. 8.2.4.7.9.2 Read Gate Training
            3. 8.2.4.7.9.3 Read Data Eye Training
            4. 8.2.4.7.9.4 Write DQ Training
            5. 8.2.4.7.9.5 CA Training
            6. 8.2.4.7.9.6 CS Training
          10. 8.2.4.7.10 Data Bus Inversion (DBI)
          11. 8.2.4.7.11 I/O Pad Calibration
          12. 8.2.4.7.12 DQS Error
        8. 8.2.4.8 PI Functional Description
          1. 8.2.4.8.1 PI Initialization
      5. 8.2.5 DDRSS Registers
        1. 8.2.5.1 DDR Subsystem Registers
        2. 8.2.5.2 DDR Controller Registers
        3. 8.2.5.3 PI Registers
        4. 8.2.5.4 DDR PHY Registers
        5. 8.2.5.5 DDRSS0_ECC_AGGR_CTL Registers
        6. 8.2.5.6 DDRSS0_ECC_AGGR_VBUS Registers
        7. 8.2.5.7 DDRSS0_ECC_AGGR_CFG Registers
    3. 8.3 Peripheral Virtualization Unit (PVU)
      1. 8.3.1 PVU Overview
        1. 8.3.1.1 PVU Features
        2. 8.3.1.2 PVU Parameters
        3. 8.3.1.3 PVU Not Supported Features
      2. 8.3.2 PVU Integration
      3. 8.3.3 PVU Functional Description
        1. 8.3.3.1  Functional Operation Overview
        2. 8.3.3.2  PVU Channels
        3. 8.3.3.3  TLB
        4. 8.3.3.4  TLB Entry
        5. 8.3.3.5  TLB Selection
        6. 8.3.3.6  DMA Classes
        7. 8.3.3.7  General virtIDs
        8. 8.3.3.8  TLB Lookup
        9. 8.3.3.9  TLB Miss
        10. 8.3.3.10 Multiple Matching Entries
        11. 8.3.3.11 TLB Disable
        12. 8.3.3.12 TLB Chaining
        13. 8.3.3.13 TLB Permissions
        14. 8.3.3.14 Translation
        15. 8.3.3.15 Memory Attributes
        16. 8.3.3.16 Faulted Transactions
        17. 8.3.3.17 Non-Virtual Transactions
        18. 8.3.3.18 Allowed virtIDs
        19. 8.3.3.19 Software Control
        20. 8.3.3.20 Fault Logging
        21. 8.3.3.21 Alignment Restrictions
      4. 8.3.4 PVU Registers
        1. 8.3.4.1 NAVSS_PVU_CFG Registers
        2. 8.3.4.2 NAVSS0_PVU_CFG_TLBIF Registers
    4. 8.4 Region-based Address Translation (RAT) Module
      1. 8.4.1 RAT Functional Description
        1. 8.4.1.1 RAT Availability
        2. 8.4.1.2 RAT Operation
        3. 8.4.1.3 RAT Error Logging
      2. 8.4.2 RAT Registers
  11. 9 Interrupts
    1. 9.1 Interrupt Architecture
    2. 9.2 Interrupt Controllers
      1. 9.2.1 Generic Interrupt Controller (GIC)
        1. 9.2.1.1 GIC Overview
          1. 9.2.1.1.1 GIC Features
          2. 9.2.1.1.2 GIC Not Supported Features
        2. 9.2.1.2 GIC Integration
        3. 9.2.1.3 GIC Functional Description
          1. 9.2.1.3.1 GIC Block Diagram
          2. 9.2.1.3.2 Arm GIC-500
          3. 9.2.1.3.3 GIC Interrupt Types
          4. 9.2.1.3.4 GIC Interfaces
          5. 9.2.1.3.5 GIC Interrupt Outputs
          6. 9.2.1.3.6 GIC ECC Support
          7. 9.2.1.3.7 GIC AXI2VBUSM and VBUSM2AXI Bridges
        4. 9.2.1.4 GIC Registers
          1. 9.2.1.4.1 Arm GIC-500 Registers
          2. 9.2.1.4.2 GIC_ECC_AGGR Registers
      2. 9.2.2 Other Interrupt Controllers
    3. 9.3 Interrupt Routers
      1. 9.3.1 INTRTR Overview
      2. 9.3.2 INTRTR Integration
        1. 9.3.2.1 WKUP_GPIOMUX_INTRTR0 Integration
        2. 9.3.2.2 GPIOMUX_INTRTR0 Integration
        3. 9.3.2.3 MAIN2MCU_LVL_INTRTR0 Integration
        4. 9.3.2.4 MAIN2MCU_PLS_INTRTR0 Integration
      3. 9.3.3 INTRTR Registers
        1. 9.3.3.1 WKUP_GPIOMUX_INTRTR0 Registers
        2. 9.3.3.2 GPIOMUX_INTRTR0 Registers
        3. 9.3.3.3 MAIN2MCU_LVL_INTRTR0 Registers
        4. 9.3.3.4 MAIN2MCU_PLS_INTRTR0 Registers
    4. 9.4 Interrupt Sources
      1. 9.4.1 WKUP Domain Interrupt Maps
        1. 9.4.1.1 WKUP_DMSC0 Interrupt Map
        2. 9.4.1.2 WKUP_GPIOMUX_INTRTR0 Interrupt Map
        3. 9.4.1.3 WKUP_GPIO0_VIRT Interrupt Map
        4. 9.4.1.4 WKUP_ESM0 Interrupt Map
      2. 9.4.2 MCU Domain Interrupt Maps
        1. 9.4.2.1 MCU_R5FSS0_CORE0 Interrupt Map
        2. 9.4.2.2 MCU_R5FSS0_CORE1 Interrupt Map
        3. 9.4.2.3 MCU_ESM0 Interrupt Map
      3. 9.4.3 MAIN Domain Interrupt Maps
        1. 9.4.3.1 COMPUTE_CLUSTER0 Interrupt Map
          1. 9.4.3.1.1 GIC500 PPI Interrupt Map
          2. 9.4.3.1.2 GIC500 SPI Interrupt Map
          3. 9.4.3.1.3 SoC Event Output Interrupt Map
        2. 9.4.3.2 R5FSS0_CORE0 Interrupt Map
        3. 9.4.3.3 R5FSS0_CORE1 Interrupt Map
        4. 9.4.3.4 MAIN2MCU_LVL_INTRTR0 Interrupt Map
        5. 9.4.3.5 MAIN2MCU_PLS_INTRTR0 Interrupt Map
        6. 9.4.3.6 GPIOMUX_INTRTR0 Interrupt Map
        7. 9.4.3.7 GPIO0_VIRT Interrupt Map
        8. 9.4.3.8 ESM0 Interrupt Map
  12. 10Data Movement Architecture (DMA)
    1. 10.1 DMA Architecture
      1. 10.1.1 Overview
        1. 10.1.1.1  Navigator Subsystem
        2. 10.1.1.2  Ring Accelerator (RA)
        3. 10.1.1.3  Proxy
        4. 10.1.1.4  Secure Proxy
        5. 10.1.1.5  Interrupt Aggregator (INTA)
        6. 10.1.1.6  Interrupt Router (IR)
        7. 10.1.1.7  Unified DMA – Third Party Channel Controller (UDMA-C)
        8. 10.1.1.8  Unified Transfer Controller (UTC)
        9. 10.1.1.9  Data Routing Unit (DRU)
        10. 10.1.1.10 Unified DMA – Peripheral Root Complex (UDMA-P)
          1. 10.1.1.10.1 Channel Classes
        11. 10.1.1.11 Peripheral DMA (PDMA)
        12. 10.1.1.12 Embedded DMA
        13. 10.1.1.13 Definition of Terms
      2. 10.1.2 UDMA Hardware/Software Interface
        1. 10.1.2.1 Data Buffers
        2. 10.1.2.2 Descriptors
          1. 10.1.2.2.1 Host Packet Descriptor
          2. 10.1.2.2.2 Host Buffer Descriptor
          3. 10.1.2.2.3 Monolithic Packet Descriptor
          4. 10.1.2.2.4 Transfer Request Descriptor
        3. 10.1.2.3 Transfer Request Record
          1. 10.1.2.3.1 Overview
          2. 10.1.2.3.2 Addressing Algorithm
            1. 10.1.2.3.2.1 Linear Addressing (Forward)
          3. 10.1.2.3.3 Transfer Request Formats
          4. 10.1.2.3.4 Flags Field Definition
            1. 10.1.2.3.4.1 Type: TR Type Field
            2. 10.1.2.3.4.2 STATIC: Static Field Definition
            3. 10.1.2.3.4.3 EVENT_SIZE: Event Generation Definition
            4. 10.1.2.3.4.4 TRIGGER INFO: TR Triggers
            5. 10.1.2.3.4.5 TRIGGERX_TYPE: Trigger Type
            6. 10.1.2.3.4.6 TRIGGERX: Trigger Selection
            7. 10.1.2.3.4.7 CMD ID: Command ID Field Definition
            8. 10.1.2.3.4.8 Configuration Specific Flags Definition
          5. 10.1.2.3.5 TR Address and Size Attributes
            1. 10.1.2.3.5.1  ICNT0
            2. 10.1.2.3.5.2  ICNT1
            3. 10.1.2.3.5.3  ADDR
            4. 10.1.2.3.5.4  DIM1
            5. 10.1.2.3.5.5  ICNT2
            6. 10.1.2.3.5.6  ICNT3
            7. 10.1.2.3.5.7  DIM2
            8. 10.1.2.3.5.8  DIM3
            9. 10.1.2.3.5.9  DDIM1
            10. 10.1.2.3.5.10 DADDR
            11. 10.1.2.3.5.11 DDIM2
            12. 10.1.2.3.5.12 DDIM3
            13. 10.1.2.3.5.13 DICNT0
            14. 10.1.2.3.5.14 DICNT1
            15. 10.1.2.3.5.15 DICNT2
            16. 10.1.2.3.5.16 DICNT3
          6. 10.1.2.3.6 FMTFLAGS
            1. 10.1.2.3.6.1 AMODE: Addressing Mode Definition
              1. 10.1.2.3.6.1.1 Linear Addressing
              2. 10.1.2.3.6.1.2 Circular Addressing
            2. 10.1.2.3.6.2 DIR: Addressing Mode Direction Definition
            3. 10.1.2.3.6.3 ELTYPE: Element Type Definition
            4. 10.1.2.3.6.4 DFMT: Data Formatting Algorithm Definition
            5. 10.1.2.3.6.5 SECTR: Secondary Transfer Request Definition
              1. 10.1.2.3.6.5.1 Secondary TR Formats
              2. 10.1.2.3.6.5.2 Secondary TR FLAGS
                1. 10.1.2.3.6.5.2.1 SEC_TR_TYPE: Secondary TR Type Field
                2. 10.1.2.3.6.5.2.2 Multiple Buffer Interleave
            6. 10.1.2.3.6.6 AMODE SPECIFIC: Addressing Mode Field
              1. 10.1.2.3.6.6.1 Circular Address Mode Specific Flags
                1. 10.1.2.3.6.6.1.1 CBK0 and CBK1: Circular Block Size Selection
                2. 10.1.2.3.6.6.1.2 Amx: Addressing Mode Selection
            7. 10.1.2.3.6.7 Cache Flags
        4. 10.1.2.4 Transfer Response Record
          1. 10.1.2.4.1 STATUS Field Definition
            1. 10.1.2.4.1.1 STATUS_TYPE Definition
              1. 10.1.2.4.1.1.1 Transfer Error
              2. 10.1.2.4.1.1.2 Aborted Error
              3. 10.1.2.4.1.1.3 Submission Error
              4. 10.1.2.4.1.1.4 Unsupported Feature
              5. 10.1.2.4.1.1.5 Transfer Exception
              6. 10.1.2.4.1.1.6 Teardown Flush
        5. 10.1.2.5 Queues
          1. 10.1.2.5.1 Queue Types
            1. 10.1.2.5.1.1 Transmit Queues (Pass By Reference)
            2. 10.1.2.5.1.2 Transmit Queues (Pass By Value)
            3. 10.1.2.5.1.3 Transmit Completion Queues (Pass By Reference)
            4. 10.1.2.5.1.4 Transmit Completion Queues (Pass By Value)
            5. 10.1.2.5.1.5 Receive Queues
            6. 10.1.2.5.1.6 Free Descriptor Queues
            7. 10.1.2.5.1.7 Free Descriptor/Buffer Queues
          2. 10.1.2.5.2 Ring Accelerator Queues Implementation
      3. 10.1.3 Operational Description
        1. 10.1.3.1  Resource Allocation
        2. 10.1.3.2  Ring Accelerator Operation
          1. 10.1.3.2.1 Queue Initialization
          2. 10.1.3.2.2 Queuing packets (Exposed Ring Mode)
          3. 10.1.3.2.3 De-queuing packets (Exposed Ring Mode)
          4. 10.1.3.2.4 Queuing packets (Queue Mode)
          5. 10.1.3.2.5 De-queuing packets (Queue Mode)
        3. 10.1.3.3  UDMA Internal Transmit Channel Setup (All Packet Types)
        4. 10.1.3.4  UDMA Internal Transmit Channel Teardown (All Packet Types)
        5. 10.1.3.5  UDMA External Transmit Channel Setup
        6. 10.1.3.6  UDMA Transmit External Channel Teardown
        7. 10.1.3.7  UDMA-P Transmit Channel Pause
        8. 10.1.3.8  UDMA-P Transmit Operation (Host Packet Type)
        9. 10.1.3.9  UDMA-P Transmit Operation (Monolithic Packet)
        10. 10.1.3.10 UDMA Transmit Operation (TR Packet)
        11. 10.1.3.11 UDMA Transmit Operation (Direct TR)
        12. 10.1.3.12 UDMA Transmit Error/Exception Handling
          1. 10.1.3.12.1 Null Icnt0 Error
          2. 10.1.3.12.2 Unsupported TR Type
          3. 10.1.3.12.3 Bus Errors
        13. 10.1.3.13 UDMA Receive Channel Setup (All Packet Types)
        14. 10.1.3.14 UDMA Receive Channel Teardown
        15. 10.1.3.15 UDMA-P Receive Channel Pause
        16. 10.1.3.16 UDMA-P Receive Free Descriptor/Buffer Queue Setup (Host Packets)
        17. 10.1.3.17 UDMA-P Receive FlowID Firewall Operation
        18. 10.1.3.18 UDMA-P Receive Operation (Host Packet)
        19. 10.1.3.19 UDMA-P Receive Operation (Monolithic Packet)
        20. 10.1.3.20 UDMA Receive Operation (TR Packet)
        21. 10.1.3.21 UDMA Receive Operation (Direct TR)
        22. 10.1.3.22 UDMA Receive Error/Exception Handling
          1. 10.1.3.22.1 Error Conditions
            1. 10.1.3.22.1.1 Bus Errors
            2. 10.1.3.22.1.2 Null Icnt0 Error
            3. 10.1.3.22.1.3 Unsupported TR Type
          2. 10.1.3.22.2 Exception Conditions Exception Conditions
            1. 10.1.3.22.2.1 Descriptor Starvation
            2. 10.1.3.22.2.2 Protocol Errors
            3. 10.1.3.22.2.3 Dropped Packets
            4. 10.1.3.22.2.4 Reception of EOL Delimiter
            5. 10.1.3.22.2.5 EOP Asserted Prematurely (Short Packet)
            6. 10.1.3.22.2.6 EOP Asserted Late (Long Packets)
        23. 10.1.3.23 UTC Operation
        24. 10.1.3.24 UTC Receive Error/Exception Handling
          1. 10.1.3.24.1 Error Handling
            1. 10.1.3.24.1.1 Null Icnt0 Error
            2. 10.1.3.24.1.2 Unsupported TR Type
          2. 10.1.3.24.2 Exception Conditions
            1. 10.1.3.24.2.1 Reception of EOL Delimiter
            2. 10.1.3.24.2.2 EOP Asserted Prematurely (Short Packet)
            3. 10.1.3.24.2.3 EOP Asserted Late (Long Packets)
    2. 10.2 Navigator Subsystem (NAVSS)
      1. 10.2.1  Main Navigator Subsystem (NAVSS)
        1. 10.2.1.1 NAVSS Overview
        2. 10.2.1.2 NAVSS Integration
          1. 10.2.1.2.1 NAVSS Interrupt Router Configuration
          2. 10.2.1.2.2 Global Event Map
          3. 10.2.1.2.3 PSI-L System Thread Map (All NAVSS)
          4. 10.2.1.2.4 NAVSS VBUSM Route ID Table
        3. 10.2.1.3 NAVSS Functional Description
        4. 10.2.1.4 NAVSS Interrupt Configuration
          1. 10.2.1.4.1 NAVSS Event and Interrupt Flow
            1. 10.2.1.4.1.1 NAVSS Interrupts Description
            2. 10.2.1.4.1.2 Application Example
        5. 10.2.1.5 NAVSS Top-level Registers
          1. 10.2.1.5.1 NAVSS0_CFG Registers
          2. 10.2.1.5.2 INTR0_INTR_ROUTER_CFG Registers
          3. 10.2.1.5.3 VIRTID_CFG_MMRS Registers
      2. 10.2.2  MCU Navigator Subsystem (MCU NAVSS)
        1. 10.2.2.1 MCU NAVSS Overview
        2. 10.2.2.2 MCU NAVSS Integration
          1. 10.2.2.2.1  MCU NAVSS Interrupt Router Configuration
          2. 10.2.2.2.2  MCU NAVSS UDMASS Interrupt Aggregator Configuration
          3. 10.2.2.2.3  MCU NAVSS UDMA Configuration
          4. 10.2.2.2.4  MCU NAVSS Ring Accelerator Configuration
          5. 10.2.2.2.5  MCU NAVSS Proxy Configuration
          6. 10.2.2.2.6  MCU NAVSS Secure Proxy Configuration
          7. 10.2.2.2.7  Global Event Map
          8. 10.2.2.2.8  PSI-L System Thread Map (All NAVSS)
          9. 10.2.2.2.9  MCU NAVSS VBUSM Route ID Table
          10. 10.2.2.2.10 1006
        3. 10.2.2.3 MCU NAVSS Functional Description
        4. 10.2.2.4 MCU NAVSS Top-Level Registers
          1. 10.2.2.4.1 MCU_NAVSS0_CFG Registers
          2. 10.2.2.4.2 MCU_NAVSS0_UDMASS_ECCAGGR0 Registers
      3. 10.2.3  Unified DMA Controller (UDMA)
        1. 10.2.3.1 UDMA Overview
          1. 10.2.3.1.1 UDMA Features
          2. 10.2.3.1.2 UDMA Parameters
        2. 10.2.3.2 UDMA Integration
        3. 10.2.3.3 UDMA Functional Description
          1. 10.2.3.3.1 Block Diagram
          2. 10.2.3.3.2 General Functionality
            1. 10.2.3.3.2.1  Operational States
            2. 10.2.3.3.2.2  Tx Channel Allocation
            3. 10.2.3.3.2.3  Rx Channel Allocation
            4. 10.2.3.3.2.4  Tx Teardown
            5. 10.2.3.3.2.5  Rx Teardown
            6. 10.2.3.3.2.6  Tx Clock Stop
            7. 10.2.3.3.2.7  Rx Clock Stop
            8. 10.2.3.3.2.8  Rx Thread Enables
            9. 10.2.3.3.2.9  Events
              1. 10.2.3.3.2.9.1 Local Event Inputs
              2. 10.2.3.3.2.9.2 Inbound Tx PSI-L Events
              3. 10.2.3.3.2.9.3 Outbound Rx PSI-L Events
            10. 10.2.3.3.2.10 Emulation Control
          3. 10.2.3.3.3 Packet Oriented Transmit Operation
            1. 10.2.3.3.3.1 Packet Mode VBUSM Master Interface Command ID Selection
          4. 10.2.3.3.4 Packet Oriented Receive Operation
            1. 10.2.3.3.4.1 Rx Packet Drop
            2. 10.2.3.3.4.2 Rx Starvation and the Starvation Timer
          5. 10.2.3.3.5 Third Party Mode Operation
            1. 10.2.3.3.5.1 Events and Flow Control
              1. 10.2.3.3.5.1.1 Channel Triggering
              2. 10.2.3.3.5.1.2 Internal TR Completion Events
            2. 10.2.3.3.5.2 Transmit Operation
              1. 10.2.3.3.5.2.1 Transfer Request
              2. 10.2.3.3.5.2.2 Transfer Response
              3. 10.2.3.3.5.2.3 Data Transfer
              4. 10.2.3.3.5.2.4 Memory Interface Transactions
              5. 10.2.3.3.5.2.5 Error Handling
            3. 10.2.3.3.5.3 Receive Operation
              1. 10.2.3.3.5.3.1 Transfer Request
              2. 10.2.3.3.5.3.2 Transfer Response
              3. 10.2.3.3.5.3.3 Error Handling
            4. 10.2.3.3.5.4 Data Transfer
              1. 10.2.3.3.5.4.1 Memory Interface Transactions
              2. 10.2.3.3.5.4.2 Rx Packet Drop
        4. 10.2.3.4 UDMA Registers
          1. 10.2.3.4.1 UDMASS_UDMAP0_CFG Registers
          2. 10.2.3.4.2 UDMASS_UDMAP0_CFG_TCHAN Registers
          3. 10.2.3.4.3 UDMASS_UDMAP0_CFG_RCHAN Registers
          4. 10.2.3.4.4 UDMASS_UDMAP0_CFG_RFLOW Registers
          5. 10.2.3.4.5 UDMASS_UDMAP0_CFG_RCHANRT Registers
          6. 10.2.3.4.6 UDMASS_UDMAP0_CFG_TCHANRT Registers
      4. 10.2.4  Ring Accelerator (RINGACC)
        1. 10.2.4.1 RINGACC Overview
          1. 10.2.4.1.1 RINGACC Features
          2. 10.2.4.1.2 RINGACC Not Supported Features
          3. 10.2.4.1.3 RINGACC Parameters
        2. 10.2.4.2 RINGACC Integration
        3. 10.2.4.3 RINGACC Functional Description
          1. 10.2.4.3.1 Block Diagram
            1. 10.2.4.3.1.1  Configuration Registers
            2. 10.2.4.3.1.2  Source Command FIFO
            3. 10.2.4.3.1.3  Source Write Data FIFO
            4. 10.2.4.3.1.4  Source Read Data FIFO
            5. 10.2.4.3.1.5  Source Write Status FIFO
            6. 10.2.4.3.1.6  Main State Machine
            7. 10.2.4.3.1.7  Destination Command FIFO
            8. 10.2.4.3.1.8  Destination Write Data FIFO
            9. 10.2.4.3.1.9  Destination Read Data FIFO
            10. 10.2.4.3.1.10 Destination Write Status FIFO
          2. 10.2.4.3.2 RINGACC Functional Operation
            1. 10.2.4.3.2.1 Queue Modes
              1. 10.2.4.3.2.1.1 Ring Mode
              2. 10.2.4.3.2.1.2 Messaging Mode
              3. 10.2.4.3.2.1.3 Credentials Mode
              4. 10.2.4.3.2.1.4 Queue Manager Mode
              5. 10.2.4.3.2.1.5 Peek Support
              6. 10.2.4.3.2.1.6 Index Register Operation
            2. 10.2.4.3.2.2 VBUSM Slave Ring Operations
            3. 10.2.4.3.2.3 VBUSM Master Interface Command ID Selection
            4. 10.2.4.3.2.4 Ring Push Operation (VBUSM Write to Source Interface)
            5. 10.2.4.3.2.5 Ring Pop Operation (VBUSM Read from Source Interface)
            6. 10.2.4.3.2.6 Host Doorbell Access
            7. 10.2.4.3.2.7 Queue Push Operation (VBUSM Write to Source Interface)
            8. 10.2.4.3.2.8 Queue Pop Operation (VBUSM Read from Source Interface)
            9. 10.2.4.3.2.9 Mismatched Element Size Handling
          3. 10.2.4.3.3 Events
          4. 10.2.4.3.4 Bus Error Handling
          5. 10.2.4.3.5 Monitors
            1. 10.2.4.3.5.1 Threshold Monitor
            2. 10.2.4.3.5.2 Watermark Monitor
            3. 10.2.4.3.5.3 Starvation Monitor
            4. 10.2.4.3.5.4 Statistics Monitor
            5. 10.2.4.3.5.5 Overflow
            6. 10.2.4.3.5.6 Ring Update Port
            7. 10.2.4.3.5.7 Tracing
        4. 10.2.4.4 RINGACC Registers
          1. 10.2.4.4.1 NAVSS0_UDMASS_RINGACC0_CFG Registers
          2. 10.2.4.4.2 NAVSS0_UDMASS_RINGACC0_GCFG Registers
          3. 10.2.4.4.3 NAVSS0_UDMASS_RINGACC0_CFG_MON Registers
          4. 10.2.4.4.4 NAVSS0_UDMASS_RINGACC0_CFG_RT Registers
          5. 10.2.4.4.5 NAVSS0_UDMASS_RINGACC0_SRC_FIFOS Registers
      5. 10.2.5  Proxy
        1. 10.2.5.1 Proxy Overview
          1. 10.2.5.1.1 Proxy Features
          2. 10.2.5.1.2 Proxy Parameters
          3. 10.2.5.1.3 Proxy Not Supported Features
        2. 10.2.5.2 Proxy Integration
        3. 10.2.5.3 Proxy Functional Description
          1. 10.2.5.3.1  Targets
            1. 10.2.5.3.1.1 Ring Accelerator
          2. 10.2.5.3.2  Proxy Sizes
          3. 10.2.5.3.3  Proxy Interleaving
          4. 10.2.5.3.4  Proxy Host States
          5. 10.2.5.3.5  Proxy Host Channel Selection
          6. 10.2.5.3.6  Proxy Host Access
            1. 10.2.5.3.6.1 Proxy Host Writes
            2. 10.2.5.3.6.2 Proxy Host Reads
          7. 10.2.5.3.7  Permission Inheritance
          8. 10.2.5.3.8  Buffer Size
          9. 10.2.5.3.9  Error Events
          10. 10.2.5.3.10 Debug Reads
        4. 10.2.5.4 Proxy Registers
          1. 10.2.5.4.1 NAVSS0_PROXY0_CFG_BUF_CFG Registers
          2. 10.2.5.4.2 NAVSS0_PROXY0_BUF_CFG Registers
          3. 10.2.5.4.3 NAVSS0_PROXY_BUF Registers
          4. 10.2.5.4.4 NAVSS0_PROXY_TARGET0_DATA Registers
      6. 10.2.6  Secure Proxy
        1. 10.2.6.1 Secure Proxy Overview
          1. 10.2.6.1.1 Secure Proxy Features
          2. 10.2.6.1.2 Secure Proxy Parameters
          3. 10.2.6.1.3 Secure Proxy Not Supported Features
        2. 10.2.6.2 Secure Proxy Integration
        3. 10.2.6.3 Secure Proxy Functional Description
          1. 10.2.6.3.1  Targets
            1. 10.2.6.3.1.1 Ring Accelerator
          2. 10.2.6.3.2  Buffers
            1. 10.2.6.3.2.1 Proxy Credits
            2. 10.2.6.3.2.2 Proxy Private Word
            3. 10.2.6.3.2.3 Completion Byte
          3. 10.2.6.3.3  Proxy Thread Sizes
          4. 10.2.6.3.4  Proxy Thread Interleaving
          5. 10.2.6.3.5  Proxy States
          6. 10.2.6.3.6  Proxy Host Access
            1. 10.2.6.3.6.1 Proxy Host Writes
            2. 10.2.6.3.6.2 Proxy Host Reads
            3. 10.2.6.3.6.3 Buffer Accesses
            4. 10.2.6.3.6.4 Target Access
            5. 10.2.6.3.6.5 Error State
          7. 10.2.6.3.7  Permission Inheritance
          8. 10.2.6.3.8  Resource Association
          9. 10.2.6.3.9  Direction
          10. 10.2.6.3.10 Threshold Events
          11. 10.2.6.3.11 Error Events
          12. 10.2.6.3.12 Bus Errors and Credits
          13. 10.2.6.3.13 Debug
        4. 10.2.6.4 Secure Proxy Registers
          1. 10.2.6.4.1 NAVSS0_SEC_PROXY0_CFG_MMRS Registers
          2. 10.2.6.4.2 NAVSS0_SEC_PROXY0_CFG_RT Registers
          3. 10.2.6.4.3 NAVSS0_SEC_PROXY0_CFG_SCFG Registers
          4. 10.2.6.4.4 NAVSS0_SEC_PROXY0_SRC_TARGET_DATA Registers
      7. 10.2.7  Interrupt Aggregator (INTR_AGGR)
        1. 10.2.7.1 INTR_AGGR Overview
          1. 10.2.7.1.1 INTR_AGGR Features
          2. 10.2.7.1.2 INTR_AGGR Parameters
        2. 10.2.7.2 INTR_AGGR Integration
        3. 10.2.7.3 INTR_AGGR Functional Description
          1. 10.2.7.3.1 Submodule Descriptions
            1. 10.2.7.3.1.1 Status/Mask Registers
            2. 10.2.7.3.1.2 Interrupt Mapping Block
            3. 10.2.7.3.1.3 Global Event Input (GEVI) Counters
            4. 10.2.7.3.1.4 Local Event Input (LEVI) to Global Event Conversion
            5. 10.2.7.3.1.5 Global Event Multicast
          2. 10.2.7.3.2 General Functionality
            1. 10.2.7.3.2.1 Event to Interrupt Bit Steering
            2. 10.2.7.3.2.2 Interrupt Status
            3. 10.2.7.3.2.3 Interrupt Masked Status
            4. 10.2.7.3.2.4 Enabling/Disabling Individual Interrupt Source Bits
            5. 10.2.7.3.2.5 Interrupt Output Generation
            6. 10.2.7.3.2.6 Global Event Counting
            7. 10.2.7.3.2.7 Local Event to Global Event Conversion
            8. 10.2.7.3.2.8 Global Event Multicast
        4. 10.2.7.4 INTR_AGGR Registers
          1. 10.2.7.4.1  MODSS_INTA_CFG Registers
          2. 10.2.7.4.2  MODSS_INTA_CFG_IMAP Registers
          3. 10.2.7.4.3  MODSS_INTA_CFG_INTR Registers
          4. 10.2.7.4.4  UDMASS_INTA0_CFG Registers
          5. 10.2.7.4.5  UDMASS_INTA0_CFG_INTR Registers
          6. 10.2.7.4.6  UDMASS_INTA0_CFG_IMAP Registers
          7. 10.2.7.4.7  UDMASS_INTA0_CFG_L2G Registers
          8. 10.2.7.4.8  UDMASS_INTA0_CFG_MCAST Registers
          9. 10.2.7.4.9  UDMASS_INTA0_CFG_GCNTCFG Registers
          10. 10.2.7.4.10 UDMASS_INTA0_CFG_GCNTRTI Registers
      8. 10.2.8  Packet Streaming Interface Link (PSI-L)
        1. 10.2.8.1 PSI-L Overview
        2. 10.2.8.2 PSI-L Functional Description
          1. 10.2.8.2.1 PSI-L Introduction
          2. 10.2.8.2.2 PSI-L Operation
            1. 10.2.8.2.2.1 Event Transport
            2. 10.2.8.2.2.2 Threads
            3. 10.2.8.2.2.3 Arbitration Protocol
            4. 10.2.8.2.2.4 Thread Configuration
              1. 10.2.8.2.2.4.1 Thread Pairing
                1. 10.2.8.2.2.4.1.1 Configuration Transaction Pairing
              2. 10.2.8.2.2.4.2 Configuration Registers Region
        3. 10.2.8.3 PSI-L Configuration Registers
        4. 10.2.8.4 PSI-L CFG_PROXY Registers
      9. 10.2.9  PSIL Subsystem (PSILSS)
        1. 10.2.9.1 PSILSS Overview
          1. 10.2.9.1.1 PSILSS Features
        2. 10.2.9.2 PSILSS Functional Description
          1. 10.2.9.2.1 PSILSS Basic Operation
          2. 10.2.9.2.2 PSILSS Event Routing
          3. 10.2.9.2.3 PSILSS Link Down Detection
          4. 10.2.9.2.4 PSILSS Configuration
        3. 10.2.9.3 PSILSS Registers
          1. 10.2.9.3.1 PDMA_USART_PSILSS0 Registers
          2. 10.2.9.3.2 PDMA_SPI_PSILSS0 Registers
      10. 10.2.10 NAVSS North Bridge (NB)
        1. 10.2.10.1 NB Overview
          1. 10.2.10.1.1 Features Supported
          2. 10.2.10.1.2 NB Parameters
            1. 10.2.10.1.2.1 Compliance to Standards
            2. 10.2.10.1.2.2 Features Not Supported
        2. 10.2.10.2 NB Functional Description
          1. 10.2.10.2.1  VBUSM Slave Interfaces
          2. 10.2.10.2.2  VBUSM Master Interface
          3. 10.2.10.2.3  VBUSM.C Interfaces
            1. 10.2.10.2.3.1 Multi-Threading
            2. 10.2.10.2.3.2 Write Command Crediting
            3. 10.2.10.2.3.3 Early Credit Response
            4. 10.2.10.2.3.4 Priority Escalation
          4. 10.2.10.2.4  Source M2M Bridges
          5. 10.2.10.2.5  Destination M2M Bridge
          6. 10.2.10.2.6  M2C Bridge
          7. 10.2.10.2.7  Memory Attribute Tables
          8. 10.2.10.2.8  Outstanding Read Data Limiter
          9. 10.2.10.2.9  Ordering
          10. 10.2.10.2.10 Quality of Service
          11. 10.2.10.2.11 IDLE Behavior
          12. 10.2.10.2.12 Clock Power Management
        3. 10.2.10.3 NB Registers
          1. 10.2.10.3.1 NAVSS0_NBSS_CFG_REGS0_MMRS Registers
          2. 10.2.10.3.2 NAVSS0_NBSS_NB_CFG_MMRS Registers
    3. 10.3 Peripheral DMA (PDMA)
      1. 10.3.1 PDMA Controller
        1. 10.3.1.1 PDMA Overview
          1. 10.3.1.1.1 PDMA Features
            1. 10.3.1.1.1.1  MCU_PDMA0 (MCU_PDMA_MISC_G0) Features
            2. 10.3.1.1.1.2  MCU_PDMA1 (MCU_PDMA_MISC_G1) Features
            3. 10.3.1.1.1.3  MCU_PDMA2 (MCU_PDMA_MISC_G2) Features
            4. 10.3.1.1.1.4  MCU_PDMA3 (MCU_PDMA_ADC) Features
            5. 10.3.1.1.1.5  PDMA2 (PDMA_DEBUG_CCMCU) Features
            6. 10.3.1.1.1.6  PDMA5 (PDMA_MCAN) Features
            7. 10.3.1.1.1.7  PDMA6 (PDMA_MCASP_G0) Features
            8. 10.3.1.1.1.8  PDMA9 (PDMA_SPI_G0) Features
            9. 10.3.1.1.1.9  PDMA10 (PDMA_SPI_G1) Features
            10. 10.3.1.1.1.10 PDMA13 (PDMA_USART_G0) Features
            11. 10.3.1.1.1.11 PDMA14 (PDMA_USART_G1) Features
            12. 10.3.1.1.1.12 PDMA15 (PDMA_USART_G2) Features
        2. 10.3.1.2 PDMA Integration
          1. 10.3.1.2.1 PDMA Integration in MCU Domain
          2. 10.3.1.2.2 PDMA Integration in MAIN Domain
        3. 10.3.1.3 PDMA Functional Description
          1. 10.3.1.3.1 PDMA Functional Blocks
            1. 10.3.1.3.1.1 Scheduler
            2. 10.3.1.3.1.2 Tx Per-Channel Buffers (TCP FIFO)
            3. 10.3.1.3.1.3 Tx DMA Unit (Tx Engine)
            4. 10.3.1.3.1.4 Rx Per-Channel Buffers (RCP FIFO)
            5. 10.3.1.3.1.5 Rx DMA Unit (Rx Engine)
          2. 10.3.1.3.2 PDMA General Functionality
            1. 10.3.1.3.2.1 Operational States
            2. 10.3.1.3.2.2 Clock Stop
            3. 10.3.1.3.2.3 Emulation Control
          3. 10.3.1.3.3 PDMA Events and Flow Control
            1. 10.3.1.3.3.1 Channel Types
              1. 10.3.1.3.3.1.1 X-Y FIFO Mode
              2. 10.3.1.3.3.1.2 MCAN Mode
              3. 10.3.1.3.3.1.3 AASRC Mode
              4. 10.3.1.3.3.1.4 1288
            2. 10.3.1.3.3.2 Channel Triggering
            3. 10.3.1.3.3.3 Completion Events
          4. 10.3.1.3.4 PDMA Transmit Operation
            1. 10.3.1.3.4.1 Destination (Tx) Channel Allocation
            2. 10.3.1.3.4.2 Destination (Tx) Channel Out-of-Band Signals
            3. 10.3.1.3.4.3 Destination Channel Initialization
              1. 10.3.1.3.4.3.1 PSI-L Destination Thread Pairing
              2. 10.3.1.3.4.3.2 Static Transfer Request Setup
              3. 10.3.1.3.4.3.3 1297
              4. 10.3.1.3.4.3.4 PSI-L Destination Thread Enables
            4. 10.3.1.3.4.4 Data Transfer
              1. 10.3.1.3.4.4.1 X-Y FIFO Mode Channel
                1. 10.3.1.3.4.4.1.1 X-Y FIFO Burst Mode
              2. 10.3.1.3.4.4.2 MCAN Mode Channel
                1. 10.3.1.3.4.4.2.1 MCAN Burst Mode
              3. 10.3.1.3.4.4.3 AASRC Mode Channel
            5. 10.3.1.3.4.5 Tx Pause
            6. 10.3.1.3.4.6 Tx Teardown
            7. 10.3.1.3.4.7 Tx Channel Reset
            8. 10.3.1.3.4.8 Tx Debug/State Registers
          5. 10.3.1.3.5 PDMA Receive Operation
            1. 10.3.1.3.5.1 Source (Rx) Channel Allocation
            2. 10.3.1.3.5.2 Source Channel Initialization
              1. 10.3.1.3.5.2.1 PSI-L Source Thread Pairing
              2. 10.3.1.3.5.2.2 Static Transfer Request Setup
              3. 10.3.1.3.5.2.3 PSI-L Source Thread Enables
            3. 10.3.1.3.5.3 Data Transfer
              1. 10.3.1.3.5.3.1 X-Y FIFO Mode Channel
              2. 10.3.1.3.5.3.2 MCAN Mode Channel
                1. 10.3.1.3.5.3.2.1 MCAN Burst Mode
              3. 10.3.1.3.5.3.3 AASRC Mode Channel
            4. 10.3.1.3.5.4 Rx Pause
            5. 10.3.1.3.5.5 Rx Teardown
            6. 10.3.1.3.5.6 Rx Channel Reset
            7. 10.3.1.3.5.7 Rx Debug/State Register
          6. 10.3.1.3.6 PDMA ECC Support
        4. 10.3.1.4 PDMA Registers
          1. 10.3.1.4.1 PDMA5 ECC Registers
          2. 10.3.1.4.2 PDMA9 ECC Registers
          3. 10.3.1.4.3 PDMA10 ECC Registers
          4. 10.3.1.4.4 PDMA PSI-L TX Configuration Registers
          5. 10.3.1.4.5 PDMA PSI-L RX Configuration Registers
      2. 10.3.2 PDMA Sources
        1. 10.3.2.1 MCU Domain PDMA Event Maps
          1. 10.3.2.1.1 MCU_PDMA_MISC_G0 Event Map
          2. 10.3.2.1.2 MCU_PDMA_MISC_G1 Event Map
          3. 10.3.2.1.3 MCU_PDMA_MISC_G2 Event Map
          4. 10.3.2.1.4 MCU_PDMA_ADC Event Map
        2. 10.3.2.2 MAIN Domain PDMA Event Maps
          1. 10.3.2.2.1 PDMA_DEBUG_CCMCU Event Map
          2. 10.3.2.2.2 PDMA_MCAN Event Map
          3. 10.3.2.2.3 PDMA_MCASP_G0 Event Map
          4. 10.3.2.2.4 PDMA_SPI_G0 Event Map
          5. 10.3.2.2.5 PDMA_SPI_G1 Event Map
          6. 10.3.2.2.6 PDMA_USART_G0 Event Map
          7. 10.3.2.2.7 PDMA_USART_G1 Event Map
          8. 10.3.2.2.8 PDMA_USART_G2 Event Map
  13. 11Time Sync
    1. 11.1 Time Sync Module (CPTS)
      1. 11.1.1 CPTS Overview
        1. 11.1.1.1 CPTS Features
        2. 11.1.1.2 CPTS Not Supported Features
      2. 11.1.2 CPTS Integration
      3. 11.1.3 CPTS Functional Description
        1. 11.1.3.1  CPTS Architecture
        2. 11.1.3.2  CPTS Initialization
        3. 11.1.3.3  32-bit Time Stamp Value
        4. 11.1.3.4  64-bit Time Stamp Value
          1. 11.1.3.4.1 64-Bit Timestamp Nudge
          2. 11.1.3.4.2 64-bit Timestamp PPM
        5. 11.1.3.5  Event FIFO
        6. 11.1.3.6  Timestamp Compare Output
          1. 11.1.3.6.1 Non-Toggle Mode
          2. 11.1.3.6.2 Toggle Mode
        7. 11.1.3.7  Timestamp Sync Output
        8. 11.1.3.8  Timestamp GENF Output
          1. 11.1.3.8.1 GENFn Nudge
          2. 11.1.3.8.2 GENFn PPM
        9. 11.1.3.9  Time Sync Events
          1. 11.1.3.9.1 Time Stamp Push Event
          2. 11.1.3.9.2 Time Stamp Counter Rollover Event (32-bit mode only)
          3. 11.1.3.9.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
          4. 11.1.3.9.4 Hardware Time Stamp Push Event
        10. 11.1.3.10 Timestamp Compare Event
        11. 11.1.3.11 CPTS Interrupt Handling
      4. 11.1.4 CPTS Registers
    2. 11.2 Timer Manager
      1. 11.2.1 Timer Manager Overview
        1. 11.2.1.1 Timer Manager Features
        2. 11.2.1.2 Timer Manager Not Supported Features
      2. 11.2.2 Timer Manager Integration
      3. 11.2.3 Timer Manager Functional Description
        1. 11.2.3.1 Timer Manager Function Overview
        2. 11.2.3.2 Timer Counter
          1. 11.2.3.2.1 Timer Counter Rollover
        3. 11.2.3.3 Timer Control Module (FSM)
        4. 11.2.3.4 Timer Reprogramming
          1. 11.2.3.4.1 Periodic Hardware Timers
        5. 11.2.3.5 Event FIFO
        6. 11.2.3.6 Output Event Lookup (OES RAM)
      4. 11.2.4 Timer Manager Programming Guide
        1. 11.2.4.1 Timer Manager Low-level Programming Models
          1. 11.2.4.1.1 Surrounding Modules Global Initialization
          2. 11.2.4.1.2 Initialization Sequence
          3. 11.2.4.1.3 Real-time Operating Requirements
            1. 11.2.4.1.3.1 Timer Touch
            2. 11.2.4.1.3.2 Timer Disable
            3. 11.2.4.1.3.3 Timer Enable
          4. 11.2.4.1.4 Power Up/Power Down Sequence
      5. 11.2.5 Timer Manager Registers
        1. 11.2.5.1 TIMERMGR_CFG_CFG Registers
        2. 11.2.5.2 TIMERMGR_CFG_OES Registers
        3. 11.2.5.3 TIMERMGR_CFG_TIMERS Registers
    3. 11.3 Time Sync and Compare Events
      1. 11.3.1 Time Sync Architecture
        1. 11.3.1.1 Time Sync Architecture Overview
      2. 11.3.2 Time Sync Routers
        1. 11.3.2.1 Time Sync Routers Overview
        2. 11.3.2.2 Time Sync Routers Integration
          1. 11.3.2.2.1 TIMESYNC_INTRTR0 Integration
          2. 11.3.2.2.2 CMPEVT_INTRTR0 Integration
        3. 11.3.2.3 Time Sync Routers Registers
          1. 11.3.2.3.1 TIMESYNC_INTRTR0 Registers
          2. 11.3.2.3.2 CMPEVT_INTRTR0 Registers
      3. 11.3.3 Time Sync Event Sources
        1. 11.3.3.1 CMPEVT_INTRTR0 Event Map
        2. 11.3.3.2 TIMESYNC_INTRTR0 Event Map
        3. 11.3.3.3 DMSS0 Sync Event Map
        4. 11.3.3.4 PCIE1 Sync Event Map
        5. 11.3.3.5 MCU_CPSW0 Sync Event Map
        6. 11.3.3.6 CPSW0 Sync Event Map
        7. 11.3.3.7 I/O Sync Event Map
  14. 12Peripherals
    1. 12.1 General Connectivity Peripherals
      1. 12.1.1 Analog-to-Digital Converter (ADC)
        1. 12.1.1.1 ADC Overview
          1. 12.1.1.1.1 ADC Features
          2. 12.1.1.1.2 ADC Not Supported Features
        2. 12.1.1.2 ADC Environment
          1. 12.1.1.2.1 ADC Interface Signals
        3. 12.1.1.3 ADC Integration
          1. 12.1.1.3.1 ADC Integration in MCU Domain
        4. 12.1.1.4 ADC Functional Description
          1. 12.1.1.4.1 ADC FSM Sequencer Functional Description
            1. 12.1.1.4.1.1 Step Enable
            2. 12.1.1.4.1.2 Step Configuration
              1. 12.1.1.4.1.2.1 One-Shot (Single) or Continuous Mode
              2. 12.1.1.4.1.2.2 Software- or Hardware-Enabled Steps
              3. 12.1.1.4.1.2.3 Averaging of Samples
              4. 12.1.1.4.1.2.4 Analog Multiplexer Input Select
              5. 12.1.1.4.1.2.5 Differential Control
              6. 12.1.1.4.1.2.6 FIFO Select
              7. 12.1.1.4.1.2.7 Range Check Interrupt Enable
            3. 12.1.1.4.1.3 Open Delay and Sample Delay
              1. 12.1.1.4.1.3.1 Open Delay
              2. 12.1.1.4.1.3.2 Sample Delay
            4. 12.1.1.4.1.4 Interrupts
            5. 12.1.1.4.1.5 Power Management
            6. 12.1.1.4.1.6 DMA Requests
          2. 12.1.1.4.2 ADC AFE Functional Description
            1. 12.1.1.4.2.1 AFE Functional Block Diagram
            2. 12.1.1.4.2.2 ADC GPI Integration
          3. 12.1.1.4.3 ADC FIFOs and DMA
            1. 12.1.1.4.3.1 FIFOs
            2. 12.1.1.4.3.2 DMA
          4. 12.1.1.4.4 ADC Error Correcting Code (ECC)
            1. 12.1.1.4.4.1 Testing ECC Error Injection
          5. 12.1.1.4.5 ADC Functional Internal Diagnostic Debug Mode
        5. 12.1.1.5 ADC Programming Guide
          1. 12.1.1.5.1 ADC Low-Level Programming Models
            1. 12.1.1.5.1.1 Global Initialization
              1. 12.1.1.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.1.5.1.1.2 General Programming Model
            2. 12.1.1.5.1.2 During Operation
        6. 12.1.1.6 ADC Registers
      2. 12.1.2 General-Purpose Interface (GPIO)
        1. 12.1.2.1 GPIO Overview
          1. 12.1.2.1.1 GPIO Features
          2. 12.1.2.1.2 GPIO Not Supported Features
        2. 12.1.2.2 GPIO Environment
          1. 12.1.2.2.1 GPIO Interface Signals
        3. 12.1.2.3 GPIO Integration
          1. 12.1.2.3.1 GPIO Integration in WKUP Domain
          2. 12.1.2.3.2 GPIO Integration in MAIN Domain
        4. 12.1.2.4 GPIO Functional Description
          1. 12.1.2.4.1 GPIO Block Diagram
          2. 12.1.2.4.2 GPIO Function
          3. 12.1.2.4.3 GPIO Interrupt and Event Generation
            1. 12.1.2.4.3.1 Interrupt Enable (per Bank)
            2. 12.1.2.4.3.2 Trigger Configuration (per Bit)
            3. 12.1.2.4.3.3 Interrupt Status and Clear (per Bit)
          4. 12.1.2.4.4 GPIO Interrupt Connectivity
          5. 12.1.2.4.5 GPIO DeepSleep Mode
          6. 12.1.2.4.6 GPIO Emulation Halt Operation
        5. 12.1.2.5 GPIO Programming Guide
          1. 12.1.2.5.1 GPIO Low-Level Programming Models
            1. 12.1.2.5.1.1 Global Initialization
              1. 12.1.2.5.1.1.1 Surrounding Modules Global Initialization
              2. 12.1.2.5.1.1.2 GPIO Module Global Initialization
            2. 12.1.2.5.1.2 GPIO Operational Modes Configuration
              1. 12.1.2.5.1.2.1 GPIO Read Input Register
              2. 12.1.2.5.1.2.2 GPIO Set Bit Function
              3. 12.1.2.5.1.2.3 GPIO Clear Bit Function
        6. 12.1.2.6 GPIO Registers
      3. 12.1.3 Inter-Integrated Circuit (I2C) Interface
        1. 12.1.3.1 I2C Overview
          1. 12.1.3.1.1 I2C Features
          2. 12.1.3.1.2 I2C Not Supported Features
        2. 12.1.3.2 I2C Environment
          1. 12.1.3.2.1 I2C Typical Application
            1. 12.1.3.2.1.1 I2C Pins for Typical Connections in I2C Mode
            2. 12.1.3.2.1.2 I2C Interface Typical Connections
            3. 12.1.3.2.1.3 1501
          2. 12.1.3.2.2 I2C Typical Connection Protocol and Data Format
            1. 12.1.3.2.2.1  I2C Serial Data Format
            2. 12.1.3.2.2.2  I2C Data Validity
            3. 12.1.3.2.2.3  I2C Start and Stop Conditions
            4. 12.1.3.2.2.4  I2C Addressing
              1. 12.1.3.2.2.4.1 Data Transfer Formats in F/S Mode
              2. 12.1.3.2.2.4.2 Data Transfer Format in HS Mode
            5. 12.1.3.2.2.5  I2C Controller Transmitter
            6. 12.1.3.2.2.6  I2C Controller Receiver
            7. 12.1.3.2.2.7  I2C Target Transmitter
            8. 12.1.3.2.2.8  I2C Target Receiver
            9. 12.1.3.2.2.9  I2C Bus Arbitration
            10. 12.1.3.2.2.10 I2C Clock Generation and Synchronization
        3. 12.1.3.3 I2C Integration
          1. 12.1.3.3.1 I2C Integration in WKUP Domain
          2. 12.1.3.3.2 I2C Integration in MCU Domain
          3. 12.1.3.3.3 I2C Integration in MAIN Domain
        4. 12.1.3.4 I2C Functional Description
          1. 12.1.3.4.1 I2C Block Diagram
          2. 12.1.3.4.2 I2C Clocks
            1. 12.1.3.4.2.1 I2C Clocking
            2. 12.1.3.4.2.2 I2C Automatic Blocking of the I2C Clock Feature
          3. 12.1.3.4.3 I2C Software Reset
          4. 12.1.3.4.4 I2C Power Management
          5. 12.1.3.4.5 I2C Interrupt Requests
          6. 12.1.3.4.6 I2C Programmable Multitarget Channel Feature
          7. 12.1.3.4.7 I2C FIFO Management
            1. 12.1.3.4.7.1 I2C FIFO Interrupt Mode
            2. 12.1.3.4.7.2 I2C FIFO Polling Mode
            3. 12.1.3.4.7.3 I2C Draining Feature
          8. 12.1.3.4.8 I2C Noise Filter
          9. 12.1.3.4.9 I2C System Test Mode
        5. 12.1.3.5 I2C Programming Guide
          1. 12.1.3.5.1 I2C Low-Level Programming Models
            1. 12.1.3.5.1.1 I2C Programming Model
              1. 12.1.3.5.1.1.1 Main Program
                1. 12.1.3.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
                2. 12.1.3.5.1.1.1.2 Initialize the I2C Controller
                3. 12.1.3.5.1.1.1.3 Configure Target Address and the Data Control Register
                4. 12.1.3.5.1.1.1.4 Initiate a Transfer
                5. 12.1.3.5.1.1.1.5 Receive Data
                6. 12.1.3.5.1.1.1.6 Transmit Data
              2. 12.1.3.5.1.1.2 Interrupt Subroutine Sequence
              3. 12.1.3.5.1.1.3 Programming Flow-Diagrams
        6. 12.1.3.6 I2C Registers
      4. 12.1.4 Improved Inter-Integrated Circuit (I3C) Interface
        1. 12.1.4.1 I3C Overview
          1. 12.1.4.1.1 I3C Features
          2. 12.1.4.1.2 I3C Not Supported Features
        2. 12.1.4.2 I3C Environment
          1. 12.1.4.2.1 I3C Typical Application
            1. 12.1.4.2.1.1 I3C Pins for Typical Connections
            2. 12.1.4.2.1.2 I3C Interface Typical Connections
            3. 12.1.4.2.1.3 1555
        3. 12.1.4.3 I3C Integration
          1. 12.1.4.3.1 I3C Integration in MCU Domain
          2. 12.1.4.3.2 I3C Integration in MAIN Domain
        4. 12.1.4.4 I3C Functional Description
          1. 12.1.4.4.1  I3C Block Diagram
          2. 12.1.4.4.2  I3C Clock Configuration
            1. 12.1.4.4.2.1 Setting Base Frequencies
            2. 12.1.4.4.2.2 Asymmetric Push-Pull SCL Timing
            3. 12.1.4.4.2.3 Open-Drain SCL Timing
            4. 12.1.4.4.2.4 Changing Programmed Frequencies
          3. 12.1.4.4.3  I3C Interrupt Requests
          4. 12.1.4.4.4  I3C Power Configuration
          5. 12.1.4.4.5  I3C Dynamic Address Management
          6. 12.1.4.4.6  I3C Retaining Registers Space
          7. 12.1.4.4.7  I3C Dynamic Address Assignment Procedure
          8. 12.1.4.4.8  I3C Sending CCC Messages
          9. 12.1.4.4.9  I3C In-Band Interrupt
            1. 12.1.4.4.9.1 Regular I3C Slave In-Band Interrupt
            2. 12.1.4.4.9.2 Current Master Takeover In-Band Interrupt
          10. 12.1.4.4.10 I3C Hot-Join Request
          11. 12.1.4.4.11 I3C Immediate Commands
          12. 12.1.4.4.12 I3C Host Commands
          13. 12.1.4.4.13 I3C Sending Private Data in SDR Messages
            1. 12.1.4.4.13.1 SDR Private Write Message
            2. 12.1.4.4.13.2 SDR Private Read Message
            3. 12.1.4.4.13.3 SDR Payload Length Adjustment
        5. 12.1.4.5 I3C Programming Guide
          1. 12.1.4.5.1 I3C Power-On Programming Model
          2. 12.1.4.5.2 I3C Static Devices Programming
          3. 12.1.4.5.3 I3C DAA Procedure Initiation
          4. 12.1.4.5.4 I3C SDR Write Message Programming Model
          5. 12.1.4.5.5 I3C SDR Read Message Programming Model
          6. 12.1.4.5.6 I3C DDR Write Message Programming Model
          7. 12.1.4.5.7 I3C DDR Read Message Programming Model
        6. 12.1.4.6 I3C Registers
      5. 12.1.5 Multichannel Serial Peripheral Interface (MCSPI)
        1. 12.1.5.1 MCSPI Overview
          1. 12.1.5.1.1 SPI Features
          2. 12.1.5.1.2 MCSPI Not Supported Features
        2. 12.1.5.2 MCSPI Environment
          1. 12.1.5.2.1 Basic MCSPI Pins for Master Mode
          2. 12.1.5.2.2 Basic MCSPI Pins for Slave Mode
          3. 12.1.5.2.3 MCSPI Internal Connectivity
          4. 12.1.5.2.4 MCSPI Protocol and Data Format
            1. 12.1.5.2.4.1 Transfer Format
          5. 12.1.5.2.5 MCSPI in Controller Mode
          6. 12.1.5.2.6 MCSPI in Peripheral Mode
        3. 12.1.5.3 MCSPI Integration
          1. 12.1.5.3.1 MCSPI Integration in MCU Domain
          2. 12.1.5.3.2 MCSPI Integration in MAIN Domain
        4. 12.1.5.4 MCSPI Functional Description
          1. 12.1.5.4.1 SPI Block Diagram
          2. 12.1.5.4.2 MCSPI Reset
          3. 12.1.5.4.3 MCSPI Controller Mode
            1. 12.1.5.4.3.1 Controller Mode Features
            2. 12.1.5.4.3.2 Controller Transmit-and-Receive Mode (Full Duplex)
            3. 12.1.5.4.3.3 Controller Transmit-Only Mode (Half Duplex)
            4. 12.1.5.4.3.4 Controller Receive-Only Mode (Half Duplex)
            5. 12.1.5.4.3.5 Single-Channel Controller Mode
              1. 12.1.5.4.3.5.1 Programming Tips When Switching to Another Channel
              2. 12.1.5.4.3.5.2 Force SPIEN[i] Mode
              3. 12.1.5.4.3.5.3 Turbo Mode
            6. 12.1.5.4.3.6 Start-Bit Mode
            7. 12.1.5.4.3.7 Chip-Select Timing Control
            8. 12.1.5.4.3.8 Programmable MCSPI Clock (SPICLK)
              1. 12.1.5.4.3.8.1 Clock Ratio Granularity
          4. 12.1.5.4.4 MCSPI Peripheral Mode
            1. 12.1.5.4.4.1 Dedicated Resources
            2. 12.1.5.4.4.2 Peripheral Transmit-and-Receive Mode
            3. 12.1.5.4.4.3 Peripheral Transmit-Only Mode
            4. 12.1.5.4.4.4 Peripheral Receive-Only Mode
          5. 12.1.5.4.5 MCSPI 3-Pin or 4-Pin Mode
          6. 12.1.5.4.6 MCSPI FIFO Buffer Management
            1. 12.1.5.4.6.1 Buffer Almost Full
            2. 12.1.5.4.6.2 Buffer Almost Empty
            3. 12.1.5.4.6.3 End of Transfer Management
            4. 12.1.5.4.6.4 Multiple MCSPI Word Access
            5. 12.1.5.4.6.5 First MCSPI Word Delay
          7. 12.1.5.4.7 MCSPI Interrupts
            1. 12.1.5.4.7.1 Interrupt Events in Controller Mode
              1. 12.1.5.4.7.1.1 TXx_EMPTY
              2. 12.1.5.4.7.1.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.1.3 RXx_ FULL
              4. 12.1.5.4.7.1.4 End Of Word Count
            2. 12.1.5.4.7.2 Interrupt Events in Peripheral Mode
              1. 12.1.5.4.7.2.1 TXx_EMPTY
              2. 12.1.5.4.7.2.2 TXx_UNDERFLOW
              3. 12.1.5.4.7.2.3 RXx_FULL
              4. 12.1.5.4.7.2.4 RX0_OVERFLOW
              5. 12.1.5.4.7.2.5 End Of Word Count
            3. 12.1.5.4.7.3 Interrupt-Driven Operation
            4. 12.1.5.4.7.4 Polling
          8. 12.1.5.4.8 MCSPI DMA Requests
          9. 12.1.5.4.9 MCSPI Power Saving Management
            1. 12.1.5.4.9.1 Normal Mode
            2. 12.1.5.4.9.2 Idle Mode
              1. 12.1.5.4.9.2.1 Force-Idle Mode
        5. 12.1.5.5 MCSPI Programming Guide
          1. 12.1.5.5.1 MCSPI Global Initialization
            1. 12.1.5.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.5.5.1.2 MCSPI Global Initialization
              1. 12.1.5.5.1.2.1 Main Sequence – MCSPI Global Initialization
          2. 12.1.5.5.2 MCSPI Operational Mode Configuration
            1. 12.1.5.5.2.1 MCSPI Operational Modes
              1. 12.1.5.5.2.1.1 Common Transfer Sequence
              2. 12.1.5.5.2.1.2 End of Transfer Sequences
              3. 12.1.5.5.2.1.3 Transmit-and-Receive (Controller and Peripheral)
              4. 12.1.5.5.2.1.4 Transmit-Only (Controller and Peripheral)
                1. 12.1.5.5.2.1.4.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.4.2 Based on DMA Write Requests
              5. 12.1.5.5.2.1.5 Controller Normal Receive-Only
                1. 12.1.5.5.2.1.5.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.5.2 Based on DMA Read Requests
              6. 12.1.5.5.2.1.6 Controller Turbo Receive-Only
                1. 12.1.5.5.2.1.6.1 Based on Interrupt Requests
                2. 12.1.5.5.2.1.6.2 Based on DMA Read Requests
              7. 12.1.5.5.2.1.7 Peripheral Receive-Only
              8. 12.1.5.5.2.1.8 Transfer Procedures With FIFO
                1. 12.1.5.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
                2. 12.1.5.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
                3. 12.1.5.5.2.1.8.3 Transmit-and-Receive With Word Count
                4. 12.1.5.5.2.1.8.4 Transmit-and-Receive Without Word Count
                5. 12.1.5.5.2.1.8.5 Transmit-Only
                6. 12.1.5.5.2.1.8.6 Receive-Only With Word Count
                7. 12.1.5.5.2.1.8.7 Receive-Only Without Word Count
              9. 12.1.5.5.2.1.9 Common Transfer Procedures Without FIFO – Polling Method
                1. 12.1.5.5.2.1.9.1 Receive-Only Procedure – Polling Method
                2. 12.1.5.5.2.1.9.2 Receive-Only Procedure – Interrupt Method
                3. 12.1.5.5.2.1.9.3 Transmit-Only Procedure – Polling Method
                4. 12.1.5.5.2.1.9.4 Transmit-and-Receive Procedure – Polling Method
        6. 12.1.5.6 MCSPI Registers
      6. 12.1.6 Universal Asynchronous Receiver/Transmitter (UART)
        1. 12.1.6.1 UART Overview
          1. 12.1.6.1.1 UART Features
          2. 12.1.6.1.2 IrDA Features
          3. 12.1.6.1.3 CIR Features
          4. 12.1.6.1.4 UART Not Supported Features
        2. 12.1.6.2 UART Environment
          1. 12.1.6.2.1 UART Functional Interfaces
            1. 12.1.6.2.1.1 System Using UART Communication With Hardware Handshake
            2. 12.1.6.2.1.2 UART Interface Description
            3. 12.1.6.2.1.3 UART Protocol and Data Format
            4. 12.1.6.2.1.4 UART 9-bit Mode Data Format
          2. 12.1.6.2.2 RS-485 Functional Interfaces
            1. 12.1.6.2.2.1 System Using RS-485 Communication
            2. 12.1.6.2.2.2 RS-485 Interface Description
          3. 12.1.6.2.3 IrDA Functional Interfaces
            1. 12.1.6.2.3.1 System Using IrDA Communication Protocol
            2. 12.1.6.2.3.2 IrDA Interface Description
            3. 12.1.6.2.3.3 IrDA Protocol and Data Format
              1. 12.1.6.2.3.3.1 SIR Mode
                1. 12.1.6.2.3.3.1.1 Frame Format
                2. 12.1.6.2.3.3.1.2 Asynchronous Transparency
                3. 12.1.6.2.3.3.1.3 Abort Sequence
                4. 12.1.6.2.3.3.1.4 Pulse Shaping
                5. 12.1.6.2.3.3.1.5 Encoder
                6. 12.1.6.2.3.3.1.6 Decoder
                7. 12.1.6.2.3.3.1.7 IR Address Checking
              2. 12.1.6.2.3.3.2 SIR Free-Format Mode
              3. 12.1.6.2.3.3.3 MIR Mode
                1. 12.1.6.2.3.3.3.1 MIR Encoder/Decoder
                2. 12.1.6.2.3.3.3.2 SIP Generation
              4. 12.1.6.2.3.3.4 FIR Mode
          4. 12.1.6.2.4 CIR Functional Interfaces
            1. 12.1.6.2.4.1 System Using CIR Communication Protocol With Remote Control
            2. 12.1.6.2.4.2 CIR Interface Description
            3. 12.1.6.2.4.3 CIR Protocol and Data Format
              1. 12.1.6.2.4.3.1 Carrier Modulation
              2. 12.1.6.2.4.3.2 Pulse Duty Cycle
              3. 12.1.6.2.4.3.3 Consumer IR Encoding/Decoding
        3. 12.1.6.3 UART Integration
          1. 12.1.6.3.1 UART Integration in WKUP Domain
          2. 12.1.6.3.2 UART Integration in MCU Domain
          3. 12.1.6.3.3 UART Integration in MAIN Domain
        4. 12.1.6.4 UART Functional Description
          1. 12.1.6.4.1 UART Block Diagram
          2. 12.1.6.4.2 UART Clock Configuration
          3. 12.1.6.4.3 UART Software Reset
            1. 12.1.6.4.3.1 Independent TX/RX
          4. 12.1.6.4.4 UART Power Management
            1. 12.1.6.4.4.1 UART Mode Power Management
              1. 12.1.6.4.4.1.1 Module Power Saving
              2. 12.1.6.4.4.1.2 System Power Saving
            2. 12.1.6.4.4.2 IrDA Mode Power Management
              1. 12.1.6.4.4.2.1 Module Power Saving
              2. 12.1.6.4.4.2.2 System Power Saving
            3. 12.1.6.4.4.3 CIR Mode Power Management
              1. 12.1.6.4.4.3.1 Module Power Saving
              2. 12.1.6.4.4.3.2 System Power Saving
            4. 12.1.6.4.4.4 Local Power Management
          5. 12.1.6.4.5 UART Interrupt Requests
            1. 12.1.6.4.5.1 UART Mode Interrupt Management
              1. 12.1.6.4.5.1.1 UART Interrupts
              2. 12.1.6.4.5.1.2 Wake-Up Interrupt
            2. 12.1.6.4.5.2 IrDA Mode Interrupt Management
              1. 12.1.6.4.5.2.1 IrDA Interrupts
              2. 12.1.6.4.5.2.2 Wake-Up Interrupts
            3. 12.1.6.4.5.3 CIR Mode Interrupt Management
              1. 12.1.6.4.5.3.1 CIR Interrupts
              2. 12.1.6.4.5.3.2 Wake-Up Interrupts
          6. 12.1.6.4.6 UART FIFO Management
            1. 12.1.6.4.6.1 FIFO Trigger
              1. 12.1.6.4.6.1.1 Transmit FIFO Trigger
              2. 12.1.6.4.6.1.2 Receive FIFO Trigger
            2. 12.1.6.4.6.2 FIFO Interrupt Mode
            3. 12.1.6.4.6.3 FIFO Polled Mode Operation
            4. 12.1.6.4.6.4 FIFO DMA Mode Operation
              1. 12.1.6.4.6.4.1 DMA sequence to disable TX DMA
              2. 12.1.6.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
              3. 12.1.6.4.6.4.3 DMA Transmission
              4. 12.1.6.4.6.4.4 DMA Reception
          7. 12.1.6.4.7 UART Mode Selection
            1. 12.1.6.4.7.1 Register Access Modes
              1. 12.1.6.4.7.1.1 Operational Mode and Configuration Modes
              2. 12.1.6.4.7.1.2 Register Access Submode
              3. 12.1.6.4.7.1.3 Registers Available for the Register Access Modes
            2. 12.1.6.4.7.2 UART/RS-485/IrDA (SIR, MIR, FIR)/CIR Mode Selection
              1. 12.1.6.4.7.2.1 Registers Available for the UART Function
              2. 12.1.6.4.7.2.2 Registers Available for the IrDA Function
              3. 12.1.6.4.7.2.3 Registers Available for the CIR Function
          8. 12.1.6.4.8 UART Protocol Formatting
            1. 12.1.6.4.8.1 UART Mode
              1. 12.1.6.4.8.1.1 UART Clock Generation: Baud Rate Generation
              2. 12.1.6.4.8.1.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.1.3 UART Data Formatting
                1. 12.1.6.4.8.1.3.1 Frame Formatting
                2. 12.1.6.4.8.1.3.2 Hardware Flow Control
                3. 12.1.6.4.8.1.3.3 Software Flow Control
                  1. 1.6.4.8.1.3.3.1 Receive (RX)
                  2. 1.6.4.8.1.3.3.2 Transmit (TX)
                4. 12.1.6.4.8.1.3.4 Autobauding Modes
                5. 12.1.6.4.8.1.3.5 Error Detection
                6. 12.1.6.4.8.1.3.6 Overrun During Receive
                7. 12.1.6.4.8.1.3.7 Time-Out and Break Conditions
                  1. 1.6.4.8.1.3.7.1 Time-Out Counter
                  2. 1.6.4.8.1.3.7.2 Break Condition
            2. 12.1.6.4.8.2 RS-485 Mode
              1. 12.1.6.4.8.2.1 RS-485 External Transceiver Direction Control
            3. 12.1.6.4.8.3 IrDA Mode
              1. 12.1.6.4.8.3.1 IrDA Clock Generation: Baud Generator
              2. 12.1.6.4.8.3.2 Choosing the Appropriate Divisor Value
              3. 12.1.6.4.8.3.3 IrDA Data Formatting
                1. 12.1.6.4.8.3.3.1  IR RX Polarity Control
                2. 12.1.6.4.8.3.3.2  IrDA Reception Control
                3. 12.1.6.4.8.3.3.3  IR Address Checking
                4. 12.1.6.4.8.3.3.4  Frame Closing
                5. 12.1.6.4.8.3.3.5  Store and Controlled Transmission
                6. 12.1.6.4.8.3.3.6  Error Detection
                7. 12.1.6.4.8.3.3.7  Underrun During Transmission
                8. 12.1.6.4.8.3.3.8  Overrun During Receive
                9. 12.1.6.4.8.3.3.9  Status FIFO
                10. 12.1.6.4.8.3.3.10 Multi-drop Parity Mode with Address Match
                11. 12.1.6.4.8.3.3.11 Time-guard
              4. 12.1.6.4.8.3.4 SIR Mode Data Formatting
                1. 12.1.6.4.8.3.4.1 Abort Sequence
                2. 12.1.6.4.8.3.4.2 Pulse Shaping
                3. 12.1.6.4.8.3.4.3 SIR Free Format Programming
              5. 12.1.6.4.8.3.5 MIR and FIR Mode Data Formatting
            4. 12.1.6.4.8.4 CIR Mode
              1. 12.1.6.4.8.4.1 CIR Mode Clock Generation
              2. 12.1.6.4.8.4.2 CIR Data Formatting
                1. 12.1.6.4.8.4.2.1 IR RX Polarity Control
                2. 12.1.6.4.8.4.2.2 CIR Transmission
                3. 12.1.6.4.8.4.2.3 CIR Reception
        5. 12.1.6.5 UART Programming Guide
          1. 12.1.6.5.1 UART Global Initialization
            1. 12.1.6.5.1.1 Surrounding Modules Global Initialization
            2. 12.1.6.5.1.2 UART Module Global Initialization
          2. 12.1.6.5.2 UART Mode selection
          3. 12.1.6.5.3 UART Submode selection
          4. 12.1.6.5.4 UART Load FIFO trigger and DMA mode settings
            1. 12.1.6.5.4.1 DMA mode Settings
            2. 12.1.6.5.4.2 FIFO Trigger Settings
          5. 12.1.6.5.5 UART Protocol, Baud rate and interrupt settings
            1. 12.1.6.5.5.1 Baud rate settings
            2. 12.1.6.5.5.2 Interrupt settings
            3. 12.1.6.5.5.3 Protocol settings
            4. 12.1.6.5.5.4 UART/RS-485/IrDA(SIR/MIR/FIR)/CIR
            5. 12.1.6.5.5.5 UART Multi-drop Parity Address Match Mode Configuration
          6. 12.1.6.5.6 UART Hardware and Software Flow Control Configuration
            1. 12.1.6.5.6.1 Hardware Flow Control Configuration
            2. 12.1.6.5.6.2 Software Flow Control Configuration
          7. 12.1.6.5.7 IrDA Programming Model
            1. 12.1.6.5.7.1 SIR mode
              1. 12.1.6.5.7.1.1 Receive
              2. 12.1.6.5.7.1.2 Transmit
            2. 12.1.6.5.7.2 MIR mode
              1. 12.1.6.5.7.2.1 Receive
              2. 12.1.6.5.7.2.2 Transmit
            3. 12.1.6.5.7.3 FIR mode
              1. 12.1.6.5.7.3.1 Receive
              2. 12.1.6.5.7.3.2 Transmit
        6. 12.1.6.6 UART Registers
    2. 12.2 High-speed Serial Interfaces
      1. 12.2.1 Gigabit Ethernet MAC (MCU_CPSW0)
        1. 12.2.1.1 MCU_CPSW0 Overview
          1. 12.2.1.1.1 MCU_CPSW0 Features
          2. 12.2.1.1.2 MCU_CPSW0 Not Supported Features
          3. 12.2.1.1.3 Terminology
        2. 12.2.1.2 MCU_CPSW0 Environment
          1. 12.2.1.2.1 MCU_CPSW0 RMII Interface
          2. 12.2.1.2.2 MCU_CPSW0 RGMII Interface
        3. 12.2.1.3 MCU_CPSW0 Integration
        4. 12.2.1.4 MCU_CPSW0 Functional Description
          1. 12.2.1.4.1 Functional Block Diagram
          2. 12.2.1.4.2 CPSW Ports
            1. 12.2.1.4.2.1 Interface Mode Selection
          3. 12.2.1.4.3 Clocking
            1. 12.2.1.4.3.1 Subsystem Clocking
            2. 12.2.1.4.3.2 Interface Clocking
              1. 12.2.1.4.3.2.1 RGMII Interface Clocking
              2. 12.2.1.4.3.2.2 RMII Interface Clocking
              3. 12.2.1.4.3.2.3 MDIO Clocking
          4. 12.2.1.4.4 Software IDLE
          5. 12.2.1.4.5 Interrupt Functionality
            1. 12.2.1.4.5.1 EVNT_PEND Interrupt
            2. 12.2.1.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.1.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.1.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.1.4.5.5 MDIO Interrupts
          6. 12.2.1.4.6 CPSW_2G
            1. 12.2.1.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.1.4.6.1.1  Error Handling
              2. 12.2.1.4.6.1.2  Bypass Operations
              3. 12.2.1.4.6.1.3  OUI Deny or Accept
              4. 12.2.1.4.6.1.4  Statistics Counting
              5. 12.2.1.4.6.1.5  Automotive Security Features
              6. 12.2.1.4.6.1.6  CPSW Switching Solutions
                1. 12.2.1.4.6.1.6.1 Basics of 2-port Switch Type
              7. 12.2.1.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.1.4.6.1.7.1 InterVLAN Routing
                2. 12.2.1.4.6.1.7.2 OAM Operations
              8. 12.2.1.4.6.1.8  Supervisory packets
              9. 12.2.1.4.6.1.9  Address Table Entry
                1. 12.2.1.4.6.1.9.1 Free Table Entry
                2. 12.2.1.4.6.1.9.2 Multicast Address Table Entry
                3. 12.2.1.4.6.1.9.3 VLAN/Multicast Address Table Entry
                4. 12.2.1.4.6.1.9.4 Unicast Address Table Entry
                5. 12.2.1.4.6.1.9.5 OUI Unicast Address Table Entry
                6. 12.2.1.4.6.1.9.6 VLAN/Unicast Address Table Entry
                7. 12.2.1.4.6.1.9.7 VLAN Table Entry
              10. 12.2.1.4.6.1.10 ALE Policing and Classification
                1. 12.2.1.4.6.1.10.1 ALE Classification
                  1. 2.1.4.6.1.10.1.1 Classifier to CPPI Transmit Flow ID Mapping
              11. 12.2.1.4.6.1.11 DSCP
              12. 12.2.1.4.6.1.12 Packet Forwarding Processes
                1. 12.2.1.4.6.1.12.1 Ingress Filtering Process
                2. 12.2.1.4.6.1.12.2 VLAN_Aware Lookup Process
                3. 12.2.1.4.6.1.12.3 Egress Process
                4. 12.2.1.4.6.1.12.4 Learning/Updating/Touching Processes
                  1. 2.1.4.6.1.12.4.1 Learning Process
                  2. 2.1.4.6.1.12.4.2 Updating Process
                  3. 2.1.4.6.1.12.4.3 Touching Process
              13. 12.2.1.4.6.1.13 VLAN Aware Mode
              14. 12.2.1.4.6.1.14 VLAN Unaware Mode
            2. 12.2.1.4.6.2  Packet Priority Handling
              1. 12.2.1.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.1.4.6.3  CPPI Port Ingress
            4. 12.2.1.4.6.4  Packet CRC Handling
              1. 12.2.1.4.6.4.1 Transmit VLAN Processing
                1. 12.2.1.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.1.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.1.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.1.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.1.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.1.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.1.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.1.4.6.5  FIFO Memory Control
            6. 12.2.1.4.6.6  FIFO Transmit Queue Control
              1. 12.2.1.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.1.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.1.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.1.4.6.7.1 IET Configuration
            8. 12.2.1.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.1.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.1.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.1.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.1.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.1.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.1.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
              7. 12.2.1.4.6.8.7 Enhanced Scheduled Traffic Packets Per Priority
            9. 12.2.1.4.6.9  Audio Video Bridging
              1. 12.2.1.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.1.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.1.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.1.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.1.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.1.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.1.4.6.10 Ethernet MAC Sliver
              1. 12.2.1.4.6.10.1 1945
                1. 12.2.1.4.6.10.1.1 1946
                  1. 2.1.4.6.10.1.1.1 CRC Insertion
                  2. 2.1.4.6.10.1.1.2 MTXER
                  3. 2.1.4.6.10.1.1.3 Adaptive Performance Optimization (APO)
                  4. 2.1.4.6.10.1.1.4 Inter-Packet-Gap Enforcement
                  5. 2.1.4.6.10.1.1.5 Back Off
                  6. 2.1.4.6.10.1.1.6 Programmable Transmit Inter-Packet Gap
                  7. 2.1.4.6.10.1.1.7 Speed, Duplex and Pause Frame Support Negotiation
              2. 12.2.1.4.6.10.2 RMII Interface
                1. 12.2.1.4.6.10.2.1 Features
                2. 12.2.1.4.6.10.2.2 RMII Receive (RX)
                3. 12.2.1.4.6.10.2.3 RMII Transmit (TX)
              3. 12.2.1.4.6.10.3 RGMII Interface
                1. 12.2.1.4.6.10.3.1 Features
                2. 12.2.1.4.6.10.3.2 RGMII Receive (RX)
                3. 12.2.1.4.6.10.3.3 In-Band Mode of Operation
                4. 12.2.1.4.6.10.3.4 Forced Mode of Operation
                5. 12.2.1.4.6.10.3.5 RGMII Transmit (TX)
              4. 12.2.1.4.6.10.4 Frame Classification
              5. 12.2.1.4.6.10.5 Receive FIFO Architecture
            11. 12.2.1.4.6.11 Embedded Memories
            12. 12.2.1.4.6.12 Memory Error Detection and Correction
              1. 12.2.1.4.6.12.1 Packet Header ECC
              2. 12.2.1.4.6.12.2 Packet Protect CRC
              3. 12.2.1.4.6.12.3 Aggregator RAM Control
            13. 12.2.1.4.6.13 Ethernet Port Flow Control
              1. 12.2.1.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.1.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.1.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.1.4.6.13.2 Flow Control Trigger
              3. 12.2.1.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.1.4.6.14 Energy Efficient Ethernet Support (802.3az)
            15. 12.2.1.4.6.15 Ethernet Switch Latency
            16. 12.2.1.4.6.16 MAC Emulation Control
            17. 12.2.1.4.6.17 MAC Command IDLE
            18. 12.2.1.4.6.18 CPSW Network Statistics
              1. 12.2.1.4.6.18.1  Rx-only Statistics Descriptions
                1. 12.2.1.4.6.18.1.1  Good Rx Frames (Offset = 3A000h - Port 0 or Offset = 3A200h - Port 1)
                2. 12.2.1.4.6.18.1.2  Broadcast Rx Frames (Offset = 3A004h - Port 0 or Offset = 3A204h - Port 1)
                3. 12.2.1.4.6.18.1.3  Multicast Rx Frames (Offset = 3A008h - Port 0 or Offset = 3A208h - Port 1)
                4. 12.2.1.4.6.18.1.4  Pause Rx Frames (Offset = 3A20Ch - Port 1)
                5. 12.2.1.4.6.18.1.5  Rx CRC Errors (Offset = 3A010h - Port 0 or Offset = 3A210h - Port 1)
                6. 12.2.1.4.6.18.1.6  Rx Align/Code Errors (Offset = 3A214h - Port 1)
                7. 12.2.1.4.6.18.1.7  Oversize Rx Frames (Offset = 3A018h - Port 0 or Offset = 3A218h - Port 1)
                8. 12.2.1.4.6.18.1.8  Rx Jabbers (Offset = 3A21Ch - Port 1)
                9. 12.2.1.4.6.18.1.9  Undersize (Short) Rx Frames (Offset = 3A020h- Port 0 or Offset = 3A220h - Port 1)
                10. 12.2.1.4.6.18.1.10 Rx Fragments (Offset = 3A024h - Port 0 or Offset = 3A224h - Port 1)
                11. 12.2.1.4.6.18.1.11 RX IPG Error (Offset = 3A25Ch - Port 1)
                12. 12.2.1.4.6.18.1.12 ALE Drop (Offset = 3A028h - Port 0 or Offset = 3A228h - Port 1)
                13. 12.2.1.4.6.18.1.13 ALE Overrun Drop (Offset = 3A02Ch - Port 0 or Offset = 3A22Ch - Port 1)
                14. 12.2.1.4.6.18.1.14 Rx Octets (Offset = 3A030h - Port 0 or Offset = 3A230h - Port 1)
                15. 12.2.1.4.6.18.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h - Port 0 or Offset = 3A284h - Port 1)
                16. 12.2.1.4.6.18.1.16 Portmask Drop (Offset = 3A088h - Port 0 or Offset = 3A288h - Port 1)
                17. 12.2.1.4.6.18.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch - Port 0 or Offset = 3A28Ch - Port 1)
                18. 12.2.1.4.6.18.1.18 ALE Rate Limit Drop (Offset = 3A090h - Port 0 or Offset = 3A290h - Port 1)
                19. 12.2.1.4.6.18.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h - Port 0 or Offset = 3A294h - Port 1)
                  1. 2.1.4.6.18.1.19.1  ALE DA=SA Drop (Offset = 3A098h - Port 0 or Offset = 3A298h - Port 1)
                  2. 2.1.4.6.18.1.19.2  Block Address Drop (Offset = 3A09Ch - Port 0 or Offset = 3A29Ch - Port 1)
                  3. 2.1.4.6.18.1.19.3  ALE Secure Drop (Offset = 3A0A0h - Port 0 or Offset = 3A2A0h - Port 1)
                  4. 2.1.4.6.18.1.19.4  ALE Authentication Drop (Offset = 3A0A4h - Port 0 or Offset = 3A2A4h - Port 1)
                  5. 2.1.4.6.18.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h - Port 0 or Offset = 3A2A8h - Port 1)
                  6. 2.1.4.6.18.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh - Port 0 or Offset = 3A2ACh - Port 1)
                  7. 2.1.4.6.18.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h - Port 0 or Offset = 3A2B0h - Port 1)
                  8. 2.1.4.6.18.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h - Port 0 or Offset = 3A2B4h - Port 1)
                  9. 2.1.4.6.18.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h - Port 0 or Offset = 3A2B8h - Port 1)
                  10. 2.1.4.6.18.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh - Port 0 or Offset = 3A2BCh - Port 1)
                  11. 2.1.4.6.18.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h - Port 0 or Offset = 3A2C0h - Port 1)
              2. 12.2.1.4.6.18.2  ALE Policer Match Red (Offset = 3A0C4h - Port 0 or Offset = 3A2C4h - Port 1)
              3. 12.2.1.4.6.18.3  ALE Policer Match Yellow (Offset = 3A0C8h - Port 0 or Offset = 3A2C8h - Port 1)
              4. 12.2.1.4.6.18.4  IET Receive Assembly Error (Offset = 3A140h - Port 0 or Offset = 3A340h - Port 1)
              5. 12.2.1.4.6.18.5  IET Receive Assembly OK (Offset = 3A144h - Port 0 or Offset = 3A344h - Port 1)
              6. 12.2.1.4.6.18.6  IET Receive SMD Error (Offset = 3A148h - Port 0 or Offset = 3A348h - Port 1)
              7. 12.2.1.4.6.18.7  IET Receive Merge Fragment Count (Offset = 3A14Ch - Port 0 or Offset = 3A34Ch - Port 1)
              8. 12.2.1.4.6.18.8  Tx-only Statistics Descriptions
                1. 12.2.1.4.6.18.8.1  Good Tx Frames (Offset = 3A034h - Port 0 or Offset = 3A234h - Port 1)
                2. 12.2.1.4.6.18.8.2  Broadcast Tx Frames (Offset = 3A038h - Port 0 or Offset = 3A238h - Port 1)
                3. 12.2.1.4.6.18.8.3  Multicast Tx Frames (Offset = 3A03Ch - Port 0 or Offset = 3A23Ch - Port 1)
                4. 12.2.1.4.6.18.8.4  Pause Tx Frames (Offset = 3A240h - Port 1)
                5. 12.2.1.4.6.18.8.5  Deferred Tx Frames (Offset = 3A244h - Port 1)
                6. 12.2.1.4.6.18.8.6  Collisions (Offset = 3A248h - Port 1)
                7. 12.2.1.4.6.18.8.7  Single Collision Tx Frames (Offset = 3A24Ch - Port 1)
                8. 12.2.1.4.6.18.8.8  Multiple Collision Tx Frames (Offset = 3A250h - Port 1)
                9. 12.2.1.4.6.18.8.9  Excessive Collisions (Offset = 3A254h - Port 1)
                10. 12.2.1.4.6.18.8.10 Late Collisions (Offset = 3A258h - Port 1)
                11. 12.2.1.4.6.18.8.11 Carrier Sense Errors (Offset = 3A260h - Port 1)
                12. 12.2.1.4.6.18.8.12 Tx Octets (Offset = 3A064h - Port 0 or Offset = 3A264h - Port 1 )
                13. 12.2.1.4.6.18.8.13 Transmit Priority 0-7 (Offset = 3A380h to 3A3A8h - Port 1)
                14. 12.2.1.4.6.18.8.14 Transmit Priority 0-7 Drop (Offset = 3A3C0h to 3A3E8 - Port 1)
                15. 12.2.1.4.6.18.8.15 Tx Memory Protect Errors (Offset = 3A17Ch - Port 0 or Offset = 3A37Ch - Port 1)
                16. 12.2.1.4.6.18.8.16 IET Transmit Merge Hold Count (Offset = 3A350h - Port 1)
                17. 12.2.1.4.6.18.8.17 IET Transmit Merge Fragment Count (Offset = 3A154h - Port 0 or Offset = 3A354h - Port 1)
              9. 12.2.1.4.6.18.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.1.4.6.18.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h - Port 0 or Offset = 3A268h - Port 1)
                2. 12.2.1.4.6.18.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch - Port 0 or Offset = 3A26Ch - Port 1)
                3. 12.2.1.4.6.18.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h - Port 0 or Offset = 3A270h - Port 1)
                4. 12.2.1.4.6.18.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h - Port 0 or Offset = 3A274h - Port 1)
                5. 12.2.1.4.6.18.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h - Port 0 or Offset = 3A278h - Port 1)
                6. 12.2.1.4.6.18.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch - Port 0 or Offset = 3A27Ch - Port 1)
                7. 12.2.1.4.6.18.9.7 Net Octets (Offset = 3A080h - Port 0 or Offset = 3A280h - Port 1)
              10. 12.2.1.4.6.18.10 2045
          7. 12.2.1.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.1.4.7.1  MCU_CPSW0 CPTS Integration
            2. 12.2.1.4.7.2  CPTS Architecture
            3. 12.2.1.4.7.3  CPTS Initialization
            4. 12.2.1.4.7.4  32-bit Time Stamp Value
            5. 12.2.1.4.7.5  64-bit Time Stamp Value
            6. 12.2.1.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.1.4.7.7  64-bit Timestamp PPM
            8. 12.2.1.4.7.8  Event FIFO
            9. 12.2.1.4.7.9  Timestamp Compare Output
              1. 12.2.1.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.1.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.1.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.1.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.1.4.7.10 Timestamp Sync Output
            11. 12.2.1.4.7.11 Timestamp GENFn Output
              1. 12.2.1.4.7.11.1 GENFn Nudge
              2. 12.2.1.4.7.11.2 GENFn PPM
            12. 12.2.1.4.7.12 Timestamp ESTFn
            13. 12.2.1.4.7.13 Time Sync Events
              1. 12.2.1.4.7.13.1 Time Stamp Push Event
              2. 12.2.1.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.1.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.1.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.1.4.7.13.5 Ethernet Port Events
                1. 12.2.1.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.1.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.1.4.7.13.5.3 2073
            14. 12.2.1.4.7.14 Timestamp Compare Event
              1. 12.2.1.4.7.14.1 32-Bit Mode
              2. 12.2.1.4.7.14.2 64-Bit Mode
            15. 12.2.1.4.7.15 Host Transmit Event
            16. 12.2.1.4.7.16 CPTS Interrupt Handling
          8. 12.2.1.4.8 CPPI Streaming Packet Interface
            1. 12.2.1.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_2G Egress)
            2. 12.2.1.4.8.2 Port 0 CPPI Receive Packet Streaming Interface (CPSW_2G Ingress)
            3. 12.2.1.4.8.3 CPPI Checksum Offload
              1. 12.2.1.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.1.4.8.3.1.1 IPV4 UDP
                2. 12.2.1.4.8.3.1.2 IPV4 TCP
                3. 12.2.1.4.8.3.1.3 IPV6 UDP
                4. 12.2.1.4.8.3.1.4 IPV6 TCP
            4. 12.2.1.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.1.4.8.5 Egress Packet Operations
          9. 12.2.1.4.9 MII Management Interface (MDIO)
            1. 12.2.1.4.9.1 MDIO Frame Formats
            2. 12.2.1.4.9.2 MDIO Functional Description
        5. 12.2.1.5 MCU_CPSW0 Programming Guide
          1. 12.2.1.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.1.5.2 CPSW Reset
          3. 12.2.1.5.3 MDIO Software Interface
            1. 12.2.1.5.3.1 Initializing the MDIO Module
            2. 12.2.1.5.3.2 Writing Data To a PHY Register
            3. 12.2.1.5.3.3 Reading Data From a PHY Register
        6. 12.2.1.6 MCU_CPSW0 Registers
          1. 12.2.1.6.1  MCU_CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.1.6.2  MCU_CPSW0_SGMII Registers
          3. 12.2.1.6.3  MCU_CPSW0_MDIO Registers
          4. 12.2.1.6.4  MCU_CPSW0_CPTS Registers
          5. 12.2.1.6.5  MCU_CPSW0_CONTROL Registers
          6. 12.2.1.6.6  MCU_CPSW0_CPINT Registers
          7. 12.2.1.6.7  MCU_CPSW0_RAM Registers
          8. 12.2.1.6.8  MCU_CPSW0_STAT0 Registers
          9. 12.2.1.6.9  MCU_CPSW0_STAT1 Registers
          10. 12.2.1.6.10 MCU_CPSW0_ALE Registers
          11. 12.2.1.6.11 MCU_CPSW0_ECC Registers
      2. 12.2.2 Gigabit Ethernet Switch (CPSW0)
        1. 12.2.2.1 CPSW0 Overview
          1. 12.2.2.1.1 CPSW0 Features
          2. 12.2.2.1.2 CPSW0 Not Supported Features
          3. 12.2.2.1.3 Terminology
        2. 12.2.2.2 CPSW0 Environment
          1. 12.2.2.2.1 CPSW0 RMII Interface
          2. 12.2.2.2.2 CPSW0 RGMII Interface
        3. 12.2.2.3 CPSW0 Integration
        4. 12.2.2.4 CPSW0 Functional Description
          1. 12.2.2.4.1 Functional Block Diagram
          2. 12.2.2.4.2 CPSW Ports
            1. 12.2.2.4.2.1 Interface Mode Selection
          3. 12.2.2.4.3 Clocking
            1. 12.2.2.4.3.1 Subsystem Clocking
            2. 12.2.2.4.3.2 Interface Clocking
              1. 12.2.2.4.3.2.1 RGMII Interface Clocking
              2. 12.2.2.4.3.2.2 RMII Interface Clocking
              3. 12.2.2.4.3.2.3 MDIO Clocking
          4. 12.2.2.4.4 Software IDLE
          5. 12.2.2.4.5 Interrupt Functionality
            1. 12.2.2.4.5.1 EVNT_PEND Interrupt
            2. 12.2.2.4.5.2 Statistics Interrupt (STAT_PEND0)
            3. 12.2.2.4.5.3 ECC DED Level Interrupt (ECC_DED_INT)
            4. 12.2.2.4.5.4 ECC SEC Level Interrupt (ECC_SEC_INT)
            5. 12.2.2.4.5.5 MDIO Interrupts
          6. 12.2.2.4.6 CPSW_5X
            1. 12.2.2.4.6.1  Address Lookup Engine (ALE)
              1. 12.2.2.4.6.1.1  Error Handling
              2. 12.2.2.4.6.1.2  Bypass Operations
              3. 12.2.2.4.6.1.3  OUI Deny or Accept
              4. 12.2.2.4.6.1.4  Statistics Counting
              5. 12.2.2.4.6.1.5  Automotive Security Features
              6. 12.2.2.4.6.1.6  CPSW Switching Solutions
                1. 12.2.2.4.6.1.6.1 Basics of 5-port Switch Type
              7. 12.2.2.4.6.1.7  VLAN Routing and OAM Operations
                1. 12.2.2.4.6.1.7.1 InterVLAN Routing
                2. 12.2.2.4.6.1.7.2 OAM Operations
              8. 12.2.2.4.6.1.8  Supervisory packets
              9. 12.2.2.4.6.1.9  Address Table Entry
                1. 12.2.2.4.6.1.9.1  Free Table Entry
                2. 12.2.2.4.6.1.9.2  Multicast Address Table Entry (Bit 40 == 0)
                3. 12.2.2.4.6.1.9.3  Multicast Address Table Entry (Bit 40 == 1)
                4. 12.2.2.4.6.1.9.4  VLAN Unicast Address Table Entry (Bit 40 == 0)
                5. 12.2.2.4.6.1.9.5  OUI Unicast Address Table Entry
                6. 12.2.2.4.6.1.9.6  VLAN/Unicast Address Table Entry (Bit 40 == 0)
                7. 12.2.2.4.6.1.9.7  VLAN/ Multicast Address Table Entry (Bit 40 == 1)
                8. 12.2.2.4.6.1.9.8  Inner VLAN Table Entry
                9. 12.2.2.4.6.1.9.9  Outer VLAN Table Entry
                10. 12.2.2.4.6.1.9.10 EtherType Table Entry
                11. 12.2.2.4.6.1.9.11 IPv4 Table Entry
                12. 12.2.2.4.6.1.9.12 IPv6 Table Entry High
                13. 12.2.2.4.6.1.9.13 IPv6 Table Entry Low
              10. 12.2.2.4.6.1.10 Multicast Address
                1. 12.2.2.4.6.1.10.1 Multicast Ranges
              11. 12.2.2.4.6.1.11 Supervisory Packets
              12. 12.2.2.4.6.1.12 Aging and Auto Aging
              13. 12.2.2.4.6.1.13 ALE Policing and Classification
                1. 12.2.2.4.6.1.13.1 ALE Policing
                2. 12.2.2.4.6.1.13.2 Classifier to Host Thread Mapping
                3. 12.2.2.4.6.1.13.3 ALE Classification
                  1. 2.2.4.6.1.13.3.1 Classifier to CPPI Transmit Flow ID Mapping
              14. 12.2.2.4.6.1.14 Mirroring
              15. 12.2.2.4.6.1.15 Trunking
              16. 12.2.2.4.6.1.16 DSCP
              17. 12.2.2.4.6.1.17 Packet Forwarding Processes
                1. 12.2.2.4.6.1.17.1 Ingress Filtering Process
                2. 12.2.2.4.6.1.17.2 VLAN_Aware Lookup Process
                3. 12.2.2.4.6.1.17.3 Egress Process
                4. 12.2.2.4.6.1.17.4 Learning/Updating/Touching Processes
                  1. 2.2.4.6.1.17.4.1 Learning Process
                  2. 2.2.4.6.1.17.4.2 Updating Process
                  3. 2.2.4.6.1.17.4.3 Touching Process
              18. 12.2.2.4.6.1.18 VLAN Aware Mode
              19. 12.2.2.4.6.1.19 VLAN Unaware Mode
            2. 12.2.2.4.6.2  Packet Priority Handling
              1. 12.2.2.4.6.2.1 Priority Mapping and Transmit VLAN Priority
            3. 12.2.2.4.6.3  CPPI Port Ingress
            4. 12.2.2.4.6.4  Packet CRC Handling
              1. 12.2.2.4.6.4.1 Transmit VLAN Processing
                1. 12.2.2.4.6.4.1.1 Untagged Packets (No VLAN or Priority Tag Header)
                2. 12.2.2.4.6.4.1.2 Priority Tagged Packets (VLAN VID == 0 && EN_VID0_MODE ==0h)
                3. 12.2.2.4.6.4.1.3 VLAN Tagged Packets (VLAN VID != 0 || (EN_VID0_MODE ==1h && VLAN VID ==0))
              2. 12.2.2.4.6.4.2 Ethernet Port Ingress Packet CRC
              3. 12.2.2.4.6.4.3 Ethernet Port Egress Packet CRC
              4. 12.2.2.4.6.4.4 CPPI Port Ingress Packet CRC
              5. 12.2.2.4.6.4.5 CPPI Port Egress Packet CRC
            5. 12.2.2.4.6.5  FIFO Memory Control
            6. 12.2.2.4.6.6  FIFO Transmit Queue Control
              1. 12.2.2.4.6.6.1 CPPI Port Receive Rate Limiting
              2. 12.2.2.4.6.6.2 Ethernet Port Transmit Rate Limiting
            7. 12.2.2.4.6.7  Intersperced Express Traffic (IET – P802.3br/D2.0)
              1. 12.2.2.4.6.7.1 IET Configuration
            8. 12.2.2.4.6.8  Enhanced Scheduled Traffic (EST – P802.1Qbv/D2.2)
              1. 12.2.2.4.6.8.1 Enhanced Scheduled Traffic Overview
              2. 12.2.2.4.6.8.2 Enhanced Scheduled Traffic Fetch RAM
              3. 12.2.2.4.6.8.3 Enhanced Scheduled Traffic Time Interval
              4. 12.2.2.4.6.8.4 Enhanced Scheduled Traffic Fetch Values
              5. 12.2.2.4.6.8.5 Enhanced Scheduled Traffic Packet Fill
              6. 12.2.2.4.6.8.6 Enhanced Scheduled Traffic Time Stamp
            9. 12.2.2.4.6.9  Audio Video Bridging
              1. 12.2.2.4.6.9.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
                1. 12.2.2.4.6.9.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
                  1. 2.2.4.6.9.1.1.1 Cross-timestamping and Presentation Timestamps
                2. 12.2.2.4.6.9.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
              2. 12.2.2.4.6.9.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
                1. 12.2.2.4.6.9.2.1 Configuring the Device for 802.1Qav Operation
            10. 12.2.2.4.6.10 Ethernet MAC Sliver
              1. 12.2.2.4.6.10.1  CRC Insertion
              2. 12.2.2.4.6.10.2  MTXER
              3. 12.2.2.4.6.10.3  Adaptive Performance Optimization (APO)
              4. 12.2.2.4.6.10.4  Inter-Packet-Gap Enforcement
              5. 12.2.2.4.6.10.5  Back Off
              6. 12.2.2.4.6.10.6  Programmable Transmit Inter-Packet Gap
              7. 12.2.2.4.6.10.7  Speed, Duplex and Pause Frame Support Negotiation
              8. 12.2.2.4.6.10.8  RMII Interface
                1. 12.2.2.4.6.10.8.1 Features
                2. 12.2.2.4.6.10.8.2 RMII Receive (RX)
                3. 12.2.2.4.6.10.8.3 RMII Transmit (TX)
              9. 12.2.2.4.6.10.9  RGMII Interface
                1. 12.2.2.4.6.10.9.1 Features
                2. 12.2.2.4.6.10.9.2 RGMII Receive (RX)
                3. 12.2.2.4.6.10.9.3 In-Band Mode of Operation
                4. 12.2.2.4.6.10.9.4 Forced Mode of Operation
                5. 12.2.2.4.6.10.9.5 RGMII Transmit (TX)
              10. 12.2.2.4.6.10.10 Frame Classification
              11. 12.2.2.4.6.10.11 Receive FIFO Architecture
            11. 12.2.2.4.6.11 Embedded Memories
            12. 12.2.2.4.6.12 Memory Error Detection and Correction
              1. 12.2.2.4.6.12.1 Packet Header ECC
              2. 12.2.2.4.6.12.2 Packet Protect CRC
              3. 12.2.2.4.6.12.3 Aggregator RAM Control
            13. 12.2.2.4.6.13 Ethernet Port Flow Control
              1. 12.2.2.4.6.13.1 Ethernet Receive Flow Control
                1. 12.2.2.4.6.13.1.1 Collision Based Receive Buffer Flow Control
                2. 12.2.2.4.6.13.1.2 IEEE 802.3X Based Receive Flow Control
              2. 12.2.2.4.6.13.2 Qbb (10/100/1G/10G) Receive Priority Based Flow Control (PFC)
              3. 12.2.2.4.6.13.3 Ethernet Transmit Flow Control
            14. 12.2.2.4.6.14 PFC Trigger Rules
              1. 12.2.2.4.6.14.1 Destination Based Rule
              2. 12.2.2.4.6.14.2 Sum of Outflows Rule
              3. 12.2.2.4.6.14.3 Sum of Blocks Per Port Rule
              4. 12.2.2.4.6.14.4 Sum of Blocks Total Rule
              5. 12.2.2.4.6.14.5 Top of Receive FIFO Rule
            15. 12.2.2.4.6.15 Energy Efficient Ethernet Support (802.3az)
            16. 12.2.2.4.6.16 Ethernet Switch Latency
            17. 12.2.2.4.6.17 MAC Emulation Control
            18. 12.2.2.4.6.18 MAC Command IDLE
            19. 12.2.2.4.6.19 CPSW Network Statistics
              1. 12.2.2.4.6.19.1  Rx-only Statistics Descriptions
                1. 12.2.2.4.6.19.1.1  Good Rx Frames (Offset = 3A000h)
                2. 12.2.2.4.6.19.1.2  Broadcast Rx Frames (Offset = 3A004h)
                3. 12.2.2.4.6.19.1.3  Multicast Rx Frames (Offset = 3A008h)
                4. 12.2.2.4.6.19.1.4  Pause Rx Frames (Offset = 3A00Ch)
                5. 12.2.2.4.6.19.1.5  Rx CRC Errors (Offset = 3A010h)
                6. 12.2.2.4.6.19.1.6  Rx Align/Code Errors (Offset = 3A014h)
                7. 12.2.2.4.6.19.1.7  Oversize Rx Frames (Offset = 3A018h)
                8. 12.2.2.4.6.19.1.8  Rx Jabbers (Offset = 3A01Ch)
                9. 12.2.2.4.6.19.1.9  Undersize (Short) Rx Frames (Offset = 3A020h)
                10. 12.2.2.4.6.19.1.10 Rx Fragments (Offset = 3A024h)
                11. 12.2.2.4.6.19.1.11 RX IPG Error
                12. 12.2.2.4.6.19.1.12 ALE Drop (Offset = 3A028h)
                13. 12.2.2.4.6.19.1.13 ALE Overrun Drop (Offset = 3A02Ch)
                14. 12.2.2.4.6.19.1.14 Rx Octets (Offset = 3A030h)
                15. 12.2.2.4.6.19.1.15 Rx Bottom of FIFO Drop (Offset = 3A084h)
                16. 12.2.2.4.6.19.1.16 Portmask Drop (Offset = 3A088h)
                17. 12.2.2.4.6.19.1.17 Rx Top of FIFO Drop (Offset = 3A08Ch)
                18. 12.2.2.4.6.19.1.18 ALE Rate Limit Drop (Offset = 3A090h)
                19. 12.2.2.4.6.19.1.19 ALE VLAN Ingress Check Drop (Offset = 3A094h)
                  1. 2.2.4.6.19.1.19.1  ALE DA=SA Drop (Offset = 3A098h)
                  2. 2.2.4.6.19.1.19.2  Block Address Drop (Offset = 3A09Ch)
                  3. 2.2.4.6.19.1.19.3  ALE Secure Drop (Offset = 3A0A0h)
                  4. 2.2.4.6.19.1.19.4  ALE Authentication Drop (Offset = 3A0A4h)
                  5. 2.2.4.6.19.1.19.5  ALE Unknown Unicast (Offset = 3A0A8h)
                  6. 2.2.4.6.19.1.19.6  ALE Unknown Unicast Bytecount (Offset = 3A0ACh)
                  7. 2.2.4.6.19.1.19.7  ALE Unknown Multicast (Offset = 3A0B0h)
                  8. 2.2.4.6.19.1.19.8  ALE Unknown Multicast Bytecount (Offset = 3A0B4h)
                  9. 2.2.4.6.19.1.19.9  ALE Unknown Broadcast (Offset = 3A0B8h)
                  10. 2.2.4.6.19.1.19.10 ALE Unknown Broadcast Bytecount (Offset = 3A0BCh)
                  11. 2.2.4.6.19.1.19.11 ALE Policer/Classifier Match (Offset = 3A0C0h)
              2. 12.2.2.4.6.19.2  ALE Policer Match Red (Offset = 3A0C4h)
              3. 12.2.2.4.6.19.3  ALE Policer Match Yellow (Offset = 3A0C8h)
              4. 12.2.2.4.6.19.4  IET Receive Assembly Error (Offset = 3A140h)
              5. 12.2.2.4.6.19.5  IET Receive Assembly OK (Offset = 3A144h)
              6. 12.2.2.4.6.19.6  IET Receive SMD Error (Offset = 3A148h)
              7. 12.2.2.4.6.19.7  IET Receive Merge Fragment Count (Offset = 3A14Ch)
              8. 12.2.2.4.6.19.8  Tx-only Statistics Descriptions
                1. 12.2.2.4.6.19.8.1  Good Tx Frames (Offset = 3A034h)
                2. 12.2.2.4.6.19.8.2  Broadcast Tx Frames (Offset = 3A038h)
                3. 12.2.2.4.6.19.8.3  Multicast Tx Frames (Offset = 3A03Ch)
                4. 12.2.2.4.6.19.8.4  Pause Tx Frames (Offset = 3A040h)
                5. 12.2.2.4.6.19.8.5  Deferred Tx Frames (Offset = 3A044h)
                6. 12.2.2.4.6.19.8.6  Collisions (Offset = 3A048h)
                7. 12.2.2.4.6.19.8.7  Single Collision Tx Frames (Offset = 3A04Ch)
                8. 12.2.2.4.6.19.8.8  Multiple Collision Tx Frames (Offset = 3A050h)
                9. 12.2.2.4.6.19.8.9  Excessive Collisions (Offset = 3A054h)
                10. 12.2.2.4.6.19.8.10 Late Collisions (Offset = 3A058h)
                11. 12.2.2.4.6.19.8.11 Carrier Sense Errors (Offset = 3A060h)
                12. 12.2.2.4.6.19.8.12 Tx Octets (Offset = 3A064h)
                13. 12.2.2.4.6.19.8.13 Transmit Priority 0-7 (Offset = 3A180h to 3A1A8h)
                14. 12.2.2.4.6.19.8.14 Transmit Priority 0-7 Drop (Offset = 3A1C0h to 3A1E8h)
                15. 12.2.2.4.6.19.8.15 Tx Memory Protect Errors (Offset = 3A17Ch)
                16. 12.2.2.4.6.19.8.16 IET Transmit Merge Fragment Count (Offset = 3A14Ch)
                17. 12.2.2.4.6.19.8.17 IET Transmit Merge Hold Count (Offset = 3A150h)
              9. 12.2.2.4.6.19.9  Rx- and Tx (Shared) Statistics Descriptions
                1. 12.2.2.4.6.19.9.1 Rx + Tx 64 Octet Frames (Offset = 3A068h)
                2. 12.2.2.4.6.19.9.2 Rx + Tx 65–127 Octet Frames (Offset = 3A06Ch)
                3. 12.2.2.4.6.19.9.3 Rx + Tx 128–255 Octet Frames (Offset = 3A070h)
                4. 12.2.2.4.6.19.9.4 Rx + Tx 256–511 Octet Frames (Offset = 3A074h)
                5. 12.2.2.4.6.19.9.5 Rx + Tx 512–1023 Octet Frames (Offset = 3A078h)
                6. 12.2.2.4.6.19.9.6 Rx + Tx 1024_Up Octet Frames (Offset = 3A07Ch)
                7. 12.2.2.4.6.19.9.7 Net Octets (Offset = 3A080h)
              10. 12.2.2.4.6.19.10 2324
          7. 12.2.2.4.7 Common Platform Time Sync (CPTS)
            1. 12.2.2.4.7.1  CPSW0 CPTS Integration
            2. 12.2.2.4.7.2  CPTS Architecture
            3. 12.2.2.4.7.3  CPTS Initialization
            4. 12.2.2.4.7.4  32-bit Time Stamp Value
            5. 12.2.2.4.7.5  64-bit Time Stamp Value
            6. 12.2.2.4.7.6  64-Bit Timestamp Nudge
            7. 12.2.2.4.7.7  64-bit Timestamp PPM
            8. 12.2.2.4.7.8  Event FIFO
            9. 12.2.2.4.7.9  Timestamp Compare Output
              1. 12.2.2.4.7.9.1 Non-Toggle Mode: 32-bit
              2. 12.2.2.4.7.9.2 Non-Toggle Mode: 64-bit
              3. 12.2.2.4.7.9.3 Toggle Mode: 32-bit
              4. 12.2.2.4.7.9.4 Toggle Mode: 64-bit
            10. 12.2.2.4.7.10 Timestamp Sync Output
            11. 12.2.2.4.7.11 Timestamp GENFn Output
              1. 12.2.2.4.7.11.1 GENFn Nudge
              2. 12.2.2.4.7.11.2 GENFn PPM
            12. 12.2.2.4.7.12 Timestamp ESTFn
            13. 12.2.2.4.7.13 Time Sync Events
              1. 12.2.2.4.7.13.1 Time Stamp Push Event
              2. 12.2.2.4.7.13.2 Time Stamp Counter Rollover Event (32-bit mode only)
              3. 12.2.2.4.7.13.3 Time Stamp Counter Half-rollover Event (32-bit mode only)
              4. 12.2.2.4.7.13.4 Hardware Time Stamp Push Event
              5. 12.2.2.4.7.13.5 Ethernet Port Events
                1. 12.2.2.4.7.13.5.1 Ethernet Port Receive Event
                2. 12.2.2.4.7.13.5.2 Ethernet Port Transmit Event
                3. 12.2.2.4.7.13.5.3 2352
            14. 12.2.2.4.7.14 Timestamp Compare Event
              1. 12.2.2.4.7.14.1 32-Bit Mode
              2. 12.2.2.4.7.14.2 64-Bit Mode
            15. 12.2.2.4.7.15 Host Transmit Event
            16. 12.2.2.4.7.16 CPTS Interrupt Handling
          8. 12.2.2.4.8 CPPI Streaming Packet Interface
            1. 12.2.2.4.8.1 Port 0 CPPI Transmit Packet Streaming Interface (CPSW_5X Egress)
            2. 12.2.2.4.8.2 CPPI Receive Packet Streaming Interface (CPSW Ingress)
            3. 12.2.2.4.8.3 CPPI Checksum Offload
              1. 12.2.2.4.8.3.1 CPPI Transmit Checksum Offload
                1. 12.2.2.4.8.3.1.1 IPV4 UDP
                2. 12.2.2.4.8.3.1.2 IPV4 TCP
                3. 12.2.2.4.8.3.1.3 IPV6 UDP
                4. 12.2.2.4.8.3.1.4 IPV6 TCP
            4. 12.2.2.4.8.4 CPPI Receive Checksum Offload
            5. 12.2.2.4.8.5 Egress Packet Operations
          9. 12.2.2.4.9 MII Management Interface (MDIO)
            1. 12.2.2.4.9.1 MDIO Frame Formats
            2. 12.2.2.4.9.2 MDIO Functional Description
        5. 12.2.2.5 CPSW0 Programming Guide
          1. 12.2.2.5.1 Initialization and Configuration of CPSW Subsystem
          2. 12.2.2.5.2 Ethernet MAC Reset or XGMII/GMII Mode Change Configuration
          3. 12.2.2.5.3 MDIO Software Interface
            1. 12.2.2.5.3.1 Initializing the MDIO Module
            2. 12.2.2.5.3.2 Writing Data To a PHY Register
            3. 12.2.2.5.3.3 Reading Data From a PHY Register
        6. 12.2.2.6 CPSW0 Registers
          1. 12.2.2.6.1  CPSW0_NUSS Subsystem (SS) Registers
          2. 12.2.2.6.2  CPSW0_SGMII Registers
          3. 12.2.2.6.3  CPSW0_MDIO Registers
          4. 12.2.2.6.4  CPSW0_CPTS Registers
          5. 12.2.2.6.5  CPSW0_CONTROL Registers
          6. 12.2.2.6.6  CPSW0_CPINT Registers
          7. 12.2.2.6.7  CPSW0_RAM Registers
          8. 12.2.2.6.8  CPSW0_STAT Registers
          9. 12.2.2.6.9  CPSW0_ALE Registers
          10. 12.2.2.6.10 CPSW0_PCSR Registers
          11. 12.2.2.6.11 CPSW0_ECC Registers
      3. 12.2.3 Peripheral Component Interconnect Express (PCIe) Subsystem
        1. 12.2.3.1 PCIe Subsystem Overview
          1. 12.2.3.1.1 PCIe Subsystem Features
          2. 12.2.3.1.2 PCIe Subsystem Not Supported Features
        2. 12.2.3.2 PCIe Subsystem Environment
        3. 12.2.3.3 PCIe Subsystem Integration
        4. 12.2.3.4 PCIe Subsystem Functional Description
          1. 12.2.3.4.1  PCIe Subsystem Block Diagram
            1. 12.2.3.4.1.1 PCIe Core Module
            2. 12.2.3.4.1.2 PCIe PHY Interface
            3. 12.2.3.4.1.3 CBA Infrastructure
            4. 12.2.3.4.1.4 VBUSM to AXI Bridges
            5. 12.2.3.4.1.5 AXI to VBUSM Bridges
            6. 12.2.3.4.1.6 VBUSP to APB Bridge
            7. 12.2.3.4.1.7 Custom Logic
          2. 12.2.3.4.2  PCIe Subsystem Reset Schemes
            1. 12.2.3.4.2.1 PCIe Conventional Reset
            2. 12.2.3.4.2.2 PCIe Function Level Reset
            3. 12.2.3.4.2.3 PCIe Reset Isolation
              1. 12.2.3.4.2.3.1 Root Port Reset with Device Not Reset
              2. 12.2.3.4.2.3.2 Device Reset with Root Port Not Reset
              3. 12.2.3.4.2.3.3 End Point Device Reset with Root Port Not Reset
              4. 12.2.3.4.2.3.4 Device Reset with End Point Device Not Reset
            4. 12.2.3.4.2.4 PCIe Reset Limitations
            5. 12.2.3.4.2.5 PCIe Reset Requirements
          3. 12.2.3.4.3  PCIe Subsystem Power Management
            1. 12.2.3.4.3.1 CBA Power Management
          4. 12.2.3.4.4  PCIe Subsystem Interrupts
            1. 12.2.3.4.4.1 Interrupts Aggregation
            2. 12.2.3.4.4.2 Interrupt Generation in EP Mode
              1. 12.2.3.4.4.2.1 Legacy Interrupt Generation in EP Mode
              2. 12.2.3.4.4.2.2 MSI and MSI-X Interrupt Generation
            3. 12.2.3.4.4.3 Interrupt Reception in EP Mode
              1. 12.2.3.4.4.3.1 PCIe Core Downstream Interrupts
              2. 12.2.3.4.4.3.2 PCIe Core Function Level Reset Interrupts
              3. 12.2.3.4.4.3.3 PCIe Core Power Management Event Interrupts
              4. 12.2.3.4.4.3.4 PCIe Core Hot Reset Request Interrupt
              5. 12.2.3.4.4.3.5 PTM Valid Interrupt
            4. 12.2.3.4.4.4 Interrupt Generation in RP Mode
            5. 12.2.3.4.4.5 Interrupt Reception in RP Mode
              1. 12.2.3.4.4.5.1 PCIe Legacy Interrupt Reception in RP Mode
              2. 12.2.3.4.4.5.2 MSI/MSI-X Interrupt Reception in RP Mode
              3. 12.2.3.4.4.5.3 Advanced Error Reporting Interrupt
            6. 12.2.3.4.4.6 Common Interrupt Reception in RP and EP Modes
              1. 12.2.3.4.4.6.1 PCIe Local Interrupt
              2. 12.2.3.4.4.6.2 PHY Interrupt
              3. 12.2.3.4.4.6.3 Link down Interrupt
              4. 12.2.3.4.4.6.4 Transaction Error Interrupts
              5. 12.2.3.4.4.6.5 Power Management Event Interrupt
              6. 12.2.3.4.4.6.6 Active Internal Diagnostics Interrupts
            7. 12.2.3.4.4.7 ECC Aggregator Interrupts
            8. 12.2.3.4.4.8 CPTS Interrupt
          5. 12.2.3.4.5  PCIe Subsystem DMA Support
            1. 12.2.3.4.5.1 PCIe DMA Support in RP Mode
            2. 12.2.3.4.5.2 PCIe DMA Support in EP Mode
          6. 12.2.3.4.6  PCIe Subsystem Transactions
            1. 12.2.3.4.6.1 PCIe Supported Transactions
            2. 12.2.3.4.6.2 PCIe Transaction Limitations
          7. 12.2.3.4.7  PCIe Subsystem Address Translation
            1. 12.2.3.4.7.1 PCIe Inbound Address Translation
              1. 12.2.3.4.7.1.1 Root Port Inbound PCIe to AXI Address Translation
              2. 12.2.3.4.7.1.2 End Point Inbound PCIe to AXI Address Translation
            2. 12.2.3.4.7.2 PCIe Outbound Address Translation
              1. 12.2.3.4.7.2.1 PCIe Outbound Address Translation Bypass
          8. 12.2.3.4.8  PCIe Subsystem Virtualization Support
            1. 12.2.3.4.8.1 End Point SR-IOV Support
            2. 12.2.3.4.8.2 Root Port ATS Support
            3. 12.2.3.4.8.3 VirtID Mapping
          9. 12.2.3.4.9  PCIe Subsystem Quality-of-Service (QoS)
          10. 12.2.3.4.10 PCIe Subsystem Precision Time Measurement (PTM)
          11. 12.2.3.4.11 PCIe Subsystem Loopback
            1. 12.2.3.4.11.1 PCIe PIPE Loopback
              1. 12.2.3.4.11.1.1 PIPE Loopback Master Mode
              2. 12.2.3.4.11.1.2 PIPE Loopback Slave Mode
          12. 12.2.3.4.12 PCIe Subsystem Error Handling
            1. 12.2.3.4.12.1 PCIe AXI to/from VBUSM Bus Error Mapping
          13. 12.2.3.4.13 PCIe Subsystem Internal Diagnostics Features
            1. 12.2.3.4.13.1 PCIe Parity
            2. 12.2.3.4.13.2 ECC Aggregators
            3. 12.2.3.4.13.3 RAM ECC Inversion
          14. 12.2.3.4.14 LTSSM State Encoding
        5. 12.2.3.5 PCIe Subsystem Registers
          1. 12.2.3.5.1  PCIE_CORE_EP_PF Registers
          2. 12.2.3.5.2  PCIE_CORE_EP_VF Registers
          3. 12.2.3.5.3  PCIE_CORE_RP Registers
          4. 12.2.3.5.4  PCIE_CORE_LM Registers
          5. 12.2.3.5.5  PCIE_CORE_AXI Registers
          6. 12.2.3.5.6  PCIE_INTD Registers
          7. 12.2.3.5.7  PCIE_VMAP Registers
          8. 12.2.3.5.8  PCIE_CPTS Registers
          9. 12.2.3.5.9  PCIE_USER_CFG Registers
          10. 12.2.3.5.10 PCIE_ECC_AGGR0 Registers
          11. 12.2.3.5.11 PCIE_ECC_AGGR1 Registers
          12. 12.2.3.5.12 PCIE_DAT0 Registers
          13. 12.2.3.5.13 PCIE_DAT1 Registers
      4. 12.2.4 Universal Serial Bus (USB) Subsystem
        1. 12.2.4.1 USB Overview
          1. 12.2.4.1.1 USB Features
          2. 12.2.4.1.2 USB Not Supported Features
          3. 12.2.4.1.3 USB Terminology
        2. 12.2.4.2 USB Environment
        3. 12.2.4.3 USB Integration
        4. 12.2.4.4 USB Functional Description
          1. 12.2.4.4.1 USB Type-C Connector Support
          2. 12.2.4.4.2 USB Controller Reset
          3. 12.2.4.4.3 Overcurrent Detection
          4. 12.2.4.4.4 Top-Level Initialization Sequence
        5. 12.2.4.5 USB Registers
          1. 12.2.4.5.1 USB3P0SS_MMR_MMRVBP_USBSS_CMN Registers
          2. 12.2.4.5.2 USB_ECC_AGGR_CFG Registers
          3. 12.2.4.5.3 USB_RAMS_INJ_CFG Registers
      5. 12.2.5 Serializer/Deserializer (SerDes)
        1. 12.2.5.1 SerDes Overview
          1. 12.2.5.1.1 SerDes Features
          2. 12.2.5.1.2 Industry Standards Compatibility
        2. 12.2.5.2 SerDes Environment
          1. 12.2.5.2.1 SerDes I/Os
        3. 12.2.5.3 SerDes Integration
          1. 12.2.5.3.1 WIZ Settings
            1. 12.2.5.3.1.1 Interface Selection
            2. 12.2.5.3.1.2 Reference Clock Distribution
            3. 12.2.5.3.1.3 Internal Reference Clock Selection
        4. 12.2.5.4 SerDes Functional Description
          1. 12.2.5.4.1 SerDes Block Diagram
          2. 12.2.5.4.2 SerDes Programming Guide
    3. 12.3 Memory Interfaces
      1. 12.3.1 Flash Subsystem (FSS)
        1. 12.3.1.1 FSS Overview
          1. 12.3.1.1.1 FSS Features
          2. 12.3.1.1.2 FSS Not Supported Features
        2. 12.3.1.2 FSS Environment
          1. 12.3.1.2.1 FSS Typical Application
        3. 12.3.1.3 FSS Integration
          1. 12.3.1.3.1 FSS Integration in MCU Domain
        4. 12.3.1.4 FSS Functional Description
          1. 12.3.1.4.1 FSS Block Diagram
          2. 12.3.1.4.2 FSS ECC Support
            1. 12.3.1.4.2.1 FSS ECC Calculation
          3. 12.3.1.4.3 FSS Modes of Operation
          4. 12.3.1.4.4 FSS Regions
            1. 12.3.1.4.4.1 FSS Regions Boot Size Configuration
          5. 12.3.1.4.5 FSS Memory Regions
        5. 12.3.1.5 FSS Programming Guide
          1. 12.3.1.5.1 FSS Initialization Sequence
          2. 12.3.1.5.2 FSS Real-Time Operation
          3. 12.3.1.5.3 FSS Power Up/Down Sequence
        6. 12.3.1.6 FSS Registers
      2. 12.3.2 Octal Serial Peripheral Interface (OSPI)
        1. 12.3.2.1 OSPI Overview
          1. 12.3.2.1.1 OSPI Features
          2. 12.3.2.1.2 OSPI Not Supported Features
        2. 12.3.2.2 OSPI Environment
        3. 12.3.2.3 OSPI Integration
          1. 12.3.2.3.1 OSPI Integration in MCU Domain
        4. 12.3.2.4 OSPI Functional Description
          1. 12.3.2.4.1  OSPI Block Diagram
            1. 12.3.2.4.1.1 Data Target Interface
            2. 12.3.2.4.1.2 Configuration Target Interface
            3. 12.3.2.4.1.3 OSPI Clock Domains
          2. 12.3.2.4.2  OSPI Modes
            1. 12.3.2.4.2.1 Read Data Capture
              1. 12.3.2.4.2.1.1 Mechanisms of Data Capturing
              2. 12.3.2.4.2.1.2 Data Capturing Mechanism Using Taps
              3. 12.3.2.4.2.1.3 Data Capturing Mechanism Using PHY Module
            2. 12.3.2.4.2.2 External Pull Down on DQS
          3. 12.3.2.4.3  OSPI Power Management
          4. 12.3.2.4.4  Auto HW Polling
          5. 12.3.2.4.5  Flash Reset
          6. 12.3.2.4.6  OSPI Memory Regions
          7. 12.3.2.4.7  OSPI Interrupt Requests
          8. 12.3.2.4.8  OSPI Data Interface
            1. 12.3.2.4.8.1 Data Interface Address Remapping
            2. 12.3.2.4.8.2 Write Protection
            3. 12.3.2.4.8.3 Access Forwarding
          9. 12.3.2.4.9  OSPI Direct Access Controller (DAC)
          10. 12.3.2.4.10 OSPI Indirect Access Controller (INDAC)
            1. 12.3.2.4.10.1 Indirect Read Controller
              1. 12.3.2.4.10.1.1 Indirect Read Transfer Process
            2. 12.3.2.4.10.2 Indirect Write Controller
              1. 12.3.2.4.10.2.1 Indirect Write Transfer Process
            3. 12.3.2.4.10.3 Indirect Access Queuing
            4. 12.3.2.4.10.4 Consecutive Writes and Reads Using Indirect Transfers
            5. 12.3.2.4.10.5 Accessing the SRAM
          11. 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG)
            1. 12.3.2.4.11.1 Servicing a STIG Request
            2. 12.3.2.4.11.2 2576
          12. 12.3.2.4.12 OSPI Arbitration Between Direct / Indirect Access Controller and STIG
          13. 12.3.2.4.13 OSPI Command Translation
          14. 12.3.2.4.14 Selecting the Flash Instruction Type
          15. 12.3.2.4.15 OSPI Data Integrity
          16. 12.3.2.4.16 OSPI PHY Module
            1. 12.3.2.4.16.1 PHY Pipeline Mode
            2. 12.3.2.4.16.2 Read Data Capturing by the PHY Module
        5. 12.3.2.5 OSPI Programming Guide
          1. 12.3.2.5.1 Configuring the OSPI Controller for Use After Reset
          2. 12.3.2.5.2 Configuring the OSPI Controller for Optimal Use
          3. 12.3.2.5.3 Using the Flash Command Control Register (STIG Operation)
          4. 12.3.2.5.4 Using SPI Legacy Mode
          5. 12.3.2.5.5 Entering XIP Mode from POR
          6. 12.3.2.5.6 Entering XIP Mode Otherwise
          7. 12.3.2.5.7 Exiting XIP Mode
        6. 12.3.2.6 OSPI Registers
      3. 12.3.3 HyperBus Interface
        1. 12.3.3.1 HyperBus Overview
          1. 12.3.3.1.1 HyperBus Features
          2. 12.3.3.1.2 HyperBus Not Supported Features
        2. 12.3.3.2 HyperBus Environment
        3. 12.3.3.3 HyperBus Integration
          1. 12.3.3.3.1 HyperBus Integration in MCU Domain
        4. 12.3.3.4 HyperBus Functional Description
          1. 12.3.3.4.1 HyperBus Interrupts
          2. 12.3.3.4.2 HyperBus ECC Support
            1. 12.3.3.4.2.1 ECC Aggregator
          3. 12.3.3.4.3 HyperBus Internal FIFOs
          4. 12.3.3.4.4 HyperBus Data Regions
          5. 12.3.3.4.5 HyperBus True Continuous Read (TCR) Mode
        5. 12.3.3.5 HyperBus Programming Guide
          1. 12.3.3.5.1 HyperBus Initialization Sequence
            1. 12.3.3.5.1.1 HyperFlash Access
            2. 12.3.3.5.1.2 HyperRAM Access
          2. 12.3.3.5.2 HyperBus Real-time Operating Requirements
          3. 12.3.3.5.3 HyperBus Power Up/Down Sequence
        6. 12.3.3.6 HyperBus Registers
      4. 12.3.4 General-Purpose Memory Controller (GPMC)
        1. 12.3.4.1 GPMC Overview
          1. 12.3.4.1.1 GPMC Features
          2. 12.3.4.1.2 GPMC Not Supported Features
        2. 12.3.4.2 GPMC Environment
          1. 12.3.4.2.1 GPMC Modes
          2. 12.3.4.2.2 GPMC I/O Signals
        3. 12.3.4.3 GPMC Integration
          1. 12.3.4.3.1 GPMC Integration in MAIN Domain
        4. 12.3.4.4 GPMC Functional Description
          1. 12.3.4.4.1  GPMC Block Diagram
          2. 12.3.4.4.2  GPMC Clock Configuration
          3. 12.3.4.4.3  GPMC Power Management
          4. 12.3.4.4.4  GPMC Interrupt Requests
          5. 12.3.4.4.5  GPMC Interconnect Port Interface
          6. 12.3.4.4.6  GPMC Address and Data Bus
            1. 12.3.4.4.6.1 GPMC I/O Configuration Setting
          7. 12.3.4.4.7  GPMC Address Decoder and Chip-Select Configuration
            1. 12.3.4.4.7.1 Chip-Select Base Address and Region Size
            2. 12.3.4.4.7.2 Access Protocol
              1. 12.3.4.4.7.2.1 Supported Devices
              2. 12.3.4.4.7.2.2 Access Size Adaptation and Device Width
              3. 12.3.4.4.7.2.3 Address/Data-Multiplexing Interface
            3. 12.3.4.4.7.3 External Signals
              1. 12.3.4.4.7.3.1 WAIT Pin Monitoring Control
                1. 12.3.4.4.7.3.1.1 Wait Monitoring During Asynchronous Read Access
                2. 12.3.4.4.7.3.1.2 Wait Monitoring During Asynchronous Write Access
                3. 12.3.4.4.7.3.1.3 Wait Monitoring During Synchronous Read Access
                4. 12.3.4.4.7.3.1.4 Wait Monitoring During Synchronous Write Access
                5. 12.3.4.4.7.3.1.5 Wait With NAND Device
                6. 12.3.4.4.7.3.1.6 Idle Cycle Control Between Successive Accesses
                  1. 3.4.4.7.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                  2. 3.4.4.7.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                  3. 3.4.4.7.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
                7. 12.3.4.4.7.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
              2. 12.3.4.4.7.3.2 DIR Pin
              3. 12.3.4.4.7.3.3 Reset
              4. 12.3.4.4.7.3.4 Write Protect Signal (nWP)
              5. 12.3.4.4.7.3.5 Byte Enable (nBE1/nBE0)
            4. 12.3.4.4.7.4 Error Handling
          8. 12.3.4.4.8  GPMC Timing Setting
            1. 12.3.4.4.8.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
            2. 12.3.4.4.8.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
            3. 12.3.4.4.8.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
            4. 12.3.4.4.8.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
            5. 12.3.4.4.8.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
            6. 12.3.4.4.8.6  GPMC_CLKOUT
            7. 12.3.4.4.8.7  GPMC Output Clock and Control Signals Setup and Hold
            8. 12.3.4.4.8.8  Access Time (RDACCESSTIME / WRACCESSTIME)
              1. 12.3.4.4.8.8.1 Access Time on Read Access
              2. 12.3.4.4.8.8.2 Access Time on Write Access
            9. 12.3.4.4.8.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
              1. 12.3.4.4.8.9.1 Page Burst Access Time on Read Access
              2. 12.3.4.4.8.9.2 Page Burst Access Time on Write Access
            10. 12.3.4.4.8.10 Bus Keeping Support
          9. 12.3.4.4.9  GPMC NOR Access Description
            1. 12.3.4.4.9.1 Asynchronous Access Description
              1. 12.3.4.4.9.1.1 Access on Address/Data Multiplexed Devices
                1. 12.3.4.4.9.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
                2. 12.3.4.4.9.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
                3. 12.3.4.4.9.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
              2. 12.3.4.4.9.1.2 Access on Address/Address/Data-Multiplexed Devices
                1. 12.3.4.4.9.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
                2. 12.3.4.4.9.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
                3. 12.3.4.4.9.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
            2. 12.3.4.4.9.2 Synchronous Access Description
              1. 12.3.4.4.9.2.1 Synchronous Single Read
              2. 12.3.4.4.9.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
              3. 12.3.4.4.9.2.3 Synchronous Single Write
              4. 12.3.4.4.9.2.4 Synchronous Multiple (Burst) Write
            3. 12.3.4.4.9.3 Asynchronous and Synchronous Accesses in non-multiplexed Mode
              1. 12.3.4.4.9.3.1 Asynchronous Single-Read Operation on non-multiplexed Device
              2. 12.3.4.4.9.3.2 Asynchronous Single-Write Operation on non-multiplexed Device
              3. 12.3.4.4.9.3.3 Asynchronous Multiple (Page Mode) Read Operation on non-multiplexed Device
              4. 12.3.4.4.9.3.4 Synchronous Operations on a non-multiplexed Device
            4. 12.3.4.4.9.4 Page and Burst Support
            5. 12.3.4.4.9.5 System Burst vs External Device Burst Support
          10. 12.3.4.4.10 GPMC pSRAM Access Specificities
          11. 12.3.4.4.11 GPMC NAND Access Description
            1. 12.3.4.4.11.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
              1. 12.3.4.4.11.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
              2. 12.3.4.4.11.1.2 NAND Device Command and Address Phase Control
              3. 12.3.4.4.11.1.3 Command Latch Cycle
              4. 12.3.4.4.11.1.4 Address Latch Cycle
              5. 12.3.4.4.11.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
              6. 12.3.4.4.11.1.6 NAND Device General Chip-Select Timing Control Requirement
              7. 12.3.4.4.11.1.7 Read and Write Access Size Adaptation
                1. 12.3.4.4.11.1.7.1 8-Bit-Wide NAND Device
                2. 12.3.4.4.11.1.7.2 16-Bit-Wide NAND Device
            2. 12.3.4.4.11.2 NAND Device-Ready Pin
              1. 12.3.4.4.11.2.1 Ready Pin Monitored by Software Polling
              2. 12.3.4.4.11.2.2 Ready Pin Monitored by Hardware Interrupt
            3. 12.3.4.4.11.3 ECC Calculator
              1. 12.3.4.4.11.3.1 Hamming Code
                1. 12.3.4.4.11.3.1.1 ECC Result Register and ECC Computation Accumulation Size
                2. 12.3.4.4.11.3.1.2 ECC Enabling
                3. 12.3.4.4.11.3.1.3 ECC Computation
                4. 12.3.4.4.11.3.1.4 ECC Comparison and Correction
                5. 12.3.4.4.11.3.1.5 ECC Calculation Based on 8-Bit Word
                6. 12.3.4.4.11.3.1.6 ECC Calculation Based on 16-Bit Word
              2. 12.3.4.4.11.3.2 BCH Code
                1. 12.3.4.4.11.3.2.1 Requirements
                2. 12.3.4.4.11.3.2.2 Memory Mapping of BCH Codeword
                  1. 3.4.4.11.3.2.2.1 Memory Mapping of Data Message
                  2. 3.4.4.11.3.2.2.2 Memory-Mapping of the ECC
                  3. 3.4.4.11.3.2.2.3 Wrapping Modes
                    1. 4.4.11.3.2.2.3.1  Manual Mode (0x0)
                    2. 4.4.11.3.2.2.3.2  Mode 0x1
                    3. 4.4.11.3.2.2.3.3  Mode 0xA (10)
                    4. 4.4.11.3.2.2.3.4  Mode 0x2
                    5. 4.4.11.3.2.2.3.5  Mode 0x3
                    6. 4.4.11.3.2.2.3.6  Mode 0x7
                    7. 4.4.11.3.2.2.3.7  Mode 0x8
                    8. 4.4.11.3.2.2.3.8  Mode 0x4
                    9. 4.4.11.3.2.2.3.9  Mode 0x9
                    10. 4.4.11.3.2.2.3.10 Mode 0x5
                    11. 4.4.11.3.2.2.3.11 Mode 0xB (11)
                    12. 4.4.11.3.2.2.3.12 Mode 0x6
                3. 12.3.4.4.11.3.2.3 Supported NAND Page Mappings and ECC Schemes
                  1. 3.4.4.11.3.2.3.1 Per-Sector Spare Mappings
                  2. 3.4.4.11.3.2.3.2 Pooled Spare Mapping
                  3. 3.4.4.11.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
            4. 12.3.4.4.11.4 Prefetch and Write-Posting Engine
              1. 12.3.4.4.11.4.1 General Facts About the Engine Configuration
              2. 12.3.4.4.11.4.2 Prefetch Mode
              3. 12.3.4.4.11.4.3 FIFO Control in Prefetch Mode
              4. 12.3.4.4.11.4.4 Write-Posting Mode
              5. 12.3.4.4.11.4.5 FIFO Control in Write-Posting Mode
              6. 12.3.4.4.11.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
              7. 12.3.4.4.11.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
          12. 12.3.4.4.12 GPMC Use Cases and Tips
            1. 12.3.4.4.12.1 How to Set GPMC Timing Parameters for Typical Accesses
              1. 12.3.4.4.12.1.1 External Memory Attached to the GPMC Module
              2. 12.3.4.4.12.1.2 Typical GPMC Setup
                1. 12.3.4.4.12.1.2.1 GPMC Configuration for Synchronous Burst Read Access
                2. 12.3.4.4.12.1.2.2 GPMC Configuration for Asynchronous Read Access
                3. 12.3.4.4.12.1.2.3 GPMC Configuration for Asynchronous Single Write Access
            2. 12.3.4.4.12.2 How to Choose a Suitable Memory to Use With the GPMC
              1. 12.3.4.4.12.2.1 Supported Memories or Devices
                1. 12.3.4.4.12.2.1.1 Memory Pin Multiplexing
                2. 12.3.4.4.12.2.1.2 NAND Interface Protocol
                3. 12.3.4.4.12.2.1.3 NOR Interface Protocol
                4. 12.3.4.4.12.2.1.4 Other Technologies
        5. 12.3.4.5 GPMC Basic Programming Model
          1. 12.3.4.5.1 GPMC High-Level Programming Model Overview
          2. 12.3.4.5.2 GPMC Initialization
          3. 12.3.4.5.3 GPMC Configuration in NOR Mode
          4. 12.3.4.5.4 GPMC Configuration in NAND Mode
          5. 12.3.4.5.5 Set Memory Access
          6. 12.3.4.5.6 GPMC Timing Parameters
            1. 12.3.4.5.6.1 GPMC Timing Parameters Formulas
              1. 12.3.4.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
              2. 12.3.4.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
              3. 12.3.4.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
        6. 12.3.4.6 GPMC Registers
      5. 12.3.5 Error Location Module (ELM)
        1. 12.3.5.1 ELM Overview
          1. 12.3.5.1.1 ELM Features
          2. 12.3.5.1.2 ELM Not Supported Features
        2. 12.3.5.2 ELM Integration
          1. 12.3.5.2.1 ELM Integration in MAIN Domain
        3. 12.3.5.3 ELM Functional Description
          1. 12.3.5.3.1 ELM Software Reset
          2. 12.3.5.3.2 ELM Power Management
          3. 12.3.5.3.3 ELM Interrupt Requests
          4. 12.3.5.3.4 ELM Processing Initialization
          5. 12.3.5.3.5 ELM Processing Sequence
          6. 12.3.5.3.6 ELM Processing Completion
        4. 12.3.5.4 ELM Basic Programming Model
          1. 12.3.5.4.1 ELM Low-Level Programming Model
            1. 12.3.5.4.1.1 Processing Initialization
            2. 12.3.5.4.1.2 Read Results
            3. 12.3.5.4.1.3 2786
          2. 12.3.5.4.2 Use Case: ELM Used in Continuous Mode
          3. 12.3.5.4.3 Use Case: ELM Used in Page Mode
        5. 12.3.5.5 ELM Registers
      6. 12.3.6 Multi-Media Card Secure Digital (MMCSD) Interface
        1. 12.3.6.1 MMCSD Overview
          1. 12.3.6.1.1 MMCSD Features
          2. 12.3.6.1.2 MMCSD Not Supported Features
        2. 12.3.6.2 MMCSD Environment
          1. 12.3.6.2.1 Protocol and Data Format
            1. 12.3.6.2.1.1 Protocol
            2. 12.3.6.2.1.2 Data Format
              1. 12.3.6.2.1.2.1 Coding Scheme for Command Token
              2. 12.3.6.2.1.2.2 Coding Scheme for Response Token
              3. 12.3.6.2.1.2.3 Coding Scheme for Data Token
        3. 12.3.6.3 MMCSD Integration
          1. 12.3.6.3.1 MMCSD Integration in MAIN Domain
        4. 12.3.6.4 MMCSD Functional Description
          1. 12.3.6.4.1 Block Diagram
          2. 12.3.6.4.2 Memory Regions
          3. 12.3.6.4.3 Interrupt Requests
          4. 12.3.6.4.4 ECC Support
            1. 12.3.6.4.4.1 ECC Aggregator
          5. 12.3.6.4.5 Advanced DMA
          6. 12.3.6.4.6 eMMC PHY BIST
            1. 12.3.6.4.6.1 BIST Overview
            2. 12.3.6.4.6.2 BIST Modes
              1. 12.3.6.4.6.2.1 DS Mode
              2. 12.3.6.4.6.2.2 HS Mode with TXDLY using DLL
              3. 12.3.6.4.6.2.3 HS Mode with TXDLY using Delay Chain
              4. 12.3.6.4.6.2.4 DDR50 Mode with TXDLY using DLL
              5. 12.3.6.4.6.2.5 DDR50 Mode with TXDLY using Delay Chain
              6. 12.3.6.4.6.2.6 HS200 Mode with TX/RXDLY using DLL
              7. 12.3.6.4.6.2.7 HS200 Mode with TX/RXDLY using Delay Chain
              8. 12.3.6.4.6.2.8 HS400 Mode
            3. 12.3.6.4.6.3 BIST Functionality
            4. 12.3.6.4.6.4 Signal Interface
            5. 12.3.6.4.6.5 Programming Flow
              1. 12.3.6.4.6.5.1 DS Mode
                1. 12.3.6.4.6.5.1.1 Configuration
                2. 12.3.6.4.6.5.1.2 BIST Programming
              2. 12.3.6.4.6.5.2 HS Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.2.1 Configuration
                2. 12.3.6.4.6.5.2.2 BIST Programming
              3. 12.3.6.4.6.5.3 HS Mode with DLL
                1. 12.3.6.4.6.5.3.1 Configuration
                2. 12.3.6.4.6.5.3.2 BIST Programming
              4. 12.3.6.4.6.5.4 DDR52 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.4.1 Configuration
                2. 12.3.6.4.6.5.4.2 BIST Programming
              5. 12.3.6.4.6.5.5 DDR52 Mode with DLL
                1. 12.3.6.4.6.5.5.1 Configuration
                2. 12.3.6.4.6.5.5.2 BIST Programming
              6. 12.3.6.4.6.5.6 HS200 Mode with DLY_CHAIN
                1. 12.3.6.4.6.5.6.1 Configuration
                2. 12.3.6.4.6.5.6.2 BIST Programming
              7. 12.3.6.4.6.5.7 HS200 Mode with DLL
                1. 12.3.6.4.6.5.7.1 Configuration
                2. 12.3.6.4.6.5.7.2 BIST Programming
              8. 12.3.6.4.6.5.8 HS400 Mode with DLL
                1. 12.3.6.4.6.5.8.1 Configuration
                2. 12.3.6.4.6.5.8.2 BIST Programming
            6. 12.3.6.4.6.6 HS200 BIST Result Check Procedure
        5. 12.3.6.5 MMCSD Programming Guide
          1. 12.3.6.5.1 Sequences
            1. 12.3.6.5.1.1  SD Card Detection
            2. 12.3.6.5.1.2  SD Clock Control
              1. 12.3.6.5.1.2.1 Internal Clock Setup Sequence
              2. 12.3.6.5.1.2.2 SD Clock Supply and Stop Sequence
              3. 12.3.6.5.1.2.3 SD Clock Frequency Change Sequence
            3. 12.3.6.5.1.3  SD Bus Power Control
            4. 12.3.6.5.1.4  Changing Bus Width
            5. 12.3.6.5.1.5  Timeout Setting on DAT Line
            6. 12.3.6.5.1.6  Card Initialization and Identification (for SD I/F)
              1. 12.3.6.5.1.6.1 Signal Voltage Switch Procedure (for UHS-I)
            7. 12.3.6.5.1.7  SD Transaction Generation
              1. 12.3.6.5.1.7.1 Transaction Control without Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.1.1 The Sequence to Issue a SD Command
                2. 12.3.6.5.1.7.1.2 The Sequence to Finalize a Command
                3. 12.3.6.5.1.7.1.3 2865
              2. 12.3.6.5.1.7.2 Transaction Control with Data Transfer Using DAT Line
                1. 12.3.6.5.1.7.2.1 Not using DMA
                2. 12.3.6.5.1.7.2.2 Using SDMA
                3. 12.3.6.5.1.7.2.3 Using ADMA
            8. 12.3.6.5.1.8  Abort Transaction
              1. 12.3.6.5.1.8.1 Asynchronous Abort
              2. 12.3.6.5.1.8.2 Synchronous Abort
            9. 12.3.6.5.1.9  Changing Bus Speed Mode
            10. 12.3.6.5.1.10 Error Recovery
              1. 12.3.6.5.1.10.1 Error Interrupt Recovery
              2. 12.3.6.5.1.10.2 Auto CMD12 Error Recovery
            11. 12.3.6.5.1.11 Wakeup Control (Optional)
            12. 12.3.6.5.1.12 Suspend/Resume (Optional, Not Supported from Version 4.00)
              1. 12.3.6.5.1.12.1 Suspend Sequence
              2. 12.3.6.5.1.12.2 Resume Sequence
              3. 12.3.6.5.1.12.3 Stop At Block Gap/Continue Timing for Read Transaction
              4. 12.3.6.5.1.12.4 Stop At Block Gap/Continue Timing for Write Transaction
          2. 12.3.6.5.2 Driver Flow Sequence
            1. 12.3.6.5.2.1 Host Controller Setup and Card Detection
              1. 12.3.6.5.2.1.1 Host Controller Setup Sequence
              2. 12.3.6.5.2.1.2 Card Interface Detection Sequence
            2. 12.3.6.5.2.2 Boot Operation
              1. 12.3.6.5.2.2.1 Normal Boot Operation: (For Legacy eMMC 5.0)
              2. 12.3.6.5.2.2.2 Alternate Boot Operation (For Legacy eMMC 5.0):
              3. 12.3.6.5.2.2.3 Boot Code Chunk Read Operation (For Legacy eMMC 5.0):
            3. 12.3.6.5.2.3 Retuning procedure (For Legacy Interface)
              1. 12.3.6.5.2.3.1 Sampling Clock Tuning
              2. 12.3.6.5.2.3.2 Tuning Modes
              3. 12.3.6.5.2.3.3 Re-Tuning Mode 2
            4. 12.3.6.5.2.4 Command Queuing Driver Flow Sequence
              1. 12.3.6.5.2.4.1 Command Queuing Initialization Sequence
              2. 12.3.6.5.2.4.2 Task Issuance Sequence
              3. 12.3.6.5.2.4.3 Task Execution and Completion Sequence
              4. 12.3.6.5.2.4.4 Task Discard and Clear Sequence
              5. 12.3.6.5.2.4.5 Error Detect and Recovery when CQ is enabled
        6. 12.3.6.6 MMCSD Registers
          1. 12.3.6.6.1 MMCSD0 Subsystem Registers
          2. 12.3.6.6.2 MMCSD0 RX RAM ECC Aggregator Registers
          3. 12.3.6.6.3 MMCSD0 TX RAM ECC Aggregator Registers
          4. 12.3.6.6.4 MMCSD0 Host Controller Registers
          5. 12.3.6.6.5 MMCSD1 Subsystem Registers
          6. 12.3.6.6.6 MMCSD1 RX RAM ECC Aggregator Registers
          7. 12.3.6.6.7 MMCSD1 TX RAM ECC Aggregator Registers
          8. 12.3.6.6.8 MMCSD1 Host Controller Registers
    4. 12.4 Industrial and Control Interfaces
      1. 12.4.1 Enhanced Capture (ECAP) Module
        1. 12.4.1.1 ECAP Overview
          1. 12.4.1.1.1 ECAP Features
        2. 12.4.1.2 ECAP Environment
          1. 12.4.1.2.1 ECAP I/O Interface
        3. 12.4.1.3 ECAP Integration
          1. 12.4.1.3.1 Daisy-Chain Connectivity between ECAP Modules
        4. 12.4.1.4 ECAP Functional Description
          1. 12.4.1.4.1 Capture and APWM Operating Modes
            1. 12.4.1.4.1.1 ECAP Capture Mode Description
              1. 12.4.1.4.1.1.1 ECAP Event Prescaler
              2. 12.4.1.4.1.1.2 ECAP Edge Polarity Select and Qualifier
              3. 12.4.1.4.1.1.3 ECAP Continuous/One-Shot Control
              4. 12.4.1.4.1.1.4 ECAP 32-Bit Counter and Phase Control
              5. 12.4.1.4.1.1.5 CAP1-CAP4 Registers
              6. 12.4.1.4.1.1.6 ECAP Interrupt Control
              7. 12.4.1.4.1.1.7 ECAP Shadow Load and Lockout Control
            2. 12.4.1.4.1.2 ECAP APWM Mode Operation
          2. 12.4.1.4.2 Summary of ECAP Functional Registers
        5. 12.4.1.5 ECAP Use Cases
          1. 12.4.1.5.1 Absolute Time-Stamp Operation Rising Edge Trigger Example
            1. 12.4.1.5.1.1 Code Snippet for CAP Mode Absolute Time, Rising Edge Trigger
          2. 12.4.1.5.2 Absolute Time-Stamp Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.2.1 Code Snippet for CAP Mode Absolute Time, Rising and Falling Edge Trigger
          3. 12.4.1.5.3 Time Difference (Delta) Operation Rising Edge Trigger Example
            1. 12.4.1.5.3.1 Code Snippet for CAP Mode Delta Time, Rising Edge Trigger
          4. 12.4.1.5.4 Time Difference (Delta) Operation Rising and Falling Edge Trigger Example
            1. 12.4.1.5.4.1 Code Snippet for CAP Mode Delta Time, Rising and Falling Edge Triggers
          5. 12.4.1.5.5 Application of the APWM Mode
            1. 12.4.1.5.5.1 Simple PWM Generation (Independent Channel/s) Example
              1. 12.4.1.5.5.1.1 Code Snippet for APWM Mode
            2. 12.4.1.5.5.2 Multichannel PWM Generation with Synchronization Example
              1. 12.4.1.5.5.2.1 Code Snippet for Multichannel PWM Generation with Synchronization
            3. 12.4.1.5.5.3 Multichannel PWM Generation with Phase Control Example
              1. 12.4.1.5.5.3.1 Code Snippet for Multichannel PWM Generation with Phase Control
        6. 12.4.1.6 ECAP Registers
      2. 12.4.2 Enhanced Pulse Width Modulation (EPWM) Module
        1. 12.4.2.1 EPWM Overview
          1. 12.4.2.1.1 EPWM Features
          2. 12.4.2.1.2 EPWM Not Supported Features
          3. 12.4.2.1.3 2951
        2. 12.4.2.2 EPWM Environment
          1. 12.4.2.2.1 EPWM I/O Interface
        3. 12.4.2.3 EPWM Integration
          1. 12.4.2.3.1 Device Specific EPWM Features
          2. 12.4.2.3.2 Daisy-Chain Connectivity between EPWM Modules
          3. 12.4.2.3.3 ADC start of conversion signals (PWM_SOCA and PWM_SOCB)
          4. 12.4.2.3.4 EPWM Modules Time Base Clock Gating
        4. 12.4.2.4 EPWM Functional Description
          1. 12.4.2.4.1  EPWM Submodule Features
            1. 12.4.2.4.1.1 Constant Definitions Used in the EPWM Code Examples
          2. 12.4.2.4.2  EPWM Time-Base (TB) Submodule
            1. 12.4.2.4.2.1 Overview
            2. 12.4.2.4.2.2 2964
            3. 12.4.2.4.2.3 Controlling and Monitoring the EPWM Time-Base Submodule
            4. 12.4.2.4.2.4 Calculating PWM Period and Frequency
              1. 12.4.2.4.2.4.1 EPWM Time-Base Period Shadow Register
              2. 12.4.2.4.2.4.2 EPWM Time-Base Counter Synchronization
            5. 12.4.2.4.2.5 Phase Locking the Time-Base Clocks of Multiple EPWM Modules
            6. 12.4.2.4.2.6 EPWM Time-Base Counter Modes and Timing Waveforms
          3. 12.4.2.4.3  EPWM Counter-Compare (CC) Submodule
            1. 12.4.2.4.3.1 Overview
            2. 12.4.2.4.3.2 Controlling and Monitoring the EPWM Counter-Compare Submodule
            3. 12.4.2.4.3.3 Operational Highlights for the EPWM Counter-Compare Submodule
            4. 12.4.2.4.3.4 EPWM Counter-Compare Submodule Timing Waveforms
          4. 12.4.2.4.4  EPWM Action-Qualifier (AQ) Submodule
            1. 12.4.2.4.4.1 Overview
            2. 12.4.2.4.4.2 Controlling and Monitoring the EPWM Action-Qualifier Submodule
            3. 12.4.2.4.4.3 EPWM Action-Qualifier Event Priority
            4. 12.4.2.4.4.4 Waveforms for Common EPWM Configurations
          5. 12.4.2.4.5  EPWM Dead-Band Generator (DB) Submodule
            1. 12.4.2.4.5.1 Overview
            2. 12.4.2.4.5.2 Controlling and Monitoring the EPWM Dead-Band Submodule
            3. 12.4.2.4.5.3 Operational Highlights for the EPWM Dead-Band Generator Submodule
          6. 12.4.2.4.6  EPWM-Chopper (PC) Submodule
            1. 12.4.2.4.6.1 Overview
            2. 12.4.2.4.6.2 2987
            3. 12.4.2.4.6.3 Controlling the EPWM-Chopper Submodule
            4. 12.4.2.4.6.4 Operational Highlights for the EPWM-Chopper Submodule
            5. 12.4.2.4.6.5 EPWM-Chopper Waveforms
              1. 12.4.2.4.6.5.1 EPWM-Chopper One-Shot Pulse
              2. 12.4.2.4.6.5.2 EPWM-Chopper Duty Cycle Control
          7. 12.4.2.4.7  EPWM Trip-Zone (TZ) Submodule
            1. 12.4.2.4.7.1 Overview
            2. 12.4.2.4.7.2 Controlling and Monitoring the EPWM Trip-Zone Submodule
            3. 12.4.2.4.7.3 Operational Highlights for the EPWM Trip-Zone Submodule
            4. 12.4.2.4.7.4 Generating EPWM Trip-Event Interrupts
          8. 12.4.2.4.8  EPWM Event-Trigger (ET) Submodule
            1. 12.4.2.4.8.1 Overview
            2. 12.4.2.4.8.2 Controlling and Monitoring the EPWM Event-Trigger Submodule
            3. 12.4.2.4.8.3 Operational Overview of the EPWM Event-Trigger Submodule
            4. 12.4.2.4.8.4 3002
          9. 12.4.2.4.9  EPWM High Resolution (HRPWM) Submodule
            1. 12.4.2.4.9.1 Overview
            2. 12.4.2.4.9.2 Architecture of the High-Resolution PWM Submodule
            3. 12.4.2.4.9.3 Controlling and Monitoring the High-Resolution PWM Submodule
            4. 12.4.2.4.9.4 Configuring the High-Resolution PWM Submodule
            5. 12.4.2.4.9.5 Operational Highlights for the High-Resolution PWM Submodule
              1. 12.4.2.4.9.5.1 HRPWM Edge Positioning
              2. 12.4.2.4.9.5.2 HRPWM Scaling Considerations
              3. 12.4.2.4.9.5.3 HRPWM Duty Cycle Range Limitation
          10. 12.4.2.4.10 EPWM / HRPWM Functional Register Groups
          11. 12.4.2.4.11 Proper EPWM Interrupt Initialization Procedure
        5. 12.4.2.5 EPWM Registers
      3. 12.4.3 Enhanced Quadrature Encoder Pulse (EQEP) Module
        1. 12.4.3.1 EQEP Overview
          1. 12.4.3.1.1 EQEP Features
          2. 12.4.3.1.2 EQEP Not Supported Features
        2. 12.4.3.2 EQEP Environment
          1. 12.4.3.2.1 EQEP I/O Interface
        3. 12.4.3.3 EQEP Integration
          1. 12.4.3.3.1 Device Specific EQEP Features
        4. 12.4.3.4 EQEP Functional Description
          1. 12.4.3.4.1 EQEP Inputs
          2. 12.4.3.4.2 EQEP Quadrature Decoder Unit (QDU)
            1. 12.4.3.4.2.1 EQEP Position Counter Input Modes
              1. 12.4.3.4.2.1.1 Quadrature Count Mode
              2. 12.4.3.4.2.1.2 EQEP Direction-count Mode
              3. 12.4.3.4.2.1.3 EQEP Up-Count Mode
              4. 12.4.3.4.2.1.4 EQEP Down-Count Mode
            2. 12.4.3.4.2.2 EQEP Input Polarity Selection
            3. 12.4.3.4.2.3 EQEP Position-Compare Sync Output
          3. 12.4.3.4.3 EQEP Position Counter and Control Unit (PCCU)
            1. 12.4.3.4.3.1 EQEP Position Counter Operating Modes
              1. 12.4.3.4.3.1.1 EQEP Position Counter Reset on Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM] = 0b00)
              2. 12.4.3.4.3.1.2 EQEP Position Counter Reset on Maximum Position (EQEP_QDEC_QEP_CTL[29-28] PCRM=0b01)
              3. 12.4.3.4.3.1.3 Position Counter Reset on the First Index Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b10)
              4. 12.4.3.4.3.1.4 Position Counter Reset on Unit Time out Event (EQEP_QDEC_QEP_CTL[29-28] PCRM = 0b11)
            2. 12.4.3.4.3.2 EQEP Position Counter Latch
              1. 12.4.3.4.3.2.1 Index Event Latch
              2. 12.4.3.4.3.2.2 EQEP Strobe Event Latch
            3. 12.4.3.4.3.3 EQEP Position Counter Initialization
            4. 12.4.3.4.3.4 EQEP Position-Compare Unit
          4. 12.4.3.4.4 EQEP Edge Capture Unit
          5. 12.4.3.4.5 EQEP Watchdog
          6. 12.4.3.4.6 Unit Timer Base
          7. 12.4.3.4.7 EQEP Interrupt Structure
          8. 12.4.3.4.8 Summary of EQEP Functional Registers
        5. 12.4.3.5 EQEP Registers
      4. 12.4.4 Controller Area Network (MCAN)
        1. 12.4.4.1 MCAN Overview
          1. 12.4.4.1.1 MCAN Features
          2. 12.4.4.1.2 MCAN Not Supported Features
        2. 12.4.4.2 MCAN Environment
          1. 12.4.4.2.1 CAN Network Basics
        3. 12.4.4.3 MCAN Integration
          1. 12.4.4.3.1 MCAN Integration in MCU Domain
          2. 12.4.4.3.2 MCAN Integration in MAIN Domain
        4. 12.4.4.4 MCAN Functional Description
          1. 12.4.4.4.1  Module Clocking Requirements
          2. 12.4.4.4.2  Interrupt and DMA Requests
            1. 12.4.4.4.2.1 Interrupt Requests
            2. 12.4.4.4.2.2 DMA Requests
            3. 12.4.4.4.2.3 3064
          3. 12.4.4.4.3  Operating Modes
            1. 12.4.4.4.3.1 Software Initialization
            2. 12.4.4.4.3.2 Normal Operation
            3. 12.4.4.4.3.3 CAN FD Operation
            4. 12.4.4.4.3.4 Transmitter Delay Compensation
              1. 12.4.4.4.3.4.1 Description
              2. 12.4.4.4.3.4.2 Transmitter Delay Compensation Measurement
            5. 12.4.4.4.3.5 Restricted Operation Mode
            6. 12.4.4.4.3.6 Bus Monitoring Mode
            7. 12.4.4.4.3.7 Disabled Automatic Retransmission (DAR) Mode
              1. 12.4.4.4.3.7.1 Frame Transmission in DAR Mode
            8. 12.4.4.4.3.8 Power Down (Sleep Mode)
              1. 12.4.4.4.3.8.1 External Clock Stop Mode
              2. 12.4.4.4.3.8.2 Suspend Mode
              3. 12.4.4.4.3.8.3 Wakeup request
            9. 12.4.4.4.3.9 Test Modes
              1. 12.4.4.4.3.9.1 Internal Loopback Mode
          4. 12.4.4.4.4  Timestamp Generation
            1. 12.4.4.4.4.1 External Timestamp Counter
          5. 12.4.4.4.5  Timeout Counter
          6. 12.4.4.4.6  ECC Support
            1. 12.4.4.4.6.1 ECC Wrapper
            2. 12.4.4.4.6.2 ECC Aggregator
          7. 12.4.4.4.7  Rx Handling
            1. 12.4.4.4.7.1 Acceptance Filtering
              1. 12.4.4.4.7.1.1 Range Filter
              2. 12.4.4.4.7.1.2 Filter for specific IDs
              3. 12.4.4.4.7.1.3 Classic Bit Mask Filter
              4. 12.4.4.4.7.1.4 Standard Message ID Filtering
              5. 12.4.4.4.7.1.5 Extended Message ID Filtering
            2. 12.4.4.4.7.2 Rx FIFOs
              1. 12.4.4.4.7.2.1 Rx FIFO Blocking Mode
              2. 12.4.4.4.7.2.2 Rx FIFO Overwrite Mode
            3. 12.4.4.4.7.3 Dedicated Rx Buffers
              1. 12.4.4.4.7.3.1 Rx Buffer Handling
            4. 12.4.4.4.7.4 Debug on CAN Support
          8. 12.4.4.4.8  Tx Handling
            1. 12.4.4.4.8.1 Transmit Pause
            2. 12.4.4.4.8.2 Dedicated Tx Buffers
            3. 12.4.4.4.8.3 Tx FIFO
            4. 12.4.4.4.8.4 Tx Queue
            5. 12.4.4.4.8.5 Mixed Dedicated Tx Buffers/Tx FIFO
            6. 12.4.4.4.8.6 Mixed Dedicated Tx Buffers/Tx Queue
            7. 12.4.4.4.8.7 Transmit Cancellation
            8. 12.4.4.4.8.8 Tx Event Handling
          9. 12.4.4.4.9  FIFO Acknowledge Handling
          10. 12.4.4.4.10 Message RAM
            1. 12.4.4.4.10.1 Message RAM Configuration
            2. 12.4.4.4.10.2 Rx Buffer and FIFO Element
            3. 12.4.4.4.10.3 Tx Buffer Element
            4. 12.4.4.4.10.4 Tx Event FIFO Element
            5. 12.4.4.4.10.5 Standard Message ID Filter Element
            6. 12.4.4.4.10.6 Extended Message ID Filter Element
        5. 12.4.4.5 MCAN Registers
          1. 12.4.4.5.1 MCAN Subsystem Registers
          2. 12.4.4.5.2 MCAN Core Registers
          3. 12.4.4.5.3 MCAN ECC Aggregator Registers
    5. 12.5 Audio Interfaces
      1. 12.5.1 Audio Tracking Logic (ATL)
        1. 12.5.1.1 ATL Overview
          1. 12.5.1.1.1 ATL Features Overview
          2. 12.5.1.1.2 ATL Not Supported Features
    6. 12.6 Timer Modules
      1. 12.6.1 Global Timebase Counter (GTC)
        1. 12.6.1.1 GTC Overview
          1. 12.6.1.1.1 GTC Features
          2. 12.6.1.1.2 GTC Not Supported Features
        2. 12.6.1.2 GTC Integration
        3. 12.6.1.3 GTC Functional Description
          1. 12.6.1.3.1 GTC Block Diagram
          2. 12.6.1.3.2 GTC Counter
          3. 12.6.1.3.3 GTC Gray Encoder
          4. 12.6.1.3.4 GTC Push Event Generation
          5. 12.6.1.3.5 GTC Register Partitioning
        4. 12.6.1.4 GTC Registers
          1. 12.6.1.4.1 GTC0_GTC_CFG0 Registers
          2. 12.6.1.4.2 GTC0_GTC_CFG1 Registers
          3. 12.6.1.4.3 GTC0_GTC_CFG2 Registers
          4. 12.6.1.4.4 GTC0_GTC_CFG3 Registers
      2. 12.6.2 Windowed Watchdog Timer (WWDT)
        1. 12.6.2.1 RTI Overview
          1. 12.6.2.1.1 RTI Features
          2. 12.6.2.1.2 RTI Not Supported Features
        2. 12.6.2.2 RTI Integration
          1. 12.6.2.2.1 RTI Integration in MCU Domain
          2. 12.6.2.2.2 RTI Integration in MAIN Domain
        3. 12.6.2.3 RTI Functional Description
          1. 12.6.2.3.1 RTI Counter Operation
          2. 12.6.2.3.2 RTI Digital Watchdog
          3. 12.6.2.3.3 RTI Digital Windowed Watchdog
          4. 12.6.2.3.4 RTI Low Power Mode Operation
          5. 12.6.2.3.5 RTI Debug Mode Behavior
        4. 12.6.2.4 RTI Registers
      3. 12.6.3 Timers
        1. 12.6.3.1 Timers Overview
          1. 12.6.3.1.1 Timers Features
          2. 12.6.3.1.2 Timers Not Supported Features
        2. 12.6.3.2 Timers Environment
          1. 12.6.3.2.1 Timer External System Interface
        3. 12.6.3.3 Timers Integration
          1. 12.6.3.3.1 Timers Integration in MCU Domain
          2. 12.6.3.3.2 Timers Integration in MAIN Domain
        4. 12.6.3.4 Timers Functional Description
          1. 12.6.3.4.1  Timer Block Diagram
          2. 12.6.3.4.2  Timer Power Management
            1. 12.6.3.4.2.1 Wake-Up Capability
          3. 12.6.3.4.3  Timer Software Reset
          4. 12.6.3.4.4  Timer Interrupts
          5. 12.6.3.4.5  Timer Mode Functionality
            1. 12.6.3.4.5.1 1-ms Tick Generation
          6. 12.6.3.4.6  Timer Capture Mode Functionality
          7. 12.6.3.4.7  Timer Compare Mode Functionality
          8. 12.6.3.4.8  Timer Prescaler Functionality
          9. 12.6.3.4.9  Timer Pulse-Width Modulation
          10. 12.6.3.4.10 Timer Counting Rate
          11. 12.6.3.4.11 Timer Under Emulation
          12. 12.6.3.4.12 Accessing Timer Registers
            1. 12.6.3.4.12.1 Writing to Timer Registers
              1. 12.6.3.4.12.1.1 Write Posting Synchronization Mode
              2. 12.6.3.4.12.1.2 Write Nonposting Synchronization Mode
            2. 12.6.3.4.12.2 Reading From Timer Counter Registers
              1. 12.6.3.4.12.2.1 Read Posted
              2. 12.6.3.4.12.2.2 Read Non-Posted
          13. 12.6.3.4.13 Timer Posted Mode Selection
        5. 12.6.3.5 Timers Low-Level Programming Models
          1. 12.6.3.5.1 Timer Global Initialization
            1. 12.6.3.5.1.1 Global Initialization of Surrounding Modules
            2. 12.6.3.5.1.2 Timer Module Global Initialization
              1. 12.6.3.5.1.2.1 Main Sequence – Timer Module Global Initialization
          2. 12.6.3.5.2 Timer Operational Mode Configuration
            1. 12.6.3.5.2.1 Timer Mode
              1. 12.6.3.5.2.1.1 Main Sequence – Timer Mode Configuration
            2. 12.6.3.5.2.2 Timer Compare Mode
              1. 12.6.3.5.2.2.1 Main Sequence – Timer Compare Mode Configuration
            3. 12.6.3.5.2.3 Timer Capture Mode
              1. 12.6.3.5.2.3.1 Main Sequence – Timer Capture Mode Configuration
              2. 12.6.3.5.2.3.2 Subsequence – Initialize Capture Mode
              3. 12.6.3.5.2.3.3 Subsequence – Detect Event
            4. 12.6.3.5.2.4 Timer PWM Mode
              1. 12.6.3.5.2.4.1 Main Sequence – Timer PWM Mode Configuration
        6. 12.6.3.6 Timers Registers
    7. 12.7 Internal Diagnostics Modules
      1. 12.7.1 Dual Clock Comparator (DCC)
        1. 12.7.1.1 DCC Overview
          1. 12.7.1.1.1 DCC Features
          2. 12.7.1.1.2 DCC Not Supported Features
        2. 12.7.1.2 DCC Integration
          1. 12.7.1.2.1 DCC Integration in MCU Domain
          2. 12.7.1.2.2 DCC Integration in MAIN Domain
        3. 12.7.1.3 DCC Functional Description
          1. 12.7.1.3.1 DCC Counter Operation
          2. 12.7.1.3.2 DCC Low Power Mode Operation
          3. 12.7.1.3.3 DCC Suspend Mode Behavior
          4. 12.7.1.3.4 DCC Single-Shot Mode
          5. 12.7.1.3.5 DCC Continuous mode
            1. 12.7.1.3.5.1 DCC Continue on Error
            2. 12.7.1.3.5.2 DCC Error Count
          6. 12.7.1.3.6 DCC Control and count hand-off across clock domains
          7. 12.7.1.3.7 DCC Error Trajectory record
            1. 12.7.1.3.7.1 DCC FIFO capturing for Errors
            2. 12.7.1.3.7.2 DCC FIFO in continuous capture mode
            3. 12.7.1.3.7.3 DCC FIFO Details
            4. 12.7.1.3.7.4 DCC FIFO Debug mode behavior
          8. 12.7.1.3.8 DCC Count read registers
        4. 12.7.1.4 DCC Registers
      2. 12.7.2 Error Signaling Module (ESM)
        1. 12.7.2.1 ESM Overview
          1. 12.7.2.1.1 ESM Features
        2. 12.7.2.2 ESM Environment
        3. 12.7.2.3 ESM Integration
          1. 12.7.2.3.1 ESM Integration in WKUP Domain
          2. 12.7.2.3.2 ESM Integration in MCU Domain
          3. 12.7.2.3.3 ESM Integration in MAIN Domain
        4. 12.7.2.4 ESM Functional Description
          1. 12.7.2.4.1 ESM Interrupt Requests
            1. 12.7.2.4.1.1 ESM Configuration Error Interrupt
            2. 12.7.2.4.1.2 ESM Low Priority Error Interrupt
              1. 12.7.2.4.1.2.1 ESM Low Priority Error Level Event
              2. 12.7.2.4.1.2.2 ESM Low Priority Error Pulse Event
            3. 12.7.2.4.1.3 ESM High Priority Error Interrupt
              1. 12.7.2.4.1.3.1 ESM High Priority Error Level Event
              2. 12.7.2.4.1.3.2 ESM High Priority Error Pulse Event
          2. 12.7.2.4.2 ESM Error Event Inputs
          3. 12.7.2.4.3 ESM Error Pin Output
          4. 12.7.2.4.4 ESM Minimum Time Interval
          5. 12.7.2.4.5 ESM Protection for Registers
          6. 12.7.2.4.6 ESM Clock Stop
        5. 12.7.2.5 ESM Registers
      3. 12.7.3 Memory Cyclic Redundancy Check (MCRC) Controller
        1. 12.7.3.1 MCRC Overview
          1. 12.7.3.1.1 MCRC Features
          2. 12.7.3.1.2 MCRC Not Supported Features
        2. 12.7.3.2 MCRC Integration
        3. 12.7.3.3 MCRC Functional Description
          1. 12.7.3.3.1  MCRC Block Diagram
          2. 12.7.3.3.2  MCRC General Operation
          3. 12.7.3.3.3  MCRC Modes of Operation
            1. 12.7.3.3.3.1 AUTO Mode
            2. 12.7.3.3.3.2 Semi-CPU Mode
            3. 12.7.3.3.3.3 Full-CPU Mode
          4. 12.7.3.3.4  PSA Signature Register
          5. 12.7.3.3.5  PSA Sector Signature Register
          6. 12.7.3.3.6  CRC Value Register
          7. 12.7.3.3.7  Raw Data Register
          8. 12.7.3.3.8  Example DMA Controller Setup
            1. 12.7.3.3.8.1 AUTO Mode Using Hardware Timer Trigger
            2. 12.7.3.3.8.2 AUTO Mode Using Software Trigger
            3. 12.7.3.3.8.3 Semi-CPU Mode Using Hardware Timer Trigger
          9. 12.7.3.3.9  Pattern Count Register
          10. 12.7.3.3.10 Sector Count Register/Current Sector Register
          11. 12.7.3.3.11 Interrupts
            1. 12.7.3.3.11.1 Compression Complete Interrupt
            2. 12.7.3.3.11.2 CRC Fail Interrupt
            3. 12.7.3.3.11.3 Overrun Interrupt
            4. 12.7.3.3.11.4 Underrun Interrupt
            5. 12.7.3.3.11.5 Timeout Interrupt
            6. 12.7.3.3.11.6 Interrupt Offset Register
            7. 12.7.3.3.11.7 Error Handling
          12. 12.7.3.3.12 Power Down Mode
          13. 12.7.3.3.13 Emulation
        4. 12.7.3.4 MCRC Programming Examples
          1. 12.7.3.4.1 Example: Auto Mode Using Time Based Event Triggering
            1. 12.7.3.4.1.1 DMA Setup
            2. 12.7.3.4.1.2 Timer Setup
            3. 12.7.3.4.1.3 CRC Setup
          2. 12.7.3.4.2 Example: Auto Mode Without Using Time Based Triggering
            1. 12.7.3.4.2.1 DMA Setup
            2. 12.7.3.4.2.2 CRC Setup
          3. 12.7.3.4.3 Example: Semi-CPU Mode
            1. 12.7.3.4.3.1 DMA Setup
            2. 12.7.3.4.3.2 Timer Setup
            3. 12.7.3.4.3.3 CRC Setup
          4. 12.7.3.4.4 Example: Full-CPU Mode
            1. 12.7.3.4.4.1 CRC Setup
        5. 12.7.3.5 MCRC Registers
      4. 12.7.4 ECC Aggregator
        1. 12.7.4.1 ECC Aggregator Overview
          1. 12.7.4.1.1 ECC Aggregator Features
        2. 12.7.4.2 ECC Aggregator Integration
        3. 12.7.4.3 ECC Aggregator Functional Description
          1. 12.7.4.3.1 ECC Aggregator Block Diagram
          2. 12.7.4.3.2 ECC Aggregator Register Groups
          3. 12.7.4.3.3 Read Access to the ECC Control and Status Registers
          4. 12.7.4.3.4 Serial Write Operation
          5. 12.7.4.3.5 Interrupts
          6. 12.7.4.3.6 Inject Only Mode
        4. 12.7.4.4 ECC Aggregator Registers
  15. 13On-Chip Debug
  16. 14Revision History

8.2.5.3 PI Registers

Table 8-1084 lists the memory-mapped registers for the PI. All register offset addresses not listed in Table 8-1084 should be considered as reserved locations and the register contents should not be modified.

Table 8-1083 PI Instances
InstanceBase Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 0000h
Table 8-1084 PI Registers
OffsetAcronymRegister NameCOMPUTE_CLUSTER0_CTL_CFG_PI Physical Address
2000hDDRSS_PI_0PI Register 00299 2000h
2004hDDRSS_PI_1PI Register 10299 2004h
2008hDDRSS_PI_2PI Register 20299 2008h
200ChDDRSS_PI_3PI Register 30299 200Ch
2010hDDRSS_PI_4PI Register 40299 2010h
2014hDDRSS_PI_5PI Register 50299 2014h
2018hDDRSS_PI_6PI Register 60299 2018h
201ChDDRSS_PI_7PI Register 70299 201Ch
2020hDDRSS_PI_8PI Register 80299 2020h
2024hDDRSS_PI_9PI Register 90299 2024h
2028hDDRSS_PI_10PI Register 100299 2028h
202ChDDRSS_PI_11PI Register 110299 202Ch
2030hDDRSS_PI_12PI Register 120299 2030h
2034hDDRSS_PI_13PI Register 130299 2034h
2038hDDRSS_PI_14PI Register 140299 2038h
203ChDDRSS_PI_15PI Register 150299 203Ch
2040hDDRSS_PI_16PI Register 160299 2040h
2044hDDRSS_PI_17PI Register 170299 2044h
2048hDDRSS_PI_18PI Register 180299 2048h
204ChDDRSS_PI_19PI Register 190299 204Ch
2050hDDRSS_PI_20PI Register 200299 2050h
2054hDDRSS_PI_21PI Register 210299 2054h
2058hDDRSS_PI_22PI Register 220299 2058h
205ChDDRSS_PI_23PI Register 230299 205Ch
2060hDDRSS_PI_24PI Register 240299 2060h
2064hDDRSS_PI_25PI Register 250299 2064h
2068hDDRSS_PI_26PI Register 260299 2068h
206ChDDRSS_PI_27PI Register 270299 206Ch
2070hDDRSS_PI_28PI Register 280299 2070h
2074hDDRSS_PI_29PI Register 290299 2074h
2078hDDRSS_PI_30PI Register 300299 2078h
207ChDDRSS_PI_31PI Register 310299 207Ch
2080hDDRSS_PI_32PI Register 320299 2080h
2084hDDRSS_PI_33PI Register 330299 2084h
2088hDDRSS_PI_34PI Register 340299 2088h
208ChDDRSS_PI_35PI Register 350299 208Ch
2090hDDRSS_PI_36PI Register 360299 2090h
2094hDDRSS_PI_37PI Register 370299 2094h
2098hDDRSS_PI_38PI Register 380299 2098h
209ChDDRSS_PI_39PI Register 390299 209Ch
20A0hDDRSS_PI_40PI Register 400299 20A0h
20A4hDDRSS_PI_41PI Register 410299 20A4h
20A8hDDRSS_PI_42PI Register 420299 20A8h
20AChDDRSS_PI_43PI Register 430299 20ACh
20B0hDDRSS_PI_44PI Register 440299 20B0h
20B4hDDRSS_PI_45PI Register 450299 20B4h
20B8hDDRSS_PI_46PI Register 460299 20B8h
20BChDDRSS_PI_47PI Register 470299 20BCh
20C0hDDRSS_PI_48PI Register 480299 20C0h
20C4hDDRSS_PI_49PI Register 490299 20C4h
20C8hDDRSS_PI_50PI Register 500299 20C8h
20CChDDRSS_PI_51PI Register 510299 20CCh
20D0hDDRSS_PI_52PI Register 520299 20D0h
20D4hDDRSS_PI_53PI Register 530299 20D4h
20D8hDDRSS_PI_54PI Register 540299 20D8h
20DChDDRSS_PI_55PI Register 550299 20DCh
20E0hDDRSS_PI_56PI Register 560299 20E0h
20E4hDDRSS_PI_57PI Register 570299 20E4h
20E8hDDRSS_PI_58PI Register 580299 20E8h
20EChDDRSS_PI_59PI Register 590299 20ECh
20F0hDDRSS_PI_60PI Register 600299 20F0h
20F4hDDRSS_PI_61PI Register 610299 20F4h
20F8hDDRSS_PI_62PI Register 620299 20F8h
20FChDDRSS_PI_63PI Register 630299 20FCh
2100hDDRSS_PI_64PI Register 640299 2100h
2104hDDRSS_PI_65PI Register 650299 2104h
2108hDDRSS_PI_66PI Register 660299 2108h
210ChDDRSS_PI_67PI Register 670299 210Ch
2110hDDRSS_PI_68PI Register 680299 2110h
2114hDDRSS_PI_69PI Register 690299 2114h
2118hDDRSS_PI_70PI Register 700299 2118h
211ChDDRSS_PI_71PI Register 710299 211Ch
2120hDDRSS_PI_72PI Register 720299 2120h
2124hDDRSS_PI_73PI Register 730299 2124h
2128hDDRSS_PI_74PI Register 740299 2128h
212ChDDRSS_PI_75PI Register 750299 212Ch
2130hDDRSS_PI_76PI Register 760299 2130h
2134hDDRSS_PI_77PI Register 770299 2134h
2138hDDRSS_PI_78PI Register 780299 2138h
213ChDDRSS_PI_79PI Register 790299 213Ch
2140hDDRSS_PI_80PI Register 800299 2140h
2144hDDRSS_PI_81PI Register 810299 2144h
2148hDDRSS_PI_82PI Register 820299 2148h
214ChDDRSS_PI_83PI Register 830299 214Ch
2150hDDRSS_PI_84PI Register 840299 2150h
2154hDDRSS_PI_85PI Register 850299 2154h
2158hDDRSS_PI_86PI Register 860299 2158h
215ChDDRSS_PI_87PI Register 870299 215Ch
2160hDDRSS_PI_88PI Register 880299 2160h
2164hDDRSS_PI_89PI Register 890299 2164h
2168hDDRSS_PI_90PI Register 900299 2168h
216ChDDRSS_PI_91PI Register 910299 216Ch
2170hDDRSS_PI_92PI Register 920299 2170h
2174hDDRSS_PI_93PI Register 930299 2174h
2178hDDRSS_PI_94PI Register 940299 2178h
217ChDDRSS_PI_95PI Register 950299 217Ch
2180hDDRSS_PI_96PI Register 960299 2180h
2184hDDRSS_PI_97PI Register 970299 2184h
2188hDDRSS_PI_98PI Register 980299 2188h
218ChDDRSS_PI_99PI Register 990299 218Ch
2190hDDRSS_PI_100PI Register 1000299 2190h
2194hDDRSS_PI_101PI Register 1010299 2194h
2198hDDRSS_PI_102PI Register 1020299 2198h
219ChDDRSS_PI_103PI Register 1030299 219Ch
21A0hDDRSS_PI_104PI Register 1040299 21A0h
21A4hDDRSS_PI_105PI Register 1050299 21A4h
21A8hDDRSS_PI_106PI Register 1060299 21A8h
21AChDDRSS_PI_107PI Register 1070299 21ACh
21B0hDDRSS_PI_108PI Register 1080299 21B0h
21B4hDDRSS_PI_109PI Register 1090299 21B4h
21B8hDDRSS_PI_110PI Register 1100299 21B8h
21BChDDRSS_PI_111PI Register 1110299 21BCh
21C0hDDRSS_PI_112PI Register 1120299 21C0h
21C4hDDRSS_PI_113PI Register 1130299 21C4h
21C8hDDRSS_PI_114PI Register 1140299 21C8h
21CChDDRSS_PI_115PI Register 1150299 21CCh
21D0hDDRSS_PI_116PI Register 1160299 21D0h
21D4hDDRSS_PI_117PI Register 1170299 21D4h
21D8hDDRSS_PI_118PI Register 1180299 21D8h
21DChDDRSS_PI_119PI Register 1190299 21DCh
21E0hDDRSS_PI_120PI Register 1200299 21E0h
21E4hDDRSS_PI_121PI Register 1210299 21E4h
21E8hDDRSS_PI_122PI Register 1220299 21E8h
21EChDDRSS_PI_123PI Register 1230299 21ECh
21F0hDDRSS_PI_124PI Register 1240299 21F0h
21F4hDDRSS_PI_125PI Register 1250299 21F4h
21F8hDDRSS_PI_126PI Register 1260299 21F8h
21FChDDRSS_PI_127PI Register 1270299 21FCh
2200hDDRSS_PI_128PI Register 1280299 2200h
2204hDDRSS_PI_129PI Register 1290299 2204h
2208hDDRSS_PI_130PI Register 1300299 2208h
220ChDDRSS_PI_131PI Register 1310299 220Ch
2210hDDRSS_PI_132PI Register 1320299 2210h
2214hDDRSS_PI_133PI Register 1330299 2214h
2218hDDRSS_PI_134PI Register 1340299 2218h
221ChDDRSS_PI_135PI Register 1350299 221Ch
2220hDDRSS_PI_136PI Register 1360299 2220h
2224hDDRSS_PI_137PI Register 1370299 2224h
2228hDDRSS_PI_138PI Register 1380299 2228h
222ChDDRSS_PI_139PI Register 1390299 222Ch
2230hDDRSS_PI_140PI Register 1400299 2230h
2234hDDRSS_PI_141PI Register 1410299 2234h
2238hDDRSS_PI_142PI Register 1420299 2238h
223ChDDRSS_PI_143PI Register 1430299 223Ch
2240hDDRSS_PI_144PI Register 1440299 2240h
2244hDDRSS_PI_145PI Register 1450299 2244h
2248hDDRSS_PI_146PI Register 1460299 2248h
224ChDDRSS_PI_147PI Register 1470299 224Ch
2250hDDRSS_PI_148PI Register 1480299 2250h
2254hDDRSS_PI_149PI Register 1490299 2254h
2258hDDRSS_PI_150PI Register 1500299 2258h
225ChDDRSS_PI_151PI Register 1510299 225Ch
2260hDDRSS_PI_152PI Register 1520299 2260h
2264hDDRSS_PI_153PI Register 1530299 2264h
2268hDDRSS_PI_154PI Register 1540299 2268h
226ChDDRSS_PI_155PI Register 1550299 226Ch
2270hDDRSS_PI_156PI Register 1560299 2270h
2274hDDRSS_PI_157PI Register 1570299 2274h
2278hDDRSS_PI_158PI Register 1580299 2278h
227ChDDRSS_PI_159PI Register 1590299 227Ch
2280hDDRSS_PI_160PI Register 1600299 2280h
2284hDDRSS_PI_161PI Register 1610299 2284h
2288hDDRSS_PI_162PI Register 1620299 2288h
228ChDDRSS_PI_163PI Register 1630299 228Ch
2290hDDRSS_PI_164PI Register 1640299 2290h
2294hDDRSS_PI_165PI Register 1650299 2294h
2298hDDRSS_PI_166PI Register 1660299 2298h
229ChDDRSS_PI_167PI Register 1670299 229Ch
22A0hDDRSS_PI_168PI Register 1680299 22A0h
22A4hDDRSS_PI_169PI Register 1690299 22A4h
22A8hDDRSS_PI_170PI Register 1700299 22A8h
22AChDDRSS_PI_171PI Register 1710299 22ACh
22B0hDDRSS_PI_172PI Register 1720299 22B0h
22B4hDDRSS_PI_173PI Register 1730299 22B4h
22B8hDDRSS_PI_174PI Register 1740299 22B8h
22BChDDRSS_PI_175PI Register 1750299 22BCh
22C0hDDRSS_PI_176PI Register 1760299 22C0h
22C4hDDRSS_PI_177PI Register 1770299 22C4h
22C8hDDRSS_PI_178PI Register 1780299 22C8h
22CChDDRSS_PI_179PI Register 1790299 22CCh
22D0hDDRSS_PI_180PI Register 1800299 22D0h
22D4hDDRSS_PI_181PI Register 1810299 22D4h
22D8hDDRSS_PI_182PI Register 1820299 22D8h
22DChDDRSS_PI_183PI Register 1830299 22DCh
22E0hDDRSS_PI_184PI Register 1840299 22E0h
22E4hDDRSS_PI_185PI Register 1850299 22E4h
22E8hDDRSS_PI_186PI Register 1860299 22E8h
22EChDDRSS_PI_187PI Register 1870299 22ECh
22F0hDDRSS_PI_188PI Register 1880299 22F0h
22F4hDDRSS_PI_189PI Register 1890299 22F4h
22F8hDDRSS_PI_190PI Register 1900299 22F8h
22FChDDRSS_PI_191PI Register 1910299 22FCh
2300hDDRSS_PI_192PI Register 1920299 2300h
2304hDDRSS_PI_193PI Register 1930299 2304h
2308hDDRSS_PI_194PI Register 1940299 2308h
230ChDDRSS_PI_195PI Register 1950299 230Ch
2310hDDRSS_PI_196PI Register 1960299 2310h
2314hDDRSS_PI_197PI Register 1970299 2314h
2318hDDRSS_PI_198PI Register 1980299 2318h
231ChDDRSS_PI_199PI Register 1990299 231Ch
2320hDDRSS_PI_200PI Register 2000299 2320h
2324hDDRSS_PI_201PI Register 2010299 2324h
2328hDDRSS_PI_202PI Register 2020299 2328h
232ChDDRSS_PI_203PI Register 2030299 232Ch
2330hDDRSS_PI_204PI Register 2040299 2330h
2334hDDRSS_PI_205PI Register 2050299 2334h
2338hDDRSS_PI_206PI Register 2060299 2338h
233ChDDRSS_PI_207PI Register 2070299 233Ch
2340hDDRSS_PI_208PI Register 2080299 2340h
2344hDDRSS_PI_209PI Register 2090299 2344h
2348hDDRSS_PI_210PI Register 2100299 2348h
234ChDDRSS_PI_211PI Register 2110299 234Ch
2350hDDRSS_PI_212PI Register 2120299 2350h
2354hDDRSS_PI_213PI Register 2130299 2354h
2358hDDRSS_PI_214PI Register 2140299 2358h
235ChDDRSS_PI_215PI Register 2150299 235Ch
2360hDDRSS_PI_216PI Register 2160299 2360h
2364hDDRSS_PI_217PI Register 2170299 2364h
2368hDDRSS_PI_218PI Register 2180299 2368h
236ChDDRSS_PI_219PI Register 2190299 236Ch
2370hDDRSS_PI_220PI Register 2200299 2370h
2374hDDRSS_PI_221PI Register 2210299 2374h
2378hDDRSS_PI_222PI Register 2220299 2378h
237ChDDRSS_PI_223PI Register 2230299 237Ch
2380hDDRSS_PI_224PI Register 2240299 2380h
2384hDDRSS_PI_225PI Register 2250299 2384h
2388hDDRSS_PI_226PI Register 2260299 2388h
238ChDDRSS_PI_227PI Register 2270299 238Ch
2390hDDRSS_PI_228PI Register 2280299 2390h
2394hDDRSS_PI_229PI Register 2290299 2394h
2398hDDRSS_PI_230PI Register 2300299 2398h
239ChDDRSS_PI_231PI Register 2310299 239Ch
23A0hDDRSS_PI_232PI Register 2320299 23A0h
23A4hDDRSS_PI_233PI Register 2330299 23A4h
23A8hDDRSS_PI_234PI Register 2340299 23A8h
23AChDDRSS_PI_235PI Register 2350299 23ACh
23B0hDDRSS_PI_236PI Register 2360299 23B0h
23B4hDDRSS_PI_237PI Register 2370299 23B4h
23B8hDDRSS_PI_238PI Register 2380299 23B8h
23BChDDRSS_PI_239PI Register 2390299 23BCh
23C0hDDRSS_PI_240PI Register 2400299 23C0h
23C4hDDRSS_PI_241PI Register 2410299 23C4h
23C8hDDRSS_PI_242PI Register 2420299 23C8h
23CChDDRSS_PI_243PI Register 2430299 23CCh
23D0hDDRSS_PI_244PI Register 2440299 23D0h
23D4hDDRSS_PI_245PI Register 2450299 23D4h
23D8hDDRSS_PI_246PI Register 2460299 23D8h
23DChDDRSS_PI_247PI Register 2470299 23DCh
23E0hDDRSS_PI_248PI Register 2480299 23E0h
23E4hDDRSS_PI_249PI Register 2490299 23E4h
23E8hDDRSS_PI_250PI Register 2500299 23E8h
23EChDDRSS_PI_251PI Register 2510299 23ECh
23F0hDDRSS_PI_252PI Register 2520299 23F0h
23F4hDDRSS_PI_253PI Register 2530299 23F4h
23F8hDDRSS_PI_254PI Register 2540299 23F8h
23FChDDRSS_PI_255PI Register 2550299 23FCh
2400hDDRSS_PI_256PI Register 2560299 2400h
2404hDDRSS_PI_257PI Register 2570299 2404h
2408hDDRSS_PI_258PI Register 2580299 2408h
240ChDDRSS_PI_259PI Register 2590299 240Ch
2410hDDRSS_PI_260PI Register 2600299 2410h
2414hDDRSS_PI_261PI Register 2610299 2414h
2418hDDRSS_PI_262PI Register 2620299 2418h
241ChDDRSS_PI_263PI Register 2630299 241Ch
2420hDDRSS_PI_264PI Register 2640299 2420h
2424hDDRSS_PI_265PI Register 2650299 2424h
2428hDDRSS_PI_266PI Register 2660299 2428h
242ChDDRSS_PI_267PI Register 2670299 242Ch
2430hDDRSS_PI_268PI Register 2680299 2430h
2434hDDRSS_PI_269PI Register 2690299 2434h
2438hDDRSS_PI_270PI Register 2700299 2438h
243ChDDRSS_PI_271PI Register 2710299 243Ch
2440hDDRSS_PI_272PI Register 2720299 2440h
2444hDDRSS_PI_273PI Register 2730299 2444h
2448hDDRSS_PI_274PI Register 2740299 2448h
244ChDDRSS_PI_275PI Register 2750299 244Ch
2450hDDRSS_PI_276PI Register 2760299 2450h
2454hDDRSS_PI_277PI Register 2770299 2454h
2458hDDRSS_PI_278PI Register 2780299 2458h
245ChDDRSS_PI_279PI Register 2790299 245Ch
2460hDDRSS_PI_280PI Register 2800299 2460h
2464hDDRSS_PI_281PI Register 2810299 2464h
2468hDDRSS_PI_282PI Register 2820299 2468h
246ChDDRSS_PI_283PI Register 2830299 246Ch
2470hDDRSS_PI_284PI Register 2840299 2470h
2474hDDRSS_PI_285PI Register 2850299 2474h
2478hDDRSS_PI_286PI Register 2860299 2478h
247ChDDRSS_PI_287PI Register 2870299 247Ch
2480hDDRSS_PI_288PI Register 2880299 2480h
2484hDDRSS_PI_289PI Register 2890299 2484h
2488hDDRSS_PI_290PI Register 2900299 2488h
248ChDDRSS_PI_291PI Register 2910299 248Ch
2490hDDRSS_PI_292PI Register 2920299 2490h
2494hDDRSS_PI_293PI Register 2930299 2494h
2498hDDRSS_PI_294PI Register 2940299 2498h
249ChDDRSS_PI_295PI Register 2950299 249Ch
24A0hDDRSS_PI_296PI Register 2960299 24A0h
24A4hDDRSS_PI_297PI Register 2970299 24A4h
24A8hDDRSS_PI_298PI Register 2980299 24A8h
24AChDDRSS_PI_299PI Register 2990299 24ACh

2.5.3.1 DDRSS_PI_0 Register (Offset = 2000h) [reset = X]

DDRSS_PI_0 is shown in Figure 8-538 and described in Table 8-1086.

Return to Summary Table.

Table 8-1085 DDRSS_PI_0 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2000h
Figure 8-538 DDRSS_PI_0 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVEDPI_DRAM_CLASS
R/W-XR/W-0h
76543210
RESERVEDPI_START
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1086 DDRSS_PI_0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR/WX
11-8PI_DRAM_CLASSR/W0h

Defines the memory class for the PI.

Bh - LPDDR4

All other values reserved

7-1RESERVEDR/WX
0PI_STARTR/W0h

Initiate command processing in the PI.
Set to 1 to initiate.

2.5.3.2 DDRSS_PI_1 Register (Offset = 2004h) [reset = CB1E3F21h]

DDRSS_PI_1 is shown in Figure 8-539 and described in Table 8-1088.

Return to Summary Table.

Table 8-1087 DDRSS_PI_1 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2004h
Figure 8-539 DDRSS_PI_1 Register
313029282726252423222120191817161514131211109876543210
PI_VERSION_0
R-CB1E3F21h
LEGEND: R = Read Only; -n = value after reset
Table 8-1088 DDRSS_PI_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_VERSION_0RCB1E3F21h

Holds the PI version number.
This is a unique number for each PHY IP delivery.
This will help in identifying different version of the PHY IP.
READ-ONLY

2.5.3.3 DDRSS_PI_2 Register (Offset = 2008h) [reset = 078D9209h]

DDRSS_PI_2 is shown in Figure 8-540 and described in Table 8-1090.

Return to Summary Table.

Table 8-1089 DDRSS_PI_2 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2008h
Figure 8-540 DDRSS_PI_2 Register
313029282726252423222120191817161514131211109876543210
PI_VERSION_1
R-078D9209h
LEGEND: R = Read Only; -n = value after reset
Table 8-1090 DDRSS_PI_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_VERSION_1R078D9209h

Holds the PI version number.
This is a unique number for each PHY IP delivery.
This will help in identifying different version of the PHY IP.
READ-ONLY

2.5.3.4 DDRSS_PI_3 Register (Offset = 200Ch) [reset = X]

DDRSS_PI_3 is shown in Figure 8-541 and described in Table 8-1092.

Return to Summary Table.

Table 8-1091 DDRSS_PI_3 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 200Ch
Figure 8-541 DDRSS_PI_3 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_ID
R-XR-1387h
LEGEND: R = Read Only; -n = value after reset
Table 8-1092 DDRSS_PI_3 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDRX
15-0PI_IDR1387h

Holds the PI ID number.
This is a DDR PHY IP identifier.
It is set to 0x1387.
READ-ONLY

2.5.3.5 DDRSS_PI_4 Register (Offset = 2010h) [reset = 0h]

DDRSS_PI_4 is shown in Figure 8-542 and described in Table 8-1094.

Return to Summary Table.

Table 8-1093 DDRSS_PI_4 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2010h
Figure 8-542 DDRSS_PI_4 Register
313029282726252423222120191817161514131211109876543210
PI_UNUSED_REG_0
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1094 DDRSS_PI_4 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_UNUSED_REG_0R0h

Unused register

2.5.3.6 DDRSS_PI_5 Register (Offset = 2014h) [reset = X]

DDRSS_PI_5 is shown in Figure 8-543 and described in Table 8-1096.

Return to Summary Table.

Table 8-1095 DDRSS_PI_5 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2014h
Figure 8-543 DDRSS_PI_5 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDPI_NOTCARE_PHYUPD
R/W-XR/W-0h
15141312111098
RESERVEDPI_INIT_LVL_EN
R/W-XR/W-0h
76543210
RESERVEDPI_NORMAL_LVL_SEQ
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1096 DDRSS_PI_5 Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR/WX
16PI_NOTCARE_PHYUPDR/W0h

Allow the PI to issue a master request to the controller if a phyupd_req from the PHY has been detected.
Set to 1 to issue the master request.

15-9RESERVEDR/WX
8PI_INIT_LVL_ENR/W0h

Enables the initial leveling sequence after PI initialization procedure.
Set to 1 to enable.

7-1RESERVEDR/WX
0PI_NORMAL_LVL_SEQR/W0h

Enable the PI to finish all the pending leveling before releasing the DFI bus.

2.5.3.7 DDRSS_PI_6 Register (Offset = 2018h) [reset = X]

DDRSS_PI_6 is shown in Figure 8-544 and described in Table 8-1098.

Return to Summary Table.

Table 8-1097 DDRSS_PI_6 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2018h
Figure 8-544 DDRSS_PI_6 Register
3130292827262524
RESERVEDPI_TRAIN_ALL_FREQ_REQ
R/W-XW-0h
2322212019181716
RESERVED
R/W-64h
15141312111098
PI_TCMD_GAP
R/W-0h
76543210
PI_TCMD_GAP
R/W-0h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1098 DDRSS_PI_6 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_TRAIN_ALL_FREQ_REQW0h

Triggers training for all supported frequencies in PI_FREQ_MAP.
Applies to LPDDR4 devices onlyh.
Set to 1 to trigger.
Only applicable after memory initialization has been completed.
Can be used to train new frequencies that were not available at initialization time.
WRITE-ONLY

23-16RESERVEDR/W64h

Reserved

15-0PI_TCMD_GAPR/W0h

Specifies the minimum gap in DFI clocks between two commands.
Used to guard the timing from the last command of MC and the first command of PI when MC hand over the control of DFI to PI.

2.5.3.8 DDRSS_PI_7 Register (Offset = 201Ch) [reset = X]

DDRSS_PI_7 is shown in Figure 8-545 and described in Table 8-1100.

Return to Summary Table.

Table 8-1099 DDRSS_PI_7 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 201Ch
Figure 8-545 DDRSS_PI_7 Register
3130292827262524
RESERVEDPI_DFI_PHYMSTR_STATE_SEL_R
R/W-XR/W-0h
2322212019181716
RESERVEDPI_DFI_PHYMSTR_CS_STATE_R
R/W-XR/W-0h
15141312111098
RESERVEDPI_DFI_PHYMSTR_TYPE
R/W-XR/W-0h
76543210
RESERVEDPI_DFI_VERSION
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1100 DDRSS_PI_7 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_DFI_PHYMSTR_STATE_SEL_RR/W0h

DFI PHY Master State Select: Indication from the PHY to the MC whether the requested memory state is IDLE or Self refresh.
'b
0: indicates that the corresponding CS must be put into the IDLE state.
'b
1: indicates that the corresponding CS must be put into the Self refresh state.

23-17RESERVEDR/WX
16PI_DFI_PHYMSTR_CS_STATE_RR/W0h

This signal indicates the state of the DRAM when the PHY becomes the master.
'b
0: The PHY specifies the required state, using the dfi_phymstr_state_sel signal.
'b
1: is reserved.

15-10RESERVEDR/WX
9-8PI_DFI_PHYMSTR_TYPER/W0h

DFI Master Request Type used for dfi 4.1 verision: This signal indicates the required state of DRAM when PHY becomes the master.
Each memory rank uses one bit.
1'b
0: IDLE.
The MC should close all the pages.
1'b
1: IDLE or Self Refresh.

7-1RESERVEDR/WX
0PI_DFI_VERSIONR/W0h

Define the DFI master version, set 1 for DFI4.1, set 0 for DFI4.0

2.5.3.9 DDRSS_PI_8 Register (Offset = 2020h) [reset = 0h]

DDRSS_PI_8 is shown in Figure 8-546 and described in Table 8-1102.

Return to Summary Table.

Table 8-1101 DDRSS_PI_8 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2020h
Figure 8-546 DDRSS_PI_8 Register
313029282726252423222120191817161514131211109876543210
PI_TDFI_PHYMSTR_MAX
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1102 DDRSS_PI_8 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TDFI_PHYMSTR_MAXR0h

Indicates the maximum number of DFI clock cycles registered while the dfi_phymstr_req signal is asserted and the dfi_phymstr_ack signal is asserted.
READ-ONLY.

2.5.3.10 DDRSS_PI_9 Register (Offset = 2024h) [reset = X]

DDRSS_PI_9 is shown in Figure 8-547 and described in Table 8-1104.

Return to Summary Table.

Table 8-1103 DDRSS_PI_9 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2024h
Figure 8-547 DDRSS_PI_9 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TDFI_PHYMSTR_RESP
R-XR-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1104 DDRSS_PI_9 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDRX
19-0PI_TDFI_PHYMSTR_RESPR0h

Indicates the maximum number of DFI clock cycles registered between a dfi_phymstr_req signal assertion and a dfi_phymstr_ack signal assertion.
READ-ONLY

2.5.3.11 DDRSS_PI_10 Register (Offset = 2028h) [reset = X]

DDRSS_PI_10 is shown in Figure 8-548 and described in Table 8-1106.

Return to Summary Table.

Table 8-1105 DDRSS_PI_10 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2028h
Figure 8-548 DDRSS_PI_10 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TDFI_PHYUPD_RESP
R-XR-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1106 DDRSS_PI_10 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDRX
19-0PI_TDFI_PHYUPD_RESPR0h

Indicates the maximum number of DFI clock cycles registered between a dfi_phyupd_req signal assertion and a dfi_phyupd_ack signal assertion.
READ-ONLY.

2.5.3.12 DDRSS_PI_11 Register (Offset = 202Ch) [reset = 0h]

DDRSS_PI_11 is shown in Figure 8-549 and described in Table 8-1108.

Return to Summary Table.

Table 8-1107 DDRSS_PI_11 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 202Ch
Figure 8-549 DDRSS_PI_11 Register
313029282726252423222120191817161514131211109876543210
PI_TDFI_PHYUPD_MAX
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1108 DDRSS_PI_11 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TDFI_PHYUPD_MAXR0h

Indicates the maximum number of DFI clock cycles registered while the dfi_phyupd_req signal is asserted and the dfi_phy_ack signal is asserted.
READ-ONLY.

2.5.3.13 DDRSS_PI_12 Register (Offset = 2030h) [reset = 0h]

DDRSS_PI_12 is shown in Figure 8-550 and described in Table 8-1110.

Return to Summary Table.

Table 8-1109 DDRSS_PI_12 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2030h
Figure 8-550 DDRSS_PI_12 Register
313029282726252423222120191817161514131211109876543210
PI_FREQ_MAP
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1110 DDRSS_PI_12 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_FREQ_MAPR/W0h

Frequency map for supported working frequencies.
Each bit represents one supported frequency.

2.5.3.14 DDRSS_PI_13 Register (Offset = 2034h) [reset = X]

DDRSS_PI_13 is shown in Figure 8-551 and described in Table 8-1112.

Return to Summary Table.

Table 8-1111 DDRSS_PI_13 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2034h
Figure 8-551 DDRSS_PI_13 Register
3130292827262524
RESERVEDRESERVED
R/W-XR/W-0h
2322212019181716
RESERVEDPI_SW_RST_N
R/W-XR/W-1h
15141312111098
RESERVEDPI_INIT_DFS_CALVL_ONLY
R/W-XR/W-0h
76543210
RESERVEDPI_INIT_WORK_FREQ
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1112 DDRSS_PI_13 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24RESERVEDR/W0h

Reserved

23-17RESERVEDR/WX
16PI_SW_RST_NR/W1h

User request to reset the whole PI except the parameter modules.
Set 0 to reset, set to 1 to release.

15-9RESERVEDR/WX
8PI_INIT_DFS_CALVL_ONLYR/W0h

Enables frequency training for CA leveling only.
Other trainings are not performed.

7-5RESERVEDR/WX
4-0PI_INIT_WORK_FREQR/W0h

Indicates the initial work frequency after initialization and initial leveling sequence.

2.5.3.15 DDRSS_PI_14 Register (Offset = 2038h) [reset = X]

DDRSS_PI_14 is shown in Figure 8-552 and described in Table 8-1114.

Return to Summary Table.

Table 8-1113 DDRSS_PI_14 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2038h
Figure 8-552 DDRSS_PI_14 Register
3130292827262524
RESERVEDPI_TMRR
R/W-XR/W-0h
2322212019181716
RESERVEDPI_SRX_LVL_TARGET_CS_EN
R/W-XR/W-0h
15141312111098
RESERVEDPI_RANK_NUM_PER_CKE
R/W-XR/W-0h
76543210
RESERVEDPI_CS_MAP
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1114 DDRSS_PI_14 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_TMRRR/W0h

DRAM tMRR value in memory clock cycles.

23-17RESERVEDR/WX
16PI_SRX_LVL_TARGET_CS_ENR/W0h

Defines self refresh exit trigger target rank/ranks training or all ranks training.
1: The rank/ranks exit from self refresh will trigger the corresponding rank/ranks training.
Note: If multiple ranks exit from self refresh, current design only support the multiple ranks srx command issues at the same time.
0: Any rank/ranks exit from self refresh will trigger all ranks training

15-13RESERVEDR/WX
12-8PI_RANK_NUM_PER_CKER/W0h

Defines the number of chip selects share one cke

7-4RESERVEDR/WX
3-0PI_CS_MAPR/W0h

Defines which chip selects are active.

2.5.3.16 DDRSS_PI_15 Register (Offset = 203Ch) [reset = X]

DDRSS_PI_15 is shown in Figure 8-553 and described in Table 8-1116.

Return to Summary Table.

Table 8-1115 DDRSS_PI_15 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 203Ch
Figure 8-553 DDRSS_PI_15 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDRESERVED
R/W-XR/W-0h
15141312111098
RESERVEDPI_MCAREF_FORWARD_ONLY
R/W-XR/W-0h
76543210
RESERVEDPI_PREAMBLE_SUPPORT
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1116 DDRSS_PI_15 Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR/WX
16RESERVEDR/W0h

Reserved

15-9RESERVEDR/WX
8PI_MCAREF_FORWARD_ONLYR/W0h

Controls the generation of AREF from the PI module or forward the MC received value.

7-2RESERVEDR/WX
1-0PI_PREAMBLE_SUPPORTR/W0h

Defines the read and write preamble length.
bit
0: Selection of one or two cycle preamble for read burst transfers.
bit
1: Selection of one or two cycles write burst transfers for NON-DDR5, one or multi(up to four) cycles write burst transfers for DDR5.

2.5.3.17 DDRSS_PI_16 Register (Offset = 2040h) [reset = X]

DDRSS_PI_16 is shown in Figure 8-554 and described in Table 8-1118.

Return to Summary Table.

Table 8-1117 DDRSS_PI_16 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2040h
Figure 8-554 DDRSS_PI_16 Register
3130292827262524
RESERVEDPI_ON_DFIBUS
R/W-XR-0h
2322212019181716
RESERVEDPI_TREF_INTERVAL
R/W-XR/W-0h
15141312111098
PI_TREF_INTERVAL
R/W-0h
76543210
PI_TREF_INTERVAL
R/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1118 DDRSS_PI_16 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_ON_DFIBUSR0h

Monitors the state of the PI controlling the DFI bus.
1 means PI is in control.
READ-ONLY.

23-20RESERVEDR/WX
19-0PI_TREF_INTERVALR/W0h

Defines the cycles between refreshes to different chip selects.

2.5.3.18 DDRSS_PI_17 Register (Offset = 2044h) [reset = X]

DDRSS_PI_17 is shown in Figure 8-555 and described in Table 8-1120.

Return to Summary Table.

Table 8-1119 DDRSS_PI_17 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2044h
Figure 8-555 DDRSS_PI_17 Register
3130292827262524
RESERVEDPI_SW_WRLVL_RESP_0
R/W-XR-0h
2322212019181716
RESERVEDPI_SWLVL_OP_DONE
R/W-XR-0h
15141312111098
RESERVEDPI_SWLVL_LOAD
R/W-XW-0h
76543210
RESERVEDPI_DATA_RETENTION
R/W-XR-0h
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1120 DDRSS_PI_17 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_SW_WRLVL_RESP_0R0h

Write leveling response for data slice 0.
READ-ONLY

23-17RESERVEDR/WX
16PI_SWLVL_OP_DONER0h

Reports the status of the software leveling operation.
Value of 1 indicates operation complete.
READ-ONLY

15-9RESERVEDR/WX
8PI_SWLVL_LOADW0h

User request to load delays and execute software leveling.
Set to 1 to trigger.
WRITE-ONLY

7-1RESERVEDR/WX
0PI_DATA_RETENTIONR0h

Monitors the readiness for the PHY to be put into data retention mode after pi_sref_entry req parameter has been written.
1 means ready for data retention.
READ-ONLY.

2.5.3.19 DDRSS_PI_18 Register (Offset = 2048h) [reset = X]

DDRSS_PI_18 is shown in Figure 8-556 and described in Table 8-1122.

Return to Summary Table.

Table 8-1121 DDRSS_PI_18 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2048h
Figure 8-556 DDRSS_PI_18 Register
3130292827262524
RESERVEDPI_SW_RDLVL_RESP_0
R-XR-0h
2322212019181716
RESERVEDPI_SW_WRLVL_RESP_3
R-XR-0h
15141312111098
RESERVEDPI_SW_WRLVL_RESP_2
R-XR-0h
76543210
RESERVEDPI_SW_WRLVL_RESP_1
R-XR-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1122 DDRSS_PI_18 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDRX
25-24PI_SW_RDLVL_RESP_0R0h

Read leveling response for data slice 0.
READ-ONLY

23-17RESERVEDRX
16PI_SW_WRLVL_RESP_3R0h

Write leveling response for data slice 3.
READ-ONLY

15-9RESERVEDRX
8PI_SW_WRLVL_RESP_2R0h

Write leveling response for data slice 2.
READ-ONLY

7-1RESERVEDRX
0PI_SW_WRLVL_RESP_1R0h

Write leveling response for data slice 1.
READ-ONLY

2.5.3.20 DDRSS_PI_19 Register (Offset = 204Ch) [reset = X]

DDRSS_PI_19 is shown in Figure 8-557 and described in Table 8-1124.

Return to Summary Table.

Table 8-1123 DDRSS_PI_19 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 204Ch
Figure 8-557 DDRSS_PI_19 Register
3130292827262524
RESERVEDPI_SW_CALVL_RESP_0
R-XR-0h
2322212019181716
RESERVEDPI_SW_RDLVL_RESP_3
R-XR-0h
15141312111098
RESERVEDPI_SW_RDLVL_RESP_2
R-XR-0h
76543210
RESERVEDPI_SW_RDLVL_RESP_1
R-XR-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1124 DDRSS_PI_19 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDRX
25-24PI_SW_CALVL_RESP_0R0h

CA leveling response for address slice 0.
READ-ONLY

23-18RESERVEDRX
17-16PI_SW_RDLVL_RESP_3R0h

Read leveling response for data slice 3.
READ-ONLY

15-10RESERVEDRX
9-8PI_SW_RDLVL_RESP_2R0h

Read leveling response for data slice 2.
READ-ONLY

7-2RESERVEDRX
1-0PI_SW_RDLVL_RESP_1R0h

Read leveling response for data slice 1.
READ-ONLY

2.5.3.21 DDRSS_PI_20 Register (Offset = 2050h) [reset = X]

DDRSS_PI_20 is shown in Figure 8-558 and described in Table 8-1126.

Return to Summary Table.

Table 8-1125 DDRSS_PI_20 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2050h
Figure 8-558 DDRSS_PI_20 Register
3130292827262524
RESERVEDPI_SWLVL_WR_SLICE_0
R/W-XW-0h
2322212019181716
RESERVEDPI_SWLVL_EXIT
R/W-XW-0h
15141312111098
RESERVEDPI_SWLVL_START
R/W-XW-0h
76543210
RESERVEDPI_SW_LEVELING_MODE
R/W-XR/W-0h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1126 DDRSS_PI_20 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_SWLVL_WR_SLICE_0W0h

SW leveling write command in WDQ training.
WRITE-ONLY

23-17RESERVEDR/WX
16PI_SWLVL_EXITW0h

User request to exit software leveling.
Set to 1 to exit.
WRITE-ONLY

15-9RESERVEDR/WX
8PI_SWLVL_STARTW0h

User request to initiate software leveling of type in the SW_LEVELING_MODE parameter.
Set to 1 to trigger.
WRITE-ONLY

7-3RESERVEDR/WX
2-0PI_SW_LEVELING_MODER/W0h

Defines the leveling operation for software leveling.
Set to 'b000 for DDR4 VREF training, set to b001 for write leveling, set to b010 for read data eye training, or set to b011 for read gate training, set to b100 for ca training, set to b101 for wdq training.

2.5.3.22 DDRSS_PI_21 Register (Offset = 2054h) [reset = X]

DDRSS_PI_21 is shown in Figure 8-559 and described in Table 8-1128.

Return to Summary Table.

Table 8-1127 DDRSS_PI_21 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2054h
Figure 8-559 DDRSS_PI_21 Register
3130292827262524
RESERVEDPI_SWLVL_WR_SLICE_1
R/W-XW-0h
2322212019181716
RESERVEDPI_SW_WDQLVL_RESP_0
R/W-XR-0h
15141312111098
RESERVEDPI_SWLVL_VREF_UPDATE_SLICE_0
R/W-XW-0h
76543210
RESERVEDPI_SWLVL_RD_SLICE_0
R/W-XW-0h
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1128 DDRSS_PI_21 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_SWLVL_WR_SLICE_1W0h

SW leveling write command in WDQ training.
WRITE-ONLY

23-18RESERVEDR/WX
17-16PI_SW_WDQLVL_RESP_0R0h

Leveling response for data slice 0.
READ-ONLY

15-9RESERVEDR/WX
8PI_SWLVL_VREF_UPDATE_SLICE_0W0h

SW leveling vref update command in WDQ training.
WRITE-ONLY

7-1RESERVEDR/WX
0PI_SWLVL_RD_SLICE_0W0h

SW leveling read command in WDQ training.
WRITE-ONLY

2.5.3.23 DDRSS_PI_22 Register (Offset = 2058h) [reset = X]

DDRSS_PI_22 is shown in Figure 8-560 and described in Table 8-1130.

Return to Summary Table.

Table 8-1129 DDRSS_PI_22 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2058h
Figure 8-560 DDRSS_PI_22 Register
3130292827262524
RESERVEDPI_SWLVL_WR_SLICE_2
R/W-XW-0h
2322212019181716
RESERVEDPI_SW_WDQLVL_RESP_1
R/W-XR-0h
15141312111098
RESERVEDPI_SWLVL_VREF_UPDATE_SLICE_1
R/W-XW-0h
76543210
RESERVEDPI_SWLVL_RD_SLICE_1
R/W-XW-0h
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1130 DDRSS_PI_22 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_SWLVL_WR_SLICE_2W0h

SW leveling write command in WDQ training.
WRITE-ONLY

23-18RESERVEDR/WX
17-16PI_SW_WDQLVL_RESP_1R0h

Leveling response for data slice 1.
READ-ONLY

15-9RESERVEDR/WX
8PI_SWLVL_VREF_UPDATE_SLICE_1W0h

SW leveling vref update command in WDQ training.
WRITE-ONLY

7-1RESERVEDR/WX
0PI_SWLVL_RD_SLICE_1W0h

SW leveling read command in WDQ training.
WRITE-ONLY

2.5.3.24 DDRSS_PI_23 Register (Offset = 205Ch) [reset = X]

DDRSS_PI_23 is shown in Figure 8-561 and described in Table 8-1132.

Return to Summary Table.

Table 8-1131 DDRSS_PI_23 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 205Ch
Figure 8-561 DDRSS_PI_23 Register
3130292827262524
RESERVEDPI_SWLVL_WR_SLICE_3
R/W-XW-0h
2322212019181716
RESERVEDPI_SW_WDQLVL_RESP_2
R/W-XR-0h
15141312111098
RESERVEDPI_SWLVL_VREF_UPDATE_SLICE_2
R/W-XW-0h
76543210
RESERVEDPI_SWLVL_RD_SLICE_2
R/W-XW-0h
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1132 DDRSS_PI_23 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_SWLVL_WR_SLICE_3W0h

SW leveling write command in WDQ training.
WRITE-ONLY

23-18RESERVEDR/WX
17-16PI_SW_WDQLVL_RESP_2R0h

Leveling response for data slice 2.
READ-ONLY

15-9RESERVEDR/WX
8PI_SWLVL_VREF_UPDATE_SLICE_2W0h

SW leveling vref update command in WDQ training.
WRITE-ONLY

7-1RESERVEDR/WX
0PI_SWLVL_RD_SLICE_2W0h

SW leveling read command in WDQ training.
WRITE-ONLY

2.5.3.25 DDRSS_PI_24 Register (Offset = 2060h) [reset = X]

DDRSS_PI_24 is shown in Figure 8-562 and described in Table 8-1134.

Return to Summary Table.

Table 8-1133 DDRSS_PI_24 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2060h
Figure 8-562 DDRSS_PI_24 Register
3130292827262524
RESERVEDPI_SWLVL_SM2_START
R/W-XW-0h
2322212019181716
RESERVEDPI_SW_WDQLVL_RESP_3
R/W-XR-0h
15141312111098
RESERVEDPI_SWLVL_VREF_UPDATE_SLICE_3
R/W-XW-0h
76543210
RESERVEDPI_SWLVL_RD_SLICE_3
R/W-XW-0h
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1134 DDRSS_PI_24 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_SWLVL_SM2_STARTW0h

SW leveling start command for stage 2.
WRITE-ONLY

23-18RESERVEDR/WX
17-16PI_SW_WDQLVL_RESP_3R0h

Leveling response for data slice 3.
READ-ONLY

15-9RESERVEDR/WX
8PI_SWLVL_VREF_UPDATE_SLICE_3W0h

SW leveling vref update command in WDQ training.
WRITE-ONLY

7-1RESERVEDR/WX
0PI_SWLVL_RD_SLICE_3W0h

SW leveling read command in WDQ training.
WRITE-ONLY

2.5.3.26 DDRSS_PI_25 Register (Offset = 2064h) [reset = X]

DDRSS_PI_25 is shown in Figure 8-563 and described in Table 8-1136.

Return to Summary Table.

Table 8-1135 DDRSS_PI_25 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2064h
Figure 8-563 DDRSS_PI_25 Register
3130292827262524
RESERVEDPI_DFS_PERIOD_EN
R/W-XR/W-0h
2322212019181716
RESERVEDPI_SEQUENTIAL_LVL_REQ
R/W-XW-0h
15141312111098
RESERVEDPI_SWLVL_SM2_RD
R/W-XW-0h
76543210
RESERVEDPI_SWLVL_SM2_WR
R/W-XW-0h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1136 DDRSS_PI_25 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_DFS_PERIOD_ENR/W0h

Enable the DFS triggered periodic leveling.

23-17RESERVEDR/WX
16PI_SEQUENTIAL_LVL_REQW0h

User request to initiate all possible leveling sequences.
Set to 1 to trigger.
WRITE-ONLY

15-9RESERVEDR/WX
8PI_SWLVL_SM2_RDW0h

SW leveling read command for stage 2.
WRITE-ONLY

7-1RESERVEDR/WX
0PI_SWLVL_SM2_WRW0h

SW leveling write command for stage 2.
WRITE-ONLY

2.5.3.27 DDRSS_PI_26 Register (Offset = 2068h) [reset = X]

DDRSS_PI_26 is shown in Figure 8-564 and described in Table 8-1138.

Return to Summary Table.

Table 8-1137 DDRSS_PI_26 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2068h
Figure 8-564 DDRSS_PI_26 Register
3130292827262524
RESERVEDPI_WRLVL_REQ
R/W-XW-0h
2322212019181716
RESERVEDPI_16BIT_DRAM_CONNECT
R/W-XR/W-1h
15141312111098
RESERVEDPI_DFI40_POLARITY
R/W-XR/W-0h
76543210
RESERVEDPI_SRE_PERIOD_EN
R/W-XR/W-0h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1138 DDRSS_PI_26 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_WRLVL_REQW0h

User request to initiate write leveling.
Set to 1 to trigger.
WRITE-ONLY

23-17RESERVEDR/WX
16PI_16BIT_DRAM_CONNECTR/W1h

Enable 16/32 bit DRAM configuration.
0: 16bit DRAM.
1: 32 bit DRAM.

15-9RESERVEDR/WX
8PI_DFI40_POLARITYR/W0h

Defines the polarity of the dfi_wrdata_cs_n/dfi_rddata_cs_n signals.

7-1RESERVEDR/WX
0PI_SRE_PERIOD_ENR/W0h

Enable the self refresh exit triggered periodic leveling.

2.5.3.28 DDRSS_PI_27 Register (Offset = 206Ch) [reset = X]

DDRSS_PI_27 is shown in Figure 8-565 and described in Table 8-1140.

Return to Summary Table.

Table 8-1139 DDRSS_PI_27 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 206Ch
Figure 8-565 DDRSS_PI_27 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDPI_WLMRD
R/W-XR/W-0h
15141312111098
RESERVEDPI_WLDQSEN
R/W-XR/W-0h
76543210
RESERVEDPI_WRLVL_CS
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1140 DDRSS_PI_27 Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR/WX
21-16PI_WLMRDR/W0h

Delay from issuing MRS to first write leveling strobe.

15-14RESERVEDR/WX
13-8PI_WLDQSENR/W0h

Delay from issuing MRS to first DQS strobe for write leveling.

7-2RESERVEDR/WX
1-0PI_WRLVL_CSR/W0h

Specifies the target chip select for the write leveling operation initiated through the WRLVL_REQ parameter.

2.5.3.29 DDRSS_PI_28 Register (Offset = 2070h) [reset = X]

DDRSS_PI_28 is shown in Figure 8-566 and described in Table 8-1142.

Return to Summary Table.

Table 8-1141 DDRSS_PI_28 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2070h
Figure 8-566 DDRSS_PI_28 Register
3130292827262524
RESERVEDPI_WRLVL_ON_SREF_EXIT
R/W-XR/W-0h
2322212019181716
RESERVEDPI_WRLVL_PERIODIC
R/W-XR/W-0h
15141312111098
PI_WRLVL_INTERVAL
R/W-0h
76543210
PI_WRLVL_INTERVAL
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1142 DDRSS_PI_28 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_WRLVL_ON_SREF_EXITR/W0h

Enables automatic write leveling on a self-refresh exit.
Set to 1 to enable.

23-17RESERVEDR/WX
16PI_WRLVL_PERIODICR/W0h

Enables the use of the dfi_lvl_periodic signal during write leveling.
Set to 1 to enable.

15-0PI_WRLVL_INTERVALR/W0h

Number of long count sequences counted between automatic write leveling commands.

2.5.3.30 DDRSS_PI_29 Register (Offset = 2074h) [reset = X]

DDRSS_PI_29 is shown in Figure 8-567 and described in Table 8-1144.

Return to Summary Table.

Table 8-1143 DDRSS_PI_29 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2074h
Figure 8-567 DDRSS_PI_29 Register
3130292827262524
RESERVEDPI_WRLVL_CS_MAP
R/W-XR/W-0h
2322212019181716
RESERVEDPI_WRLVL_ROTATE
R/W-XR/W-0h
15141312111098
RESERVEDPI_WRLVL_RESP_MASK
R/W-XR/W-0h
76543210
RESERVEDPI_WRLVL_DISABLE_DFS
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1144 DDRSS_PI_29 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_WRLVL_CS_MAPR/W0h

Defines the chip select map for write leveling operations.
Bit (0) controls cs0, bit (1) controls cs1, etc.
Set each bit to 1 to enable chip for write leveling.

23-17RESERVEDR/WX
16PI_WRLVL_ROTATER/W0h

Enables rotational CS for counter triggered automatic write leveling.
Set to 1, only one rank's write levling will process, the rank number is rotational for each time that write leveling been triggered by counter expiring.
Set to 0 or not a short pattern leveling (indicated by dfi_lvl_periodic), the counter expired write leveling will process all the ranks.

15-12RESERVEDR/WX
11-8PI_WRLVL_RESP_MASKR/W0h

Mask for the dfi_wrlvl_resp signal during write leveling.

7-1RESERVEDR/WX
0PI_WRLVL_DISABLE_DFSR/W0h

Disable automatic write leveling on freq change.
Set to 1 to disable wrlvl on dfs,set 0 enable wrlvl on dfs.

2.5.3.31 DDRSS_PI_30 Register (Offset = 2078h) [reset = X]

DDRSS_PI_30 is shown in Figure 8-568 and described in Table 8-1146.

Return to Summary Table.

Table 8-1145 DDRSS_PI_30 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2078h
Figure 8-568 DDRSS_PI_30 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
PI_TDFI_WRLVL_EN
R/W-0h
76543210
RESERVEDPI_WRLVL_ERROR_STATUS
R/W-XR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1146 DDRSS_PI_30 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/WX
15-8PI_TDFI_WRLVL_ENR/W0h

Defines the DFI tWRLVL_EN timing parameter (in DFI clocks), the minimum cycles from a dfi_wrlvl_en assertion to the first dfi_wrlvl_strobe assertion.

7-1RESERVEDR/WX
0PI_WRLVL_ERROR_STATUSR0h

Holds the error associated with the write level error interrupt.
Bit (0) set indicates a TDFI_WRLVL_MAX parameter violation and bit (1) set indicates a TDFI_WRLVL_RESP parameter violation.
READ-ONLY

2.5.3.32 DDRSS_PI_31 Register (Offset = 207Ch) [reset = 0h]

DDRSS_PI_31 is shown in Figure 8-569 and described in Table 8-1148.

Return to Summary Table.

Table 8-1147 DDRSS_PI_31 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 207Ch
Figure 8-569 DDRSS_PI_31 Register
313029282726252423222120191817161514131211109876543210
PI_TDFI_WRLVL_RESP
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1148 DDRSS_PI_31 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TDFI_WRLVL_RESPR/W0h

Defines the DFI tWRLVL_RESP timing parameter (in DFI clocks), the maximum cycles between a dfi_wrlvl_req assertion and a dfi_wrlvl_en assertion.

2.5.3.33 DDRSS_PI_32 Register (Offset = 2080h) [reset = 0h]

DDRSS_PI_32 is shown in Figure 8-570 and described in Table 8-1150.

Return to Summary Table.

Table 8-1149 DDRSS_PI_32 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2080h
Figure 8-570 DDRSS_PI_32 Register
313029282726252423222120191817161514131211109876543210
PI_TDFI_WRLVL_MAX
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1150 DDRSS_PI_32 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TDFI_WRLVL_MAXR/W0h

Defines the DFI tWRLVL_MAX timing parameter (in DFI clocks), the maximum cycles between a dfi_wrlvl_en assertion and a valid dfi_wrlvl_resp.

2.5.3.34 DDRSS_PI_33 Register (Offset = 2084h) [reset = X]

DDRSS_PI_33 is shown in Figure 8-571 and described in Table 8-1152.

Return to Summary Table.

Table 8-1151 DDRSS_PI_33 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2084h
Figure 8-571 DDRSS_PI_33 Register
3130292827262524
RESERVEDPI_ODT_VALUE
R/W-XR/W-0h
2322212019181716
RESERVEDPI_TODTH_RD
R/W-XR/W-0h
15141312111098
RESERVEDPI_TODTH_WR
R/W-XR/W-0h
76543210
RESERVEDPI_WRLVL_STROBE_NUM
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1152 DDRSS_PI_33 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_ODT_VALUER/W0h

When using LPDDR4, this value will be driven out on the dfi_odt signal.

23-20RESERVEDR/WX
19-16PI_TODTH_RDR/W0h

Defines the minimum DRAM cycles of ODT high time for a read command, in memory clocks.

15-12RESERVEDR/WX
11-8PI_TODTH_WRR/W0h

Defines the minimum DRAM cycles of ODT high time for a write command, in memory clocks.

7-5RESERVEDR/WX
4-0PI_WRLVL_STROBE_NUMR/W0h

Defines the number of write leveling strobes generated.

2.5.3.35 DDRSS_PI_34 Register (Offset = 2088h) [reset = X]

DDRSS_PI_34 is shown in Figure 8-572 and described in Table 8-1154.

Return to Summary Table.

Table 8-1153 DDRSS_PI_34 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2088h
Figure 8-572 DDRSS_PI_34 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDPI_RDLVL_CS
R/W-XR/W-0h
15141312111098
RESERVEDPI_RDLVL_GATE_REQ
R/W-XW-0h
76543210
RESERVEDPI_RDLVL_REQ
R/W-XW-0h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1154 DDRSS_PI_34 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/WX
17-16PI_RDLVL_CSR/W0h

Specifies the target chip select for the data eye training operation initiated through the RDLVL_REQ parameter or the gate training operation initiated through the RDLVL_GATE_REQ parameter.

15-9RESERVEDR/WX
8PI_RDLVL_GATE_REQW0h

User request to initiate gate training.
Set to 1 to trigger.
WRITE-ONLY

7-1RESERVEDR/WX
0PI_RDLVL_REQW0h

User request to initiate data eye training.
Set to 1 to trigger.
WRITE-ONLY

2.5.3.36 DDRSS_PI_35 Register (Offset = 208Ch) [reset = 0h]

DDRSS_PI_35 is shown in Figure 8-573 and described in Table 8-1156.

Return to Summary Table.

Table 8-1155 DDRSS_PI_35 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 208Ch
Figure 8-573 DDRSS_PI_35 Register
313029282726252423222120191817161514131211109876543210
PI_RDLVL_PAT_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1156 DDRSS_PI_35 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_RDLVL_PAT_0R/W0h

Non-default pattern 0 used for read data eye training of DDR4 or LPDDR4, and read dbi training of DDR4.

2.5.3.37 DDRSS_PI_36 Register (Offset = 2090h) [reset = 0h]

DDRSS_PI_36 is shown in Figure 8-574 and described in Table 8-1158.

Return to Summary Table.

Table 8-1157 DDRSS_PI_36 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2090h
Figure 8-574 DDRSS_PI_36 Register
313029282726252423222120191817161514131211109876543210
PI_RDLVL_PAT_1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1158 DDRSS_PI_36 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_RDLVL_PAT_1R/W0h

Non-default pattern 1 used for read data eye training of DDR4 or LPDDR4, and read dbi training of DDR4.

2.5.3.38 DDRSS_PI_37 Register (Offset = 2094h) [reset = 0h]

DDRSS_PI_37 is shown in Figure 8-575 and described in Table 8-1160.

Return to Summary Table.

Table 8-1159 DDRSS_PI_37 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2094h
Figure 8-575 DDRSS_PI_37 Register
313029282726252423222120191817161514131211109876543210
PI_RDLVL_PAT_2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1160 DDRSS_PI_37 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_RDLVL_PAT_2R/W0h

Non-default pattern 2 used for read data eye training of DDR4 or LPDDR4, and read dbi training of DDR4.

2.5.3.39 DDRSS_PI_38 Register (Offset = 2098h) [reset = 0h]

DDRSS_PI_38 is shown in Figure 8-576 and described in Table 8-1162.

Return to Summary Table.

Table 8-1161 DDRSS_PI_38 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2098h
Figure 8-576 DDRSS_PI_38 Register
313029282726252423222120191817161514131211109876543210
PI_RDLVL_PAT_3
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1162 DDRSS_PI_38 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_RDLVL_PAT_3R/W0h

Non-default pattern 3 used for read data eye training of DDR4 or LPDDR4, and read dbi training of DDR4.

2.5.3.40 DDRSS_PI_39 Register (Offset = 209Ch) [reset = 0h]

DDRSS_PI_39 is shown in Figure 8-577 and described in Table 8-1164.

Return to Summary Table.

Table 8-1163 DDRSS_PI_39 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 209Ch
Figure 8-577 DDRSS_PI_39 Register
313029282726252423222120191817161514131211109876543210
PI_RDLVL_PAT_4
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1164 DDRSS_PI_39 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_RDLVL_PAT_4R/W0h

Non-default pattern 4 used for read data eye training of DDR4 or LPDDR4, and read dbi training of DDR4.

2.5.3.41 DDRSS_PI_40 Register (Offset = 20A0h) [reset = 0h]

DDRSS_PI_40 is shown in Figure 8-578 and described in Table 8-1166.

Return to Summary Table.

Table 8-1165 DDRSS_PI_40 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20A0h
Figure 8-578 DDRSS_PI_40 Register
313029282726252423222120191817161514131211109876543210
PI_RDLVL_PAT_5
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1166 DDRSS_PI_40 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_RDLVL_PAT_5R/W0h

Non-default pattern 5 used for read data eye training of DDR4 or LPDDR4, and read dbi training of DDR4.

2.5.3.42 DDRSS_PI_41 Register (Offset = 20A4h) [reset = 0h]

DDRSS_PI_41 is shown in Figure 8-579 and described in Table 8-1168.

Return to Summary Table.

Table 8-1167 DDRSS_PI_41 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20A4h
Figure 8-579 DDRSS_PI_41 Register
313029282726252423222120191817161514131211109876543210
PI_RDLVL_PAT_6
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1168 DDRSS_PI_41 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_RDLVL_PAT_6R/W0h

Non-default pattern 6 used for read data eye training of DDR4 or LPDDR4, and read dbi training of DDR4.

2.5.3.43 DDRSS_PI_42 Register (Offset = 20A8h) [reset = 0h]

DDRSS_PI_42 is shown in Figure 8-580 and described in Table 8-1170.

Return to Summary Table.

Table 8-1169 DDRSS_PI_42 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20A8h
Figure 8-580 DDRSS_PI_42 Register
313029282726252423222120191817161514131211109876543210
PI_RDLVL_PAT_7
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1170 DDRSS_PI_42 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_RDLVL_PAT_7R/W0h

Non-default pattern 7 used for read data eye training of DDR4 or LPDDR4, and read dbi training of DDR4.

2.5.3.44 DDRSS_PI_43 Register (Offset = 20ACh) [reset = X]

DDRSS_PI_43 is shown in Figure 8-581 and described in Table 8-1172.

Return to Summary Table.

Table 8-1171 DDRSS_PI_43 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20ACh
Figure 8-581 DDRSS_PI_43 Register
3130292827262524
RESERVEDPI_RDLVL_DISABLE_DFS
R/W-XR/W-0h
2322212019181716
RESERVEDPI_RDLVL_ON_SREF_EXIT
R/W-XR/W-0h
15141312111098
RESERVEDPI_RDLVL_PERIODIC
R/W-XR/W-0h
76543210
RESERVEDPI_RDLVL_SEQ_EN
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1172 DDRSS_PI_43 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_RDLVL_DISABLE_DFSR/W0h

Disables automatic data eye training on freq change.
Set to 1 to disable rdlvl on dfs,Set to 0 to enable rdlvl on dfs.

23-17RESERVEDR/WX
16PI_RDLVL_ON_SREF_EXITR/W0h

Enables automatic data eye training on a self-refresh exit.
Set to 1 to enable.

15-9RESERVEDR/WX
8PI_RDLVL_PERIODICR/W0h

Enables the use of the dfi_lvl_periodic signal during data eye training.
Set to 1 to enable.

7-4RESERVEDR/WX
3-0PI_RDLVL_SEQ_ENR/W0h

Specifies the pattern, format and MPR for data eye training.

2.5.3.45 DDRSS_PI_44 Register (Offset = 20B0h) [reset = X]

DDRSS_PI_44 is shown in Figure 8-582 and described in Table 8-1174.

Return to Summary Table.

Table 8-1173 DDRSS_PI_44 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20B0h
Figure 8-582 DDRSS_PI_44 Register
3130292827262524
RESERVEDPI_RDLVL_ROTATE
R/W-XR/W-0h
2322212019181716
RESERVEDPI_RDLVL_GATE_DISABLE_DFS
R/W-XR/W-0h
15141312111098
RESERVEDPI_RDLVL_GATE_ON_SREF_EXIT
R/W-XR/W-0h
76543210
RESERVEDPI_RDLVL_GATE_PERIODIC
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1174 DDRSS_PI_44 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_RDLVL_ROTATER/W0h

Enables rotational CS for interval data eye training.
Set to 1 for rotating CS.

23-17RESERVEDR/WX
16PI_RDLVL_GATE_DISABLE_DFSR/W0h

Disables automatic gate training on freq change.
Set to 1 to disable rdlvl_gate on dfs,Set to 0 to enable rdlvl_gate on dfs.

15-9RESERVEDR/WX
8PI_RDLVL_GATE_ON_SREF_EXITR/W0h

Enables automatic gate training on a self-refresh exit.
Set to 1 to enable.

7-1RESERVEDR/WX
0PI_RDLVL_GATE_PERIODICR/W0h

Enables the use of the dfi_lvl_periodic signal during gate training.
Set to 1 to enable.

2.5.3.46 DDRSS_PI_45 Register (Offset = 20B4h) [reset = X]

DDRSS_PI_45 is shown in Figure 8-583 and described in Table 8-1176.

Return to Summary Table.

Table 8-1175 DDRSS_PI_45 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20B4h
Figure 8-583 DDRSS_PI_45 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDPI_RDLVL_GATE_CS_MAP
R/W-XR/W-0h
15141312111098
RESERVEDPI_RDLVL_CS_MAP
R/W-XR/W-0h
76543210
RESERVEDPI_RDLVL_GATE_ROTATE
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1176 DDRSS_PI_45 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/WX
19-16PI_RDLVL_GATE_CS_MAPR/W0h

Defines the chip select map for gate training operations.
Bit (0) controls cs0, bit (1) controls cs1, etc.
Set each bit to 1 to enable chip for gate training.

15-12RESERVEDR/WX
11-8PI_RDLVL_CS_MAPR/W0h

Defines the chip select map for data eye training operations.
Bit (0) controls cs0, bit (1) controls cs1, etc.
Set each bit to 1 to enable chip for data eye training.

7-1RESERVEDR/WX
0PI_RDLVL_GATE_ROTATER/W0h

Enables rotational CS for interval gate training.
Set to 1 for rotating CS.

2.5.3.47 DDRSS_PI_46 Register (Offset = 20B8h) [reset = X]

DDRSS_PI_46 is shown in Figure 8-584 and described in Table 8-1178.

Return to Summary Table.

Table 8-1177 DDRSS_PI_46 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20B8h
Figure 8-584 DDRSS_PI_46 Register
31302928272625242322212019181716
RESERVED
R/W-X
1514131211109876543210
RESERVEDPI_TDFI_RDLVL_RR
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1178 DDRSS_PI_46 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/WX
9-0PI_TDFI_RDLVL_RRR/W0h

Defines the DFI tRDLVL_RR timing parameter (in DFI clocks), the minimum cycles between read commands.

2.5.3.48 DDRSS_PI_47 Register (Offset = 20BCh) [reset = 0h]

DDRSS_PI_47 is shown in Figure 8-585 and described in Table 8-1180.

Return to Summary Table.

Table 8-1179 DDRSS_PI_47 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20BCh
Figure 8-585 DDRSS_PI_47 Register
313029282726252423222120191817161514131211109876543210
PI_TDFI_RDLVL_RESP
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1180 DDRSS_PI_47 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TDFI_RDLVL_RESPR/W0h

Defines the DFI tRDLVL_RESP timing parameter (in DFI clocks), the maximum cycles between a dfi_rdlvl_req or dfi_rdlvl_gate_req assertion and a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion.

2.5.3.49 DDRSS_PI_48 Register (Offset = 20C0h) [reset = X]

DDRSS_PI_48 is shown in Figure 8-586 and described in Table 8-1182.

Return to Summary Table.

Table 8-1181 DDRSS_PI_48 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20C0h
Figure 8-586 DDRSS_PI_48 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
PI_TDFI_RDLVL_EN
R/W-0h
76543210
RESERVEDPI_RDLVL_RESP_MASK
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1182 DDRSS_PI_48 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/WX
15-8PI_TDFI_RDLVL_ENR/W0h

Defines the DFI tRDLVL_EN timing parameter (in DFI clocks), the minimum cycles from a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion to the first read or MRR.
Set to 1 means the minium value(1 cycle), set to 0 means the maxium value

7-4RESERVEDR/WX
3-0PI_RDLVL_RESP_MASKR/W0h

Mask for the dfi_rdlvl_resp signal during data eye training.

2.5.3.50 DDRSS_PI_49 Register (Offset = 20C4h) [reset = 0h]

DDRSS_PI_49 is shown in Figure 8-587 and described in Table 8-1184.

Return to Summary Table.

Table 8-1183 DDRSS_PI_49 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20C4h
Figure 8-587 DDRSS_PI_49 Register
313029282726252423222120191817161514131211109876543210
PI_TDFI_RDLVL_MAX
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1184 DDRSS_PI_49 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TDFI_RDLVL_MAXR/W0h

Defines the DFI tRDLVL_MAX timing parameter (in DFI clocks), the maximum cycles between a dfi_rdlvl_en or dfi_rdlvl_gate_en assertion and a valid dfi_rdlvl_resp.

2.5.3.51 DDRSS_PI_50 Register (Offset = 20C8h) [reset = X]

DDRSS_PI_50 is shown in Figure 8-588 and described in Table 8-1186.

Return to Summary Table.

Table 8-1185 DDRSS_PI_50 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20C8h
Figure 8-588 DDRSS_PI_50 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
PI_RDLVL_INTERVAL
R/W-0h
15141312111098
PI_RDLVL_INTERVAL
R/W-0h
76543210
RESERVEDPI_RDLVL_ERROR_STATUS
R/W-XR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1186 DDRSS_PI_50 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-8PI_RDLVL_INTERVALR/W0h

Number of long count sequences counted between automatic data eye training commands.

7-1RESERVEDR/WX
0PI_RDLVL_ERROR_STATUSR0h

Holds the error associated with the data eye training error or gate training error interrupt.
Uppermost bit set indicates a TDFI_RDLVL_RESP parameter violation.
Next uppermost bit set indicates a TDFI_RDLVL_MAX parameter violation.
Lower bits are reserved.
READ-ONLY

2.5.3.52 DDRSS_PI_51 Register (Offset = 20CCh) [reset = X]

DDRSS_PI_51 is shown in Figure 8-589 and described in Table 8-1188.

Return to Summary Table.

Table 8-1187 DDRSS_PI_51 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20CCh
Figure 8-589 DDRSS_PI_51 Register
3130292827262524
RESERVEDPI_RDLVL_PATTERN_NUM
R/W-XR/W-0h
2322212019181716
RESERVEDPI_RDLVL_PATTERN_START
R/W-XR/W-0h
15141312111098
PI_RDLVL_GATE_INTERVAL
R/W-0h
76543210
PI_RDLVL_GATE_INTERVAL
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1188 DDRSS_PI_51 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_RDLVL_PATTERN_NUMR/W0h

Defines the number of pattern supported in read leveling.

23-20RESERVEDR/WX
19-16PI_RDLVL_PATTERN_STARTR/W0h

Defines the start pattern in read leveling.

15-0PI_RDLVL_GATE_INTERVALR/W0h

Number of long count sequences counted between automatic gate training commands.

2.5.3.53 DDRSS_PI_52 Register (Offset = 20D0h) [reset = X]

DDRSS_PI_52 is shown in Figure 8-590 and described in Table 8-1190.

Return to Summary Table.

Table 8-1189 DDRSS_PI_52 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20D0h
Figure 8-590 DDRSS_PI_52 Register
3130292827262524
RESERVEDPI_REG_DIMM_ENABLE
R/W-XR/W-0h
2322212019181716
RESERVEDPI_RD_PREAMBLE_TRAINING_EN
R/W-XR/W-0h
15141312111098
RESERVEDPI_RDLVL_GATE_STROBE_NUM
R/W-XR/W-0h
76543210
RESERVEDPI_RDLVL_STROBE_NUM
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1190 DDRSS_PI_52 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_REG_DIMM_ENABLER/W0h

Enable registered DIMM operation.
Set to 1 to enable.

23-17RESERVEDR/WX
16PI_RD_PREAMBLE_TRAINING_ENR/W0h

Enable read preamble training during gate training.
Set to 1 to enable.

15-13RESERVEDR/WX
12-8PI_RDLVL_GATE_STROBE_NUMR/W0h

Defines the number of back to back MPC command in one read process in read gate training.

7-5RESERVEDR/WX
4-0PI_RDLVL_STROBE_NUMR/W0h

Defines the number of back to back MPC command in one read process in read eye training.

2.5.3.54 DDRSS_PI_53 Register (Offset = 20D4h) [reset = X]

DDRSS_PI_53 is shown in Figure 8-591 and described in Table 8-1192.

Return to Summary Table.

Table 8-1191 DDRSS_PI_53 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20D4h
Figure 8-591 DDRSS_PI_53 Register
3130292827262524
RESERVEDPI_CALVL_CS
R/W-XR/W-0h
2322212019181716
RESERVEDPI_CALVL_REQ
R/W-XW-0h
15141312111098
RESERVEDPI_TDFI_PHY_WRLAT
R/W-XR-0h
76543210
RESERVEDPI_TDFI_RDDATA_EN
R/W-XR-0h
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1192 DDRSS_PI_53 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-24PI_CALVL_CSR/W0h

Specifies the target chip select for the CA training operation initiated through the CALVL_REQ parameter.

23-17RESERVEDR/WX
16PI_CALVL_REQW0h

User request to initiate CA training.
Set to 1 to trigger.
WRITE-ONLY

15RESERVEDR/WX
14-8PI_TDFI_PHY_WRLATR0h

Holds the calculated DFI tPHY_WRLAT timing parameter (in DFI PHY clocks), the maximum cycles between a write command and a dfi_wrdata_en assertion.
READ-ONLY

7RESERVEDR/WX
6-0PI_TDFI_RDDATA_ENR0h

Holds the calculated DFI tRDDATA_EN timing parameter (in DFI PHY clocks), the maximum cycles between a read command and a dfi_rddata_en assertion.
READ-ONLY

2.5.3.55 DDRSS_PI_54 Register (Offset = 20D8h) [reset = X]

DDRSS_PI_54 is shown in Figure 8-592 and described in Table 8-1194.

Return to Summary Table.

Table 8-1193 DDRSS_PI_54 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20D8h
Figure 8-592 DDRSS_PI_54 Register
3130292827262524
RESERVEDPI_CALVL_PERIODIC
R/W-XR/W-0h
2322212019181716
RESERVEDPI_CALVL_SEQ_EN
R/W-XR/W-0h
15141312111098
RESERVEDRESERVED
R/W-XR/W-0h
76543210
RESERVEDRESERVED
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1194 DDRSS_PI_54 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_CALVL_PERIODICR/W0h

Enables the use of the dfi_lvl_periodic signal during CA training.
Set to 1 to enable.

23-18RESERVEDR/WX
17-16PI_CALVL_SEQ_ENR/W0h

Specifies which CA training patterns will be used.
Set to 0 for pattern 0 only, set to 1 for patterns 0 and 1, set to 2 for patterns 0, 1 and 2, or set to 3 for all patterns.

15-12RESERVEDR/WX
11-8RESERVEDR/W0h

Reserved

7-1RESERVEDR/WX
0RESERVEDR/W0h

Reserved

2.5.3.56 DDRSS_PI_55 Register (Offset = 20DCh) [reset = X]

DDRSS_PI_55 is shown in Figure 8-593 and described in Table 8-1196.

Return to Summary Table.

Table 8-1195 DDRSS_PI_55 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20DCh
Figure 8-593 DDRSS_PI_55 Register
3130292827262524
RESERVEDPI_CALVL_CS_MAP
R/W-XR/W-0h
2322212019181716
RESERVEDPI_CALVL_ROTATE
R/W-XR/W-0h
15141312111098
RESERVEDPI_CALVL_DISABLE_DFS
R/W-XR/W-0h
76543210
RESERVEDPI_CALVL_ON_SREF_EXIT
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1196 DDRSS_PI_55 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_CALVL_CS_MAPR/W0h

Defines the chip select map for CA training operations.
Bit (0) controls cs0, bit (1) controls cs1, etc.
Set each bit to 1 to enable chip for CA training.

23-17RESERVEDR/WX
16PI_CALVL_ROTATER/W0h

Enables rotational CS for interval CA training.
Set to 1 for rotating CS.

15-9RESERVEDR/WX
8PI_CALVL_DISABLE_DFSR/W0h

Disables automatic CA training on freq change.
Set to 1 to disable CA training on dfs, Set to 0 to enable CA training .

7-1RESERVEDR/WX
0PI_CALVL_ON_SREF_EXITR/W0h

Enables automatic CA training on a self-refresh exit.
Set to 1 to enable.

2.5.3.57 DDRSS_PI_56 Register (Offset = 20E0h) [reset = X]

DDRSS_PI_56 is shown in Figure 8-594 and described in Table 8-1198.

Return to Summary Table.

Table 8-1197 DDRSS_PI_56 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20E0h
Figure 8-594 DDRSS_PI_56 Register
31302928272625242322212019181716
RESERVED
R/W-X
1514131211109876543210
RESERVEDPI_TDFI_CALVL_EN
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1198 DDRSS_PI_56 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/WX
7-0PI_TDFI_CALVL_ENR/W0h

Defines the DFI tCALVL_EN timing parameter (in DFI clocks), the minimum cycles between a dfi_calvl_en assertion and a dfi_cke de-assertion.

2.5.3.58 DDRSS_PI_57 Register (Offset = 20E4h) [reset = 0h]

DDRSS_PI_57 is shown in Figure 8-595 and described in Table 8-1200.

Return to Summary Table.

Table 8-1199 DDRSS_PI_57 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20E4h
Figure 8-595 DDRSS_PI_57 Register
313029282726252423222120191817161514131211109876543210
PI_TDFI_CALVL_RESP
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1200 DDRSS_PI_57 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TDFI_CALVL_RESPR/W0h

Defines the DFI tCALVL_RESP timing parameter (in DFI clocks), the maximum cycles between a dfi_calvl_req assertion and a dfi_calvl_en assertion.

2.5.3.59 DDRSS_PI_58 Register (Offset = 20E8h) [reset = 0h]

DDRSS_PI_58 is shown in Figure 8-596 and described in Table 8-1202.

Return to Summary Table.

Table 8-1201 DDRSS_PI_58 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20E8h
Figure 8-596 DDRSS_PI_58 Register
313029282726252423222120191817161514131211109876543210
PI_TDFI_CALVL_MAX
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1202 DDRSS_PI_58 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TDFI_CALVL_MAXR/W0h

Defines the DFI tCALVL_MAX timing parameter (in DFI clocks), the maximum cycles between a dfi_calvl_en assertion and a valid dfi_calvl_resp.

2.5.3.60 DDRSS_PI_59 Register (Offset = 20ECh) [reset = X]

DDRSS_PI_59 is shown in Figure 8-597 and described in Table 8-1204.

Return to Summary Table.

Table 8-1203 DDRSS_PI_59 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20ECh
Figure 8-597 DDRSS_PI_59 Register
3130292827262524
PI_CALVL_INTERVAL
R/W-0h
2322212019181716
PI_CALVL_INTERVAL
R/W-0h
15141312111098
RESERVEDPI_CALVL_ERROR_STATUS
R/W-XR-0h
76543210
RESERVEDPI_CALVL_RESP_MASK
R/W-XR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1204 DDRSS_PI_59 Register Field Descriptions
BitFieldTypeResetDescription
31-16PI_CALVL_INTERVALR/W0h

Number of long count sequences counted between automatic CA training commands.

15-10RESERVEDR/WX
9-8PI_CALVL_ERROR_STATUSR0h

Holds the error associated with the CA training error interrupt.
Bit (0) set indicates a TDFI_CALVL_RESP parameter violation and bit (1) set indicates a TDFI_CALVL_MAX parameter violation.
READ-ONLY

7-1RESERVEDR/WX
0PI_CALVL_RESP_MASKR/W0h

Mask for the dfi_calvl_resp signal during CA training.

2.5.3.61 DDRSS_PI_60 Register (Offset = 20F0h) [reset = X]

DDRSS_PI_60 is shown in Figure 8-598 and described in Table 8-1206.

Return to Summary Table.

Table 8-1205 DDRSS_PI_60 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20F0h
Figure 8-598 DDRSS_PI_60 Register
3130292827262524
RESERVEDPI_TCAEXT
R/W-XR/W-0h
2322212019181716
RESERVEDPI_TCACKEH
R/W-XR/W-0h
15141312111098
RESERVEDPI_TCAMRD
R/W-XR/W-0h
76543210
RESERVEDPI_TCACKEL
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1206 DDRSS_PI_60 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24PI_TCAEXTR/W0h

DRAM tCAEXT value in memory cycles.

23-21RESERVEDR/WX
20-16PI_TCACKEHR/W0h

DRAM tCACKEH value in memory cycles.

15-14RESERVEDR/WX
13-8PI_TCAMRDR/W0h

DRAM tCAMRD value in memory cycles.

7-5RESERVEDR/WX
4-0PI_TCACKELR/W0h

DRAM tCACKEL value in memory cycles.

2.5.3.62 DDRSS_PI_61 Register (Offset = 20F4h) [reset = X]

DDRSS_PI_61 is shown in Figure 8-599 and described in Table 8-1208.

Return to Summary Table.

Table 8-1207 DDRSS_PI_61 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20F4h
Figure 8-599 DDRSS_PI_61 Register
3130292827262524
PI_TDFI_INIT_START_MIN
R/W-0h
2322212019181716
RESERVEDPI_CALVL_VREF_NORMAL_STEPSIZE
R/W-XR/W-0h
15141312111098
RESERVEDPI_CALVL_VREF_INITIAL_STEPSIZE
R/W-XR/W-0h
76543210
RESERVEDPI_CA_TRAIN_VREF_EN
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1208 DDRSS_PI_61 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TDFI_INIT_START_MINR/W0h

Minimum number of DFI clocks before dfi_init_start can be driven after a previous command/training event.

23-20RESERVEDR/WX
19-16PI_CALVL_VREF_NORMAL_STEPSIZER/W0h

The adjust step for the post-initial Vref(ca) training.

15-12RESERVEDR/WX
11-8PI_CALVL_VREF_INITIAL_STEPSIZER/W0h

The adjust step for the initial Vref(ca) training.

7-1RESERVEDR/WX
0PI_CA_TRAIN_VREF_ENR/W0h

Control for VREF training during CA training post power-on initialization.
Set to enable VREF training.

2.5.3.63 DDRSS_PI_62 Register (Offset = 20F8h) [reset = X]

DDRSS_PI_62 is shown in Figure 8-600 and described in Table 8-1210.

Return to Summary Table.

Table 8-1209 DDRSS_PI_62 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20F8h
Figure 8-600 DDRSS_PI_62 Register
3130292827262524
RESERVEDPI_SW_CA_TRAIN_VREF
R/W-XR/W-0h
2322212019181716
RESERVEDPI_CALVL_STROBE_NUM
R/W-XR/W-0h
15141312111098
RESERVEDPI_TCKCKEH
R/W-XR/W-0h
76543210
PI_TDFI_INIT_COMPLETE_MIN
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1210 DDRSS_PI_62 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/WX
30-24PI_SW_CA_TRAIN_VREFR/W0h

The Vref value which is set for SW step by step CA training.

23-21RESERVEDR/WX
20-16PI_CALVL_STROBE_NUMR/W0h

The consecutive dfi_calvl_strobe number when updating the CA vref data.

15-12RESERVEDR/WX
11-8PI_TCKCKEHR/W0h

DRAM tCKELCK Clock and command valid before CKE HIGH.

7-0PI_TDFI_INIT_COMPLETE_MINR/W0h

Minimum number of DFI clocks from dfi_init_complete to a command/training event.

2.5.3.64 DDRSS_PI_63 Register (Offset = 20FCh) [reset = X]

DDRSS_PI_63 is shown in Figure 8-601 and described in Table 8-1212.

Return to Summary Table.

Table 8-1211 DDRSS_PI_63 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 20FCh
Figure 8-601 DDRSS_PI_63 Register
3130292827262524
RESERVEDPI_REFRESH_BETWEEN_SEGMENT_DISABLE
R/W-XR/W-1h
2322212019181716
RESERVEDPI_DRAM_CLK_DISABLE_DEASSERT_SEL
R/W-XR/W-0h
15141312111098
PI_INIT_STARTORCOMPLETE_2_CLKDISABLE
R/W-0h
76543210
PI_CLKDISABLE_2_INIT_START
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1212 DDRSS_PI_63 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_REFRESH_BETWEEN_SEGMENT_DISABLER/W1h

Disable the refresh between CA first and second segment training.
Set to 1 to disable.

23-17RESERVEDR/WX
16PI_DRAM_CLK_DISABLE_DEASSERT_SELR/W0h

Indicate dfi_dram_clk_disable deassert following dfi_init_start deassert or dfi_init_complete assert.
Set to
0: dfi_dram_clk_disable deassert following dfi_init_start deassert.
Set to
1: dfi_dram_clk_disable deassert following dfi_init_complete assert.

15-8PI_INIT_STARTORCOMPLETE_2_CLKDISABLER/W0h

Defines the delay from deasserting of dfi_init_start or asserting of dfi_init_complete to deasserting of dfi_dram_clk_disable in DFI clock.

7-0PI_CLKDISABLE_2_INIT_STARTR/W0h

Defines the delay from the asserting of dfi_dram_clk_disable to the asserting of dfi_init_start in DFI clock.

2.5.3.65 DDRSS_PI_64 Register (Offset = 2100h) [reset = X]

DDRSS_PI_64 is shown in Figure 8-602 and described in Table 8-1214.

Return to Summary Table.

Table 8-1213 DDRSS_PI_64 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2100h
Figure 8-602 DDRSS_PI_64 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
PI_FSM_ERROR_INFO_MASK
R/W-0h
15141312111098
PI_FSM_ERROR_INFO_MASK
R/W-0h
76543210
RESERVEDPI_MC_DFS_PI_SET_VREF_ENABLE
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1214 DDRSS_PI_64 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-8PI_FSM_ERROR_INFO_MASKR/W0h

PI FSM Error Info MASK

7-1RESERVEDR/WX
0PI_MC_DFS_PI_SET_VREF_ENABLER/W0h

Enable the PI to set VREF value after DFS issued by MC.
MR12 and MR14 for LPDDR4.
MR6 for DDR4.
1 means disable.

2.5.3.66 DDRSS_PI_65 Register (Offset = 2104h) [reset = 0h]

DDRSS_PI_65 is shown in Figure 8-603 and described in Table 8-1216.

Return to Summary Table.

Table 8-1215 DDRSS_PI_65 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2104h
Figure 8-603 DDRSS_PI_65 Register
31302928272625242322212019181716
PI_FSM_ERROR_INFO
R-0h
1514131211109876543210
PI_SC_FSM_ERROR_INFO_WOCLR
W-0h
LEGEND: R = Read Only; W = Write Only; -n = value after reset
Table 8-1216 DDRSS_PI_65 Register Field Descriptions
BitFieldTypeResetDescription
31-16PI_FSM_ERROR_INFOR0h

Gather each fsm error bit.
READ-ONLY.

15-0PI_SC_FSM_ERROR_INFO_WOCLRW0h

PI FSM Error Info.
WOCLR

2.5.3.67 DDRSS_PI_66 Register (Offset = 2108h) [reset = X]

DDRSS_PI_66 is shown in Figure 8-604 and described in Table 8-1218.

Return to Summary Table.

Table 8-1217 DDRSS_PI_66 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2108h
Figure 8-604 DDRSS_PI_66 Register
3130292827262524
RESERVEDPI_WDQLVL_ROTATE
R/W-XR/W-0h
2322212019181716
RESERVEDPI_WDQLVL_RESP_MASK
R/W-XR/W-0h
15141312111098
RESERVEDPI_WDQLVL_BST_NUM
R/W-XR/W-0h
76543210
RESERVEDPI_WDQLVL_VREF_EN
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1218 DDRSS_PI_66 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_WDQLVL_ROTATER/W0h

Enables write DQ training rotate for interval training.

23-20RESERVEDR/WX
19-16PI_WDQLVL_RESP_MASKR/W0h

Write DQ training response mask.
When set to 1, the dfi_wdqlvl_en of the slice is not asserted.

15-11RESERVEDR/WX
10-8PI_WDQLVL_BST_NUMR/W0h

Defines the number of write/read bursts issued at each step in write DQ training.

7-1RESERVEDR/WX
0PI_WDQLVL_VREF_ENR/W0h

Control for VREF training as part of non-initialization write DQ training.

2.5.3.68 DDRSS_PI_67 Register (Offset = 210Ch) [reset = X]

DDRSS_PI_67 is shown in Figure 8-605 and described in Table 8-1220.

Return to Summary Table.

Table 8-1219 DDRSS_PI_67 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 210Ch
Figure 8-605 DDRSS_PI_67 Register
3130292827262524
RESERVEDPI_WDQLVL_PERIODIC
R/W-XR/W-0h
2322212019181716
RESERVEDPI_WDQLVL_VREF_NORMAL_STEPSIZE
R/W-XR/W-0h
15141312111098
RESERVEDPI_WDQLVL_VREF_INITIAL_STEPSIZE
R/W-XR/W-0h
76543210
RESERVEDPI_WDQLVL_CS_MAP
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1220 DDRSS_PI_67 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_WDQLVL_PERIODICR/W0h

Enables periodic write DQ training.

23-21RESERVEDR/WX
20-16PI_WDQLVL_VREF_NORMAL_STEPSIZER/W0h

Write DQ training vref step size for post_initial training.

15-13RESERVEDR/WX
12-8PI_WDQLVL_VREF_INITIAL_STEPSIZER/W0h

Write DQ training vref step size for initial training.

7-4RESERVEDR/WX
3-0PI_WDQLVL_CS_MAPR/W0h

Map of CS's included in write DQ training sequence.

2.5.3.69 DDRSS_PI_68 Register (Offset = 2110h) [reset = X]

DDRSS_PI_68 is shown in Figure 8-606 and described in Table 8-1222.

Return to Summary Table.

Table 8-1221 DDRSS_PI_68 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2110h
Figure 8-606 DDRSS_PI_68 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
PI_TDFI_WDQLVL_EN
R/W-0h
15141312111098
RESERVEDPI_WDQLVL_CS
R/W-XR/W-0h
76543210
RESERVEDPI_WDQLVL_REQ
R/W-XW-0h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1222 DDRSS_PI_68 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-16PI_TDFI_WDQLVL_ENR/W0h

DFI timing param tWDQLVL_EN.
Minimum number of DFI clocks required after the write DQ training enable signal is asserted until the first write command may be asserted.

15-10RESERVEDR/WX
9-8PI_WDQLVL_CSR/W0h

Write DQ training target chip select.

7-1RESERVEDR/WX
0PI_WDQLVL_REQW0h

SW write to initiate Write DQ training request.
WRITE-ONLY

2.5.3.70 DDRSS_PI_69 Register (Offset = 2114h) [reset = 0h]

DDRSS_PI_69 is shown in Figure 8-607 and described in Table 8-1224.

Return to Summary Table.

Table 8-1223 DDRSS_PI_69 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2114h
Figure 8-607 DDRSS_PI_69 Register
313029282726252423222120191817161514131211109876543210
PI_TDFI_WDQLVL_RESP
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1224 DDRSS_PI_69 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TDFI_WDQLVL_RESPR/W0h

DFI timing param tWDQLVL_RESP.
Maximum number of DFI clocks that may occur between a write DQ training request and the associated mode enable.

2.5.3.71 DDRSS_PI_70 Register (Offset = 2118h) [reset = 0h]

DDRSS_PI_70 is shown in Figure 8-608 and described in Table 8-1226.

Return to Summary Table.

Table 8-1225 DDRSS_PI_70 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2118h
Figure 8-608 DDRSS_PI_70 Register
313029282726252423222120191817161514131211109876543210
PI_TDFI_WDQLVL_MAX
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1226 DDRSS_PI_70 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TDFI_WDQLVL_MAXR/W0h

DFI timing param tWDQLVL_MAX.
Maximum number of DFI clocks that the PI will wait for a response from the PHY.

2.5.3.72 DDRSS_PI_71 Register (Offset = 211Ch) [reset = X]

DDRSS_PI_71 is shown in Figure 8-609 and described in Table 8-1228.

Return to Summary Table.

Table 8-1227 DDRSS_PI_71 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 211Ch
Figure 8-609 DDRSS_PI_71 Register
3130292827262524
RESERVEDPI_WDQLVL_DISABLE_DFS
R/W-XR/W-0h
2322212019181716
RESERVEDPI_WDQLVL_ON_SREF_EXIT
R/W-XR/W-0h
15141312111098
PI_WDQLVL_INTERVAL
R/W-0h
76543210
PI_WDQLVL_INTERVAL
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1228 DDRSS_PI_71 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_WDQLVL_DISABLE_DFSR/W0h

Disable automatic write DQ training on freq change.
Set to 1 to disable.

23-17RESERVEDR/WX
16PI_WDQLVL_ON_SREF_EXITR/W0h

Issue a write DQ training command on self-refresh exit.

15-0PI_WDQLVL_INTERVALR/W0h

Sets the maximum number of long count sequences allowed between automatic write DQ training operations.

2.5.3.73 DDRSS_PI_72 Register (Offset = 2120h) [reset = X]

DDRSS_PI_72 is shown in Figure 8-610 and described in Table 8-1230.

Return to Summary Table.

Table 8-1229 DDRSS_PI_72 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2120h
Figure 8-610 DDRSS_PI_72 Register
3130292827262524
RESERVEDPI_PARALLEL_WDQLVL_EN
R/W-XR/W-0h
2322212019181716
RESERVEDPI_DQS_OSC_PERIOD_EN
R/W-XR/W-0h
15141312111098
RESERVEDPI_WDQLVL_OSC_EN
R/W-XR/W-0h
76543210
RESERVEDPI_WDQLVL_ERROR_STATUS
R/W-XR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1230 DDRSS_PI_72 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_PARALLEL_WDQLVL_ENR/W0h

Enable per rank parallel Write DQ training for LPDDR4,
1 = enabled.

23-17RESERVEDR/WX
16PI_DQS_OSC_PERIOD_ENR/W0h

Enable for DQS oscillator triggered periodic write DQ training,
1 = enabled.

15-9RESERVEDR/WX
8PI_WDQLVL_OSC_ENR/W0h

Enable for DQS oscillator triggered write DQ training,
1 = enabled.

7-2RESERVEDR/WX
1-0PI_WDQLVL_ERROR_STATUSR0h

Holds the error associated with the write dq level error interrupt.
Bit (0) set indicates a PI_TDFI_WDQLVL_MAX parameter violation and bit (1) set indicates a PI_TDFI_WDQLVL_RESP parameter violation.
READ-ONLY.

2.5.3.74 DDRSS_PI_73 Register (Offset = 2124h) [reset = X]

DDRSS_PI_73 is shown in Figure 8-611 and described in Table 8-1232.

Return to Summary Table.

Table 8-1231 DDRSS_PI_73 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2124h
Figure 8-611 DDRSS_PI_73 Register
3130292827262524
RESERVEDRESERVED
R/W-XR/W-0h
2322212019181716
RESERVEDPI_TCCD
R/W-XR/W-0h
15141312111098
RESERVEDPI_ROW_DIFF
R/W-XR/W-0h
76543210
RESERVEDPI_BANK_DIFF
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1232 DDRSS_PI_73 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24RESERVEDR/W0h

Reserved

23-21RESERVEDR/WX
20-16PI_TCCDR/W0h

DRAM CAS-to-CAS value in cycles.

15-11RESERVEDR/WX
10-8PI_ROW_DIFFR/W0h

Difference between number of address pins available and number being used.

7-2RESERVEDR/WX
1-0PI_BANK_DIFFR/W0h

Difference between number of bank pins available and number being used.

2.5.3.75 DDRSS_PI_74 Register (Offset = 2128h) [reset = X]

DDRSS_PI_74 is shown in Figure 8-612 and described in Table 8-1234.

Return to Summary Table.

Table 8-1233 DDRSS_PI_74 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2128h
Figure 8-612 DDRSS_PI_74 Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-XR/W-2hR/W-XR/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-XR/W-2hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1234 DDRSS_PI_74 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24RESERVEDR/W2h

Reserved

23-20RESERVEDR/WX
19-16RESERVEDR/W0h

Reserved

15-12RESERVEDR/WX
11-8RESERVEDR/W2h

Reserved

7-4RESERVEDR/WX
3-0RESERVEDR/W0h

Reserved

2.5.3.76 DDRSS_PI_75 Register (Offset = 212Ch) [reset = X]

DDRSS_PI_75 is shown in Figure 8-613 and described in Table 8-1236.

Return to Summary Table.

Table 8-1235 DDRSS_PI_75 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 212Ch
Figure 8-613 DDRSS_PI_75 Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-XR/W-1hR/W-XR/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-XR/W-1hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1236 DDRSS_PI_75 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24RESERVEDR/W1h

Reserved

23-20RESERVEDR/WX
19-16RESERVEDR/W0h

Reserved

15-12RESERVEDR/WX
11-8RESERVEDR/W1h

Reserved

7-4RESERVEDR/WX
3-0RESERVEDR/W0h

Reserved

2.5.3.77 DDRSS_PI_76 Register (Offset = 2130h) [reset = X]

DDRSS_PI_76 is shown in Figure 8-614 and described in Table 8-1238.

Return to Summary Table.

Table 8-1237 DDRSS_PI_76 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2130h
Figure 8-614 DDRSS_PI_76 Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-XR/W-1hR/W-XR/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1238 DDRSS_PI_76 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24RESERVEDR/W1h

Reserved

23-20RESERVEDR/WX
19-16RESERVEDR/W0h

Reserved

15-12RESERVEDR/WX
11-8RESERVEDR/W0h

Reserved

7-4RESERVEDR/WX
3-0RESERVEDR/W0h

Reserved

2.5.3.78 DDRSS_PI_77 Register (Offset = 2134h) [reset = X]

DDRSS_PI_77 is shown in Figure 8-615 and described in Table 8-1240.

Return to Summary Table.

Table 8-1239 DDRSS_PI_77 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2134h
Figure 8-615 DDRSS_PI_77 Register
31302928272625242322212019181716
RESERVEDRESERVEDRESERVEDRESERVED
R/W-XR/W-2hR/W-XR/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-XR/W-2hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1240 DDRSS_PI_77 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24RESERVEDR/W2h

Reserved

23-20RESERVEDR/WX
19-16RESERVEDR/W0h

Reserved

15-12RESERVEDR/WX
11-8RESERVEDR/W2h

Reserved

7-4RESERVEDR/WX
3-0RESERVEDR/W0h

Reserved

2.5.3.79 DDRSS_PI_78 Register (Offset = 2138h) [reset = X]

DDRSS_PI_78 is shown in Figure 8-616 and described in Table 8-1242.

Return to Summary Table.

Table 8-1241 DDRSS_PI_78 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2138h
Figure 8-616 DDRSS_PI_78 Register
31302928272625242322212019181716
RESERVEDRESERVED
R/W-XR/W-0h
1514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVED
R/W-XR/W-2hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1242 DDRSS_PI_78 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/WX
19-16RESERVEDR/W0h

Reserved

15-12RESERVEDR/WX
11-8RESERVEDR/W2h

Reserved

7-4RESERVEDR/WX
3-0RESERVEDR/W0h

Reserved

2.5.3.80 DDRSS_PI_79 Register (Offset = 213Ch) [reset = X]

DDRSS_PI_79 is shown in Figure 8-617 and described in Table 8-1244.

Return to Summary Table.

Table 8-1243 DDRSS_PI_79 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 213Ch
Figure 8-617 DDRSS_PI_79 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_INT_STATUS
R-XR-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1244 DDRSS_PI_79 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDRX
27-0PI_INT_STATUSR0h

Status of interrupt features in the PI.
READ-ONLY

2.5.3.81 DDRSS_PI_80 Register (Offset = 2140h) [reset = X]

DDRSS_PI_80 is shown in Figure 8-618 and described in Table 8-1246.

Return to Summary Table.

Table 8-1245 DDRSS_PI_80 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2140h
Figure 8-618 DDRSS_PI_80 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_INT_ACK
W-XW-0h
LEGEND: W = Write Only; -n = value after reset
Table 8-1246 DDRSS_PI_80 Register Field Descriptions
BitFieldTypeResetDescription
31-27RESERVEDWX
26-0PI_INT_ACKW0h

Clear the corresponding interrupt bit of the PI_INT_STATUS parameter.
WRITE-ONLY

2.5.3.82 DDRSS_PI_81 Register (Offset = 2144h) [reset = X]

DDRSS_PI_81 is shown in Figure 8-619 and described in Table 8-1248.

Return to Summary Table.

Table 8-1247 DDRSS_PI_81 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2144h
Figure 8-619 DDRSS_PI_81 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_INT_MASK
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1248 DDRSS_PI_81 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-0PI_INT_MASKR/W0h

Mask for PI_int signals from the PI_INT_STATUS parameter.

2.5.3.83 DDRSS_PI_82 Register (Offset = 2148h) [reset = 0h]

DDRSS_PI_82 is shown in Figure 8-620 and described in Table 8-1250.

Return to Summary Table.

Table 8-1249 DDRSS_PI_82 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2148h
Figure 8-620 DDRSS_PI_82 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_EXP_DATA_0
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1250 DDRSS_PI_82 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_EXP_DATA_0R0h

Expected data on BIST error.
READ-ONLY

2.5.3.84 DDRSS_PI_83 Register (Offset = 214Ch) [reset = 0h]

DDRSS_PI_83 is shown in Figure 8-621 and described in Table 8-1252.

Return to Summary Table.

Table 8-1251 DDRSS_PI_83 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 214Ch
Figure 8-621 DDRSS_PI_83 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_EXP_DATA_1
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1252 DDRSS_PI_83 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_EXP_DATA_1R0h

Expected data on BIST error.
READ-ONLY

2.5.3.85 DDRSS_PI_84 Register (Offset = 2150h) [reset = 0h]

DDRSS_PI_84 is shown in Figure 8-622 and described in Table 8-1254.

Return to Summary Table.

Table 8-1253 DDRSS_PI_84 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2150h
Figure 8-622 DDRSS_PI_84 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_EXP_DATA_2
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1254 DDRSS_PI_84 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_EXP_DATA_2R0h

Expected data on BIST error.
READ-ONLY

2.5.3.86 DDRSS_PI_85 Register (Offset = 2154h) [reset = 0h]

DDRSS_PI_85 is shown in Figure 8-623 and described in Table 8-1256.

Return to Summary Table.

Table 8-1255 DDRSS_PI_85 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2154h
Figure 8-623 DDRSS_PI_85 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_EXP_DATA_3
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1256 DDRSS_PI_85 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_EXP_DATA_3R0h

Expected data on BIST error.
READ-ONLY

2.5.3.87 DDRSS_PI_86 Register (Offset = 2158h) [reset = 0h]

DDRSS_PI_86 is shown in Figure 8-624 and described in Table 8-1258.

Return to Summary Table.

Table 8-1257 DDRSS_PI_86 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2158h
Figure 8-624 DDRSS_PI_86 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_FAIL_DATA_0
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1258 DDRSS_PI_86 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_FAIL_DATA_0R0h

Actual data on BIST error.
READ-ONLY

2.5.3.88 DDRSS_PI_87 Register (Offset = 215Ch) [reset = 0h]

DDRSS_PI_87 is shown in Figure 8-625 and described in Table 8-1260.

Return to Summary Table.

Table 8-1259 DDRSS_PI_87 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 215Ch
Figure 8-625 DDRSS_PI_87 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_FAIL_DATA_1
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1260 DDRSS_PI_87 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_FAIL_DATA_1R0h

Actual data on BIST error.
READ-ONLY

2.5.3.89 DDRSS_PI_88 Register (Offset = 2160h) [reset = 0h]

DDRSS_PI_88 is shown in Figure 8-626 and described in Table 8-1262.

Return to Summary Table.

Table 8-1261 DDRSS_PI_88 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2160h
Figure 8-626 DDRSS_PI_88 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_FAIL_DATA_2
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1262 DDRSS_PI_88 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_FAIL_DATA_2R0h

Actual data on BIST error.
READ-ONLY

2.5.3.90 DDRSS_PI_89 Register (Offset = 2164h) [reset = 0h]

DDRSS_PI_89 is shown in Figure 8-627 and described in Table 8-1264.

Return to Summary Table.

Table 8-1263 DDRSS_PI_89 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2164h
Figure 8-627 DDRSS_PI_89 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_FAIL_DATA_3
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1264 DDRSS_PI_89 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_FAIL_DATA_3R0h

Actual data on BIST error.
READ-ONLY

2.5.3.91 DDRSS_PI_90 Register (Offset = 2168h) [reset = 0h]

DDRSS_PI_90 is shown in Figure 8-628 and described in Table 8-1266.

Return to Summary Table.

Table 8-1265 DDRSS_PI_90 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2168h
Figure 8-628 DDRSS_PI_90 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_FAIL_ADDR_0
R-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1266 DDRSS_PI_90 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_FAIL_ADDR_0R0h

The burst aligned address of BIST error.
READ-ONLY

2.5.3.92 DDRSS_PI_91 Register (Offset = 216Ch) [reset = X]

DDRSS_PI_91 is shown in Figure 8-629 and described in Table 8-1268.

Return to Summary Table.

Table 8-1267 DDRSS_PI_91 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 216Ch
Figure 8-629 DDRSS_PI_91 Register
3130292827262524
RESERVEDPI_CMD_SWAP_EN
R/W-XR/W-0h
2322212019181716
RESERVEDPI_LONG_COUNT_MASK
R/W-XR/W-0h
15141312111098
RESERVEDPI_BSTLEN
R/W-XR/W-2h
76543210
RESERVEDPI_BIST_FAIL_ADDR_1
R/W-XR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1268 DDRSS_PI_91 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_CMD_SWAP_ENR/W0h

Command pin swap function enable

23-21RESERVEDR/WX
20-16PI_LONG_COUNT_MASKR/W0h

Reduces the length of the long counter from 1024 cycles.

15-13RESERVEDR/WX
12-8PI_BSTLENR/W2h

Encoded burst length sent to DRAMs during initialization.

7-3RESERVEDR/WX
2-0PI_BIST_FAIL_ADDR_1R0h

The burst aligned address of BIST error.
READ-ONLY

2.5.3.93 DDRSS_PI_92 Register (Offset = 2170h) [reset = X]

DDRSS_PI_92 is shown in Figure 8-630 and described in Table 8-1270.

Return to Summary Table.

Table 8-1269 DDRSS_PI_92 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2170h
Figure 8-630 DDRSS_PI_92 Register
3130292827262524
RESERVEDPI_DATA_BYTE_SWAP_SLICE2
R/W-XR/W-0h
2322212019181716
RESERVEDPI_DATA_BYTE_SWAP_SLICE1
R/W-XR/W-0h
15141312111098
RESERVEDPI_DATA_BYTE_SWAP_SLICE0
R/W-XR/W-0h
76543210
RESERVEDPI_DATA_BYTE_SWAP_EN
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1270 DDRSS_PI_92 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-24PI_DATA_BYTE_SWAP_SLICE2R/W0h

DATA pin 2 mux selector

23-18RESERVEDR/WX
17-16PI_DATA_BYTE_SWAP_SLICE1R/W0h

DATA pin 1 mux selector

15-10RESERVEDR/WX
9-8PI_DATA_BYTE_SWAP_SLICE0R/W0h

DATA pin 0 mux selector

7-1RESERVEDR/WX
0PI_DATA_BYTE_SWAP_ENR/W0h

DATA pin swap function enable

2.5.3.94 DDRSS_PI_93 Register (Offset = 2174h) [reset = X]

DDRSS_PI_93 is shown in Figure 8-631 and described in Table 8-1272.

Return to Summary Table.

Table 8-1271 DDRSS_PI_93 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2174h
Figure 8-631 DDRSS_PI_93 Register
3130292827262524
RESERVEDPI_UPDATE_ERROR_STATUS
R/W-XR-0h
2322212019181716
PI_TDFI_CTRLUPD_MIN
R/W-0h
15141312111098
RESERVEDPI_CTRLUPD_REQ_PER_AREF_EN
R/W-XR/W-0h
76543210
RESERVEDPI_DATA_BYTE_SWAP_SLICE3
R/W-XR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1272 DDRSS_PI_93 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-24PI_UPDATE_ERROR_STATUSR0h

Identifies the source of any DFI PI-initiated update errors.
Value of 1 indicates a timing violation of the associated timing parameter.
Bit
1-
0: ctrlupd_max_error, ctrlupd_interval_error.
Bit
6-
2: reserved.
READ-ONLY

23-16PI_TDFI_CTRLUPD_MINR/W0h

Reports the DFI tCTRLUPD_MIN timing parameter (in DFI clocks), the minimum cycles that dfi_ctrlupd_req must be asserted.

15-9RESERVEDR/WX
8PI_CTRLUPD_REQ_PER_AREF_ENR/W0h

Enable an automatic PI initiated update (dfi_ctrlupd_req) after every refresh.
Set to 1 to enable.

7-2RESERVEDR/WX
1-0PI_DATA_BYTE_SWAP_SLICE3R/W0h

DATA pin 3 mux selector

2.5.3.95 DDRSS_PI_94 Register (Offset = 2178h) [reset = X]

DDRSS_PI_94 is shown in Figure 8-632 and described in Table 8-1274.

Return to Summary Table.

Table 8-1273 DDRSS_PI_94 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2178h
Figure 8-632 DDRSS_PI_94 Register
3130292827262524
RESERVEDPI_BIST_DATA_CHECK
R/W-XR/W-0h
2322212019181716
RESERVEDPI_ADDR_SPACE
R/W-XR/W-0h
15141312111098
RESERVEDPI_BIST_RESULT
R/W-XR-0h
76543210
RESERVEDPI_BIST_GO
R/W-XR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1274 DDRSS_PI_94 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_BIST_DATA_CHECKR/W0h

Enable data checking with BIST operation.
Set to 1 to enable.

23-22RESERVEDR/WX
21-16PI_ADDR_SPACER/W0h

Sets the number of address bits to check during BIST operation.
The end address of BIST is start_address+(1 shifted up by PI_ADDR_SPACE)-1.
The end address should not beyond the actual memory address range.

15-10RESERVEDR/WX
9-8PI_BIST_RESULTR0h

BIST operation status (pass/fail).
Bit (0) indicates data check status and bit (1) indicates address check status.
Value of 1 is a passing result.
READ-ONLY

7-1RESERVEDR/WX
0PI_BIST_GOR/W0h

Initiate a BIST operation.
Set to 1 to trigger.

2.5.3.96 DDRSS_PI_95 Register (Offset = 217Ch) [reset = X]

DDRSS_PI_95 is shown in Figure 8-633 and described in Table 8-1276.

Return to Summary Table.

Table 8-1275 DDRSS_PI_95 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 217Ch
Figure 8-633 DDRSS_PI_95 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPI_BIST_ADDR_CHECK
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1276 DDRSS_PI_95 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/WX
0PI_BIST_ADDR_CHECKR/W0h

Enable address checking with BIST operation.
Set to 1 to enable.

2.5.3.97 DDRSS_PI_96 Register (Offset = 2180h) [reset = 0h]

DDRSS_PI_96 is shown in Figure 8-634 and described in Table 8-1278.

Return to Summary Table.

Table 8-1277 DDRSS_PI_96 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2180h
Figure 8-634 DDRSS_PI_96 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_START_ADDRESS_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1278 DDRSS_PI_96 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_START_ADDRESS_0R/W0h

Start BIST checking at this address.

2.5.3.98 DDRSS_PI_97 Register (Offset = 2184h) [reset = X]

DDRSS_PI_97 is shown in Figure 8-635 and described in Table 8-1280.

Return to Summary Table.

Table 8-1279 DDRSS_PI_97 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2184h
Figure 8-635 DDRSS_PI_97 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
PI_MBIST_INIT_PATTERN
R/W-0h
76543210
RESERVEDPI_BIST_START_ADDRESS_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1280 DDRSS_PI_97 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/WX
15-8PI_MBIST_INIT_PATTERNR/W0h

PI mbist data check, random lfsr pattern mode init pattern seed.

7-3RESERVEDR/WX
2-0PI_BIST_START_ADDRESS_1R/W0h

Start BIST checking at this address.

2.5.3.99 DDRSS_PI_98 Register (Offset = 2188h) [reset = 0h]

DDRSS_PI_98 is shown in Figure 8-636 and described in Table 8-1282.

Return to Summary Table.

Table 8-1281 DDRSS_PI_98 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2188h
Figure 8-636 DDRSS_PI_98 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_DATA_MASK_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1282 DDRSS_PI_98 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_DATA_MASK_0R/W0h

Mask applied to data for BIST error checking.
Bit (0) controls memory data path bit (0), bit (1) controls memory data path bit (1), etc.
The mask range is the data transfer size in each memory clock cycle (The data on a rising edge and a failing edge).
Set each bit to 1 to mask.

2.5.3.100 DDRSS_PI_99 Register (Offset = 218Ch) [reset = 0h]

DDRSS_PI_99 is shown in Figure 8-637 and described in Table 8-1284.

Return to Summary Table.

Table 8-1283 DDRSS_PI_99 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 218Ch
Figure 8-637 DDRSS_PI_99 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_DATA_MASK_1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1284 DDRSS_PI_99 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_DATA_MASK_1R/W0h

Mask applied to data for BIST error checking.
Bit (0) controls memory data path bit (0), bit (1) controls memory data path bit (1), etc.
The mask range is the data transfer size in each memory clock cycle (The data on a rising edge and a failing edge).
Set each bit to 1 to mask.

2.5.3.101 DDRSS_PI_100 Register (Offset = 2190h) [reset = X]

DDRSS_PI_100 is shown in Figure 8-638 and described in Table 8-1286.

Return to Summary Table.

Table 8-1285 DDRSS_PI_100 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2190h
Figure 8-638 DDRSS_PI_100 Register
31302928272625242322212019181716
RESERVEDPI_BIST_ERR_STOP
R/W-XR/W-0h
1514131211109876543210
RESERVEDPI_BIST_ERR_COUNT
R/W-XR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1286 DDRSS_PI_100 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-16PI_BIST_ERR_STOPR/W0h

Defines the maximum number of error occurrences allowed prior to quitting when the BIST_TEST_MODE parameter is set to 1, 2 or 3.
A value of 0 will allow the test to run to completion.

15-12RESERVEDR/WX
11-0PI_BIST_ERR_COUNTR0h

Indicates the number of BIST errors found when the BIST_TEST_MODE parameter is set to 1, 2 or 3.
READ-ONLY

2.5.3.102 DDRSS_PI_101 Register (Offset = 2194h) [reset = 0h]

DDRSS_PI_101 is shown in Figure 8-639 and described in Table 8-1288.

Return to Summary Table.

Table 8-1287 DDRSS_PI_101 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2194h
Figure 8-639 DDRSS_PI_101 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_ADDR_MASK_0_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1288 DDRSS_PI_101 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_ADDR_MASK_0_0R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.103 DDRSS_PI_102 Register (Offset = 2198h) [reset = X]

DDRSS_PI_102 is shown in Figure 8-640 and described in Table 8-1290.

Return to Summary Table.

Table 8-1289 DDRSS_PI_102 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2198h
Figure 8-640 DDRSS_PI_102 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPI_BIST_ADDR_MASK_0_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1290 DDRSS_PI_102 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/WX
3-0PI_BIST_ADDR_MASK_0_1R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.104 DDRSS_PI_103 Register (Offset = 219Ch) [reset = 0h]

DDRSS_PI_103 is shown in Figure 8-641 and described in Table 8-1292.

Return to Summary Table.

Table 8-1291 DDRSS_PI_103 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 219Ch
Figure 8-641 DDRSS_PI_103 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_ADDR_MASK_1_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1292 DDRSS_PI_103 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_ADDR_MASK_1_0R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.105 DDRSS_PI_104 Register (Offset = 21A0h) [reset = X]

DDRSS_PI_104 is shown in Figure 8-642 and described in Table 8-1294.

Return to Summary Table.

Table 8-1293 DDRSS_PI_104 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21A0h
Figure 8-642 DDRSS_PI_104 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPI_BIST_ADDR_MASK_1_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1294 DDRSS_PI_104 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/WX
3-0PI_BIST_ADDR_MASK_1_1R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.106 DDRSS_PI_105 Register (Offset = 21A4h) [reset = 0h]

DDRSS_PI_105 is shown in Figure 8-643 and described in Table 8-1296.

Return to Summary Table.

Table 8-1295 DDRSS_PI_105 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21A4h
Figure 8-643 DDRSS_PI_105 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_ADDR_MASK_2_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1296 DDRSS_PI_105 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_ADDR_MASK_2_0R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.107 DDRSS_PI_106 Register (Offset = 21A8h) [reset = X]

DDRSS_PI_106 is shown in Figure 8-644 and described in Table 8-1298.

Return to Summary Table.

Table 8-1297 DDRSS_PI_106 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21A8h
Figure 8-644 DDRSS_PI_106 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPI_BIST_ADDR_MASK_2_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1298 DDRSS_PI_106 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/WX
3-0PI_BIST_ADDR_MASK_2_1R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.108 DDRSS_PI_107 Register (Offset = 21ACh) [reset = 0h]

DDRSS_PI_107 is shown in Figure 8-645 and described in Table 8-1300.

Return to Summary Table.

Table 8-1299 DDRSS_PI_107 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21ACh
Figure 8-645 DDRSS_PI_107 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_ADDR_MASK_3_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1300 DDRSS_PI_107 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_ADDR_MASK_3_0R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.109 DDRSS_PI_108 Register (Offset = 21B0h) [reset = X]

DDRSS_PI_108 is shown in Figure 8-646 and described in Table 8-1302.

Return to Summary Table.

Table 8-1301 DDRSS_PI_108 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21B0h
Figure 8-646 DDRSS_PI_108 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPI_BIST_ADDR_MASK_3_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1302 DDRSS_PI_108 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/WX
3-0PI_BIST_ADDR_MASK_3_1R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.110 DDRSS_PI_109 Register (Offset = 21B4h) [reset = 0h]

DDRSS_PI_109 is shown in Figure 8-647 and described in Table 8-1304.

Return to Summary Table.

Table 8-1303 DDRSS_PI_109 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21B4h
Figure 8-647 DDRSS_PI_109 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_ADDR_MASK_4_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1304 DDRSS_PI_109 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_ADDR_MASK_4_0R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.111 DDRSS_PI_110 Register (Offset = 21B8h) [reset = X]

DDRSS_PI_110 is shown in Figure 8-648 and described in Table 8-1306.

Return to Summary Table.

Table 8-1305 DDRSS_PI_110 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21B8h
Figure 8-648 DDRSS_PI_110 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPI_BIST_ADDR_MASK_4_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1306 DDRSS_PI_110 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/WX
3-0PI_BIST_ADDR_MASK_4_1R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.112 DDRSS_PI_111 Register (Offset = 21BCh) [reset = 0h]

DDRSS_PI_111 is shown in Figure 8-649 and described in Table 8-1308.

Return to Summary Table.

Table 8-1307 DDRSS_PI_111 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21BCh
Figure 8-649 DDRSS_PI_111 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_ADDR_MASK_5_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1308 DDRSS_PI_111 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_ADDR_MASK_5_0R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.113 DDRSS_PI_112 Register (Offset = 21C0h) [reset = X]

DDRSS_PI_112 is shown in Figure 8-650 and described in Table 8-1310.

Return to Summary Table.

Table 8-1309 DDRSS_PI_112 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21C0h
Figure 8-650 DDRSS_PI_112 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPI_BIST_ADDR_MASK_5_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1310 DDRSS_PI_112 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/WX
3-0PI_BIST_ADDR_MASK_5_1R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.114 DDRSS_PI_113 Register (Offset = 21C4h) [reset = 0h]

DDRSS_PI_113 is shown in Figure 8-651 and described in Table 8-1312.

Return to Summary Table.

Table 8-1311 DDRSS_PI_113 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21C4h
Figure 8-651 DDRSS_PI_113 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_ADDR_MASK_6_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1312 DDRSS_PI_113 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_ADDR_MASK_6_0R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.115 DDRSS_PI_114 Register (Offset = 21C8h) [reset = X]

DDRSS_PI_114 is shown in Figure 8-652 and described in Table 8-1314.

Return to Summary Table.

Table 8-1313 DDRSS_PI_114 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21C8h
Figure 8-652 DDRSS_PI_114 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPI_BIST_ADDR_MASK_6_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1314 DDRSS_PI_114 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/WX
3-0PI_BIST_ADDR_MASK_6_1R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.116 DDRSS_PI_115 Register (Offset = 21CCh) [reset = 0h]

DDRSS_PI_115 is shown in Figure 8-653 and described in Table 8-1316.

Return to Summary Table.

Table 8-1315 DDRSS_PI_115 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21CCh
Figure 8-653 DDRSS_PI_115 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_ADDR_MASK_7_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1316 DDRSS_PI_115 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_ADDR_MASK_7_0R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.117 DDRSS_PI_116 Register (Offset = 21D0h) [reset = X]

DDRSS_PI_116 is shown in Figure 8-654 and described in Table 8-1318.

Return to Summary Table.

Table 8-1317 DDRSS_PI_116 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21D0h
Figure 8-654 DDRSS_PI_116 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPI_BIST_ADDR_MASK_7_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1318 DDRSS_PI_116 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/WX
3-0PI_BIST_ADDR_MASK_7_1R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.118 DDRSS_PI_117 Register (Offset = 21D4h) [reset = 0h]

DDRSS_PI_117 is shown in Figure 8-655 and described in Table 8-1320.

Return to Summary Table.

Table 8-1319 DDRSS_PI_117 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21D4h
Figure 8-655 DDRSS_PI_117 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_ADDR_MASK_8_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1320 DDRSS_PI_117 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_ADDR_MASK_8_0R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.119 DDRSS_PI_118 Register (Offset = 21D8h) [reset = X]

DDRSS_PI_118 is shown in Figure 8-656 and described in Table 8-1322.

Return to Summary Table.

Table 8-1321 DDRSS_PI_118 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21D8h
Figure 8-656 DDRSS_PI_118 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPI_BIST_ADDR_MASK_8_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1322 DDRSS_PI_118 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/WX
3-0PI_BIST_ADDR_MASK_8_1R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.120 DDRSS_PI_119 Register (Offset = 21DCh) [reset = 0h]

DDRSS_PI_119 is shown in Figure 8-657 and described in Table 8-1324.

Return to Summary Table.

Table 8-1323 DDRSS_PI_119 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21DCh
Figure 8-657 DDRSS_PI_119 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_ADDR_MASK_9_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1324 DDRSS_PI_119 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_ADDR_MASK_9_0R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.121 DDRSS_PI_120 Register (Offset = 21E0h) [reset = X]

DDRSS_PI_120 is shown in Figure 8-658 and described in Table 8-1326.

Return to Summary Table.

Table 8-1325 DDRSS_PI_120 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21E0h
Figure 8-658 DDRSS_PI_120 Register
3130292827262524
RESERVEDPI_BIST_PAT_MODE
R/W-XR/W-0h
2322212019181716
RESERVEDPI_BIST_ADDR_MODE
R/W-XR/W-0h
15141312111098
RESERVEDPI_BIST_MODE
R/W-XR/W-0h
76543210
RESERVEDPI_BIST_ADDR_MASK_9_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1326 DDRSS_PI_120 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-24PI_BIST_PAT_MODER/W0h

Sets the pattern mode of BIST.
'b00 indicates using built-in pattern.
'b01 indicates checkerboard pattern, each data transfer inverts the last data transfer based on the built-in pattern.
'b10 indicates using both user pattern and built-in pattern.
'b11 indicates using pi lfsr random pattern.

23-18RESERVEDR/WX
17-16PI_BIST_ADDR_MODER/W0h

Sets the address traversing order of BIST.
'b00 indicates fast column order (burst-column-bank-row-rank).
'b01 indicates fast row order (burst-row-column-bank-rank).
'b10 indicates fast bank order (burst-bank-column-row-rank).

15-11RESERVEDR/WX
10-8PI_BIST_MODER/W0h

Sets the BIST data checking mode.
'b00 indicates MOVI13N mode.
'b01 indicates March C mode.
'b10 indicates GALPAT mode.
'b11 indicates PRBS mode.
'b100 indicates programmable March data check mode.

7-4RESERVEDR/WX
3-0PI_BIST_ADDR_MASK_9_1R/W0h

Defines an address to be masked during the BIST operation..

2.5.3.122 DDRSS_PI_121 Register (Offset = 21E4h) [reset = 0h]

DDRSS_PI_121 is shown in Figure 8-659 and described in Table 8-1328.

Return to Summary Table.

Table 8-1327 DDRSS_PI_121 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21E4h
Figure 8-659 DDRSS_PI_121 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_USER_PAT_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1328 DDRSS_PI_121 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_USER_PAT_0R/W0h

Sets the user-specified pattern of BIST.

2.5.3.123 DDRSS_PI_122 Register (Offset = 21E8h) [reset = 0h]

DDRSS_PI_122 is shown in Figure 8-660 and described in Table 8-1330.

Return to Summary Table.

Table 8-1329 DDRSS_PI_122 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21E8h
Figure 8-660 DDRSS_PI_122 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_USER_PAT_1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1330 DDRSS_PI_122 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_USER_PAT_1R/W0h

Sets the user-specified pattern of BIST.

2.5.3.124 DDRSS_PI_123 Register (Offset = 21ECh) [reset = 0h]

DDRSS_PI_123 is shown in Figure 8-661 and described in Table 8-1332.

Return to Summary Table.

Table 8-1331 DDRSS_PI_123 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21ECh
Figure 8-661 DDRSS_PI_123 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_USER_PAT_2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1332 DDRSS_PI_123 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_USER_PAT_2R/W0h

Sets the user-specified pattern of BIST.

2.5.3.125 DDRSS_PI_124 Register (Offset = 21F0h) [reset = 0h]

DDRSS_PI_124 is shown in Figure 8-662 and described in Table 8-1334.

Return to Summary Table.

Table 8-1333 DDRSS_PI_124 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21F0h
Figure 8-662 DDRSS_PI_124 Register
313029282726252423222120191817161514131211109876543210
PI_BIST_USER_PAT_3
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1334 DDRSS_PI_124 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_BIST_USER_PAT_3R/W0h

Sets the user-specified pattern of BIST.

2.5.3.126 DDRSS_PI_125 Register (Offset = 21F4h) [reset = X]

DDRSS_PI_125 is shown in Figure 8-663 and described in Table 8-1336.

Return to Summary Table.

Table 8-1335 DDRSS_PI_125 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21F4h
Figure 8-663 DDRSS_PI_125 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPI_BIST_PAT_NUM
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1336 DDRSS_PI_125 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR/WX
3-0PI_BIST_PAT_NUMR/W0h

Sets the max used pattern number of BIST from a total of 8 built-in patterns.
Ex.
set to 3, The BIST would use pattern 1, 2 and 3.

2.5.3.127 DDRSS_PI_126 Register (Offset = 21F8h) [reset = X]

DDRSS_PI_126 is shown in Figure 8-664 and described in Table 8-1338.

Return to Summary Table.

Table 8-1337 DDRSS_PI_126 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21F8h
Figure 8-664 DDRSS_PI_126 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_BIST_STAGE_0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1338 DDRSS_PI_126 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/WX
29-0PI_BIST_STAGE_0R/W0h

Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4.

2.5.3.128 DDRSS_PI_127 Register (Offset = 21FCh) [reset = X]

DDRSS_PI_127 is shown in Figure 8-665 and described in Table 8-1340.

Return to Summary Table.

Table 8-1339 DDRSS_PI_127 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 21FCh
Figure 8-665 DDRSS_PI_127 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_BIST_STAGE_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1340 DDRSS_PI_127 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/WX
29-0PI_BIST_STAGE_1R/W0h

Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4.

2.5.3.129 DDRSS_PI_128 Register (Offset = 2200h) [reset = X]

DDRSS_PI_128 is shown in Figure 8-666 and described in Table 8-1342.

Return to Summary Table.

Table 8-1341 DDRSS_PI_128 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2200h
Figure 8-666 DDRSS_PI_128 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_BIST_STAGE_2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1342 DDRSS_PI_128 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/WX
29-0PI_BIST_STAGE_2R/W0h

Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4.

2.5.3.130 DDRSS_PI_129 Register (Offset = 2204h) [reset = X]

DDRSS_PI_129 is shown in Figure 8-667 and described in Table 8-1344.

Return to Summary Table.

Table 8-1343 DDRSS_PI_129 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2204h
Figure 8-667 DDRSS_PI_129 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_BIST_STAGE_3
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1344 DDRSS_PI_129 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/WX
29-0PI_BIST_STAGE_3R/W0h

Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4.

2.5.3.131 DDRSS_PI_130 Register (Offset = 2208h) [reset = X]

DDRSS_PI_130 is shown in Figure 8-668 and described in Table 8-1346.

Return to Summary Table.

Table 8-1345 DDRSS_PI_130 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2208h
Figure 8-668 DDRSS_PI_130 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_BIST_STAGE_4
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1346 DDRSS_PI_130 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/WX
29-0PI_BIST_STAGE_4R/W0h

Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4.

2.5.3.132 DDRSS_PI_131 Register (Offset = 220Ch) [reset = X]

DDRSS_PI_131 is shown in Figure 8-669 and described in Table 8-1348.

Return to Summary Table.

Table 8-1347 DDRSS_PI_131 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 220Ch
Figure 8-669 DDRSS_PI_131 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_BIST_STAGE_5
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1348 DDRSS_PI_131 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/WX
29-0PI_BIST_STAGE_5R/W0h

Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4.

2.5.3.133 DDRSS_PI_132 Register (Offset = 2210h) [reset = X]

DDRSS_PI_132 is shown in Figure 8-670 and described in Table 8-1350.

Return to Summary Table.

Table 8-1349 DDRSS_PI_132 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2210h
Figure 8-670 DDRSS_PI_132 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_BIST_STAGE_6
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1350 DDRSS_PI_132 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/WX
29-0PI_BIST_STAGE_6R/W0h

Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4.

2.5.3.134 DDRSS_PI_133 Register (Offset = 2214h) [reset = X]

DDRSS_PI_133 is shown in Figure 8-671 and described in Table 8-1352.

Return to Summary Table.

Table 8-1351 DDRSS_PI_133 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2214h
Figure 8-671 DDRSS_PI_133 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_BIST_STAGE_7
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1352 DDRSS_PI_133 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/WX
29-0PI_BIST_STAGE_7R/W0h

Sets the programmable algorithm of each stage X when pi_bist_mmode = 'h4.

2.5.3.135 DDRSS_PI_134 Register (Offset = 2218h) [reset = X]

DDRSS_PI_134 is shown in Figure 8-672 and described in Table 8-1354.

Return to Summary Table.

Table 8-1353 DDRSS_PI_134 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2218h
Figure 8-672 DDRSS_PI_134 Register
3130292827262524
RESERVEDPI_SREFRESH_EXIT_NO_REFRESH
R/W-XR/W-0h
2322212019181716
RESERVEDPI_PWRUP_SREFRESH_EXIT
R/W-XR/W-0h
15141312111098
RESERVEDPI_SELF_REFRESH_EN
R/W-XR/W-0h
76543210
RESERVEDPI_COL_DIFF
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1354 DDRSS_PI_134 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_SREFRESH_EXIT_NO_REFRESHR/W0h

Disables the automatic refresh request associated with self-refresh exit.
Set to 1 to disable.

23-17RESERVEDR/WX
16PI_PWRUP_SREFRESH_EXITR/W0h

Allow powerup via self-refresh instead of full memory initialization.
Set to 1 to enable.

15-9RESERVEDR/WX
8PI_SELF_REFRESH_ENR/W0h

Control for PI to enable self refresh mode.
Set to 1 to enable.

7-4RESERVEDR/WX
3-0PI_COL_DIFFR/W0h

Difference between number of column pins available and number being used.

2.5.3.136 DDRSS_PI_135 Register (Offset = 221Ch) [reset = X]

DDRSS_PI_135 is shown in Figure 8-673 and described in Table 8-1356.

Return to Summary Table.

Table 8-1355 DDRSS_PI_135 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 221Ch
Figure 8-673 DDRSS_PI_135 Register
3130292827262524
RESERVEDPI_NO_PHY_IND_TRAIN_INIT
R/W-XR/W-0h
2322212019181716
RESERVEDPI_NO_MRW_INIT
R/W-XR/W-0h
15141312111098
RESERVEDPI_NO_MRW_BT_INIT
R/W-XR/W-0h
76543210
RESERVEDPI_SREF_ENTRY_REQ
R/W-XW-0h
LEGEND: R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1356 DDRSS_PI_135 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_NO_PHY_IND_TRAIN_INITR/W0h

Disable PHY Independent Training during initialization.
Set to 1 to disable.

23-17RESERVEDR/WX
16PI_NO_MRW_INITR/W0h

Disable MRW commands after training during initialization.
Set to 1 to disable.

15-9RESERVEDR/WX
8PI_NO_MRW_BT_INITR/W0h

Disable MRW commands before training during initialization.
Set to 1 to disable.

7-1RESERVEDR/WX
0PI_SREF_ENTRY_REQW0h

In PI power up data retention, PI can issued sref entry command.
WRITE-ONLY

2.5.3.137 DDRSS_PI_136 Register (Offset = 2220h) [reset = X]

DDRSS_PI_136 is shown in Figure 8-674 and described in Table 8-1358.

Return to Summary Table.

Table 8-1357 DDRSS_PI_136 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2220h
Figure 8-674 DDRSS_PI_136 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPI_NO_AUTO_MRR_INIT
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1358 DDRSS_PI_136 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/WX
0PI_NO_AUTO_MRR_INITR/W0h

Disable MRR commands during initialization.
Set to 1 to disable.

2.5.3.138 DDRSS_PI_137 Register (Offset = 2224h) [reset = 0h]

DDRSS_PI_137 is shown in Figure 8-675 and described in Table 8-1360.

Return to Summary Table.

Table 8-1359 DDRSS_PI_137 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2224h
Figure 8-675 DDRSS_PI_137 Register
313029282726252423222120191817161514131211109876543210
PI_TRST_PWRON
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1360 DDRSS_PI_137 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TRST_PWRONR/W0h

Duration of memory reset during power-on initialization.

2.5.3.139 DDRSS_PI_138 Register (Offset = 2228h) [reset = 0h]

DDRSS_PI_138 is shown in Figure 8-676 and described in Table 8-1362.

Return to Summary Table.

Table 8-1361 DDRSS_PI_138 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2228h
Figure 8-676 DDRSS_PI_138 Register
313029282726252423222120191817161514131211109876543210
PI_CKE_INACTIVE
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1362 DDRSS_PI_138 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_CKE_INACTIVER/W0h

Number of cycles after reset before CKE will be active.

2.5.3.140 DDRSS_PI_139 Register (Offset = 222Ch) [reset = X]

DDRSS_PI_139 is shown in Figure 8-677 and described in Table 8-1364.

Return to Summary Table.

Table 8-1363 DDRSS_PI_139 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 222Ch
Figure 8-677 DDRSS_PI_139 Register
3130292827262524
PI_DLL_RST_DELAY
R/W-0h
2322212019181716
PI_DLL_RST_DELAY
R/W-0h
15141312111098
RESERVEDPI_DRAM_INIT_EN
R/W-XR/W-0h
76543210
RESERVEDPI_DLL_RST
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1364 DDRSS_PI_139 Register Field Descriptions
BitFieldTypeResetDescription
31-16PI_DLL_RST_DELAYR/W0h

Minimum cycles required for DLL reset signal dll_rst_n to be held.

15-9RESERVEDR/WX
8PI_DRAM_INIT_ENR/W0h

Control for the initialization of DRAM by the PI.

7-1RESERVEDR/WX
0PI_DLL_RSTR/W0h

Enables use of the DLL reset (dll_rst_n).

2.5.3.141 DDRSS_PI_140 Register (Offset = 2230h) [reset = X]

DDRSS_PI_140 is shown in Figure 8-678 and described in Table 8-1366.

Return to Summary Table.

Table 8-1365 DDRSS_PI_140 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2230h
Figure 8-678 DDRSS_PI_140 Register
31302928272625242322212019181716
RESERVED
R/W-X
1514131211109876543210
RESERVEDPI_DLL_RST_ADJ_DLY
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1366 DDRSS_PI_140 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/WX
7-0PI_DLL_RST_ADJ_DLYR/W0h

Minimum cycles after setting master delay in DLL until the DLL reset signal dll_rst_n may be asserted.

2.5.3.142 DDRSS_PI_141 Register (Offset = 2234h) [reset = X]

DDRSS_PI_141 is shown in Figure 8-679 and described in Table 8-1368.

Return to Summary Table.

Table 8-1367 DDRSS_PI_141 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2234h
Figure 8-679 DDRSS_PI_141 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_WRITE_MODEREG
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1368 DDRSS_PI_141 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-0PI_WRITE_MODEREGR/W0h

Write memory mode register data to the DRAMs.
Bits (
7:0) define the memory mode register number if bit (23) is set, bits (
15:8) define the chip select if bit (24) is clear, bits (
23:16) define which memory mode register/s to write, bit (24) defines whether all chip selects will be written, and bit (25) triggers the write.

2.5.3.143 DDRSS_PI_142 Register (Offset = 2238h) [reset = X]

DDRSS_PI_142 is shown in Figure 8-680 and described in Table 8-1370.

Return to Summary Table.

Table 8-1369 DDRSS_PI_142 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2238h
Figure 8-680 DDRSS_PI_142 Register
31302928272625242322212019181716
RESERVEDPI_READ_MODEREG
R/W-XR/W-0h
1514131211109876543210
PI_READ_MODEREGPI_MRW_STATUS
R/W-0hR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1370 DDRSS_PI_142 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24-8PI_READ_MODEREGR/W0h

Read the specified memory mode register from specified chip when start bit set.
Bits (
7:0) define the memory mode register and bits (
15:8) define the chip select.
Set bit (16) to 1 to trigger.

7-0PI_MRW_STATUSR0h

Write memory mode register status.
Bit (0) set indicates a WRITE_MODEREG parameter programming error.
Bit (1) set indicates a PASR error.
Bit (2) is Reserved.
Bit (3) set indicates a self refresh or deep power down error.
Bit (4) set indicates that a write to MR3 or MR11 was attempted (write_modereg bit (25) was asserted with bit (17) set, or bit (23) was asserted with bits (
7:0) defining MR3 or MR11) during tZQCAL after a ZQ calibration start command.
READ-ONLY

2.5.3.144 DDRSS_PI_143 Register (Offset = 223Ch) [reset = X]

DDRSS_PI_143 is shown in Figure 8-681 and described in Table 8-1372.

Return to Summary Table.

Table 8-1371 DDRSS_PI_143 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 223Ch
Figure 8-681 DDRSS_PI_143 Register
3130292827262524
RESERVEDPI_NO_ZQ_INIT
R/W-XR/W-0h
2322212019181716
PI_PERIPHERAL_MRR_DATA_0
R-0h
15141312111098
PI_PERIPHERAL_MRR_DATA_0
R-0h
76543210
PI_PERIPHERAL_MRR_DATA_0
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1372 DDRSS_PI_143 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_NO_ZQ_INITR/W0h

Disable ZQ operations during initialization.
Set to 1 to disable.

23-0PI_PERIPHERAL_MRR_DATA_0R0h

Data and chip returned from memory mode register read requested by the READ_MODEREG parameter, Bits (
15:0) indicate the MRR data, (
23:16) indicate the chip select.
READ-ONLY

2.5.3.145 DDRSS_PI_144 Register (Offset = 2240h) [reset = X]

DDRSS_PI_144 is shown in Figure 8-682 and described in Table 8-1374.

Return to Summary Table.

Table 8-1373 DDRSS_PI_144 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2240h
Figure 8-682 DDRSS_PI_144 Register
3130292827262524
RESERVEDRESERVED
R/W-XR/W-0h
2322212019181716
RESERVEDPI_ZQ_REQ_PENDING
R/W-XR-0h
15141312111098
RESERVEDRESERVED
R/W-XW-0h
76543210
RESERVEDRESERVED
R/W-XR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; W = Write Only; -n = value after reset
Table 8-1374 DDRSS_PI_144 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24RESERVEDR/W0h

Reserved

23-17RESERVEDR/WX
16PI_ZQ_REQ_PENDINGR0h

Indicates that a ZQ command is currently in progress or waiting to run.
When this is asserted, no writes to ZQ_REQ should occur.
READ-ONLY

15-12RESERVEDR/WX
11-8RESERVEDW0h

Reserved

7-4RESERVEDR/WX
3-0RESERVEDR/W0h

Reserved

2.5.3.146 DDRSS_PI_145 Register (Offset = 2244h) [reset = X]

DDRSS_PI_145 is shown in Figure 8-683 and described in Table 8-1376.

Return to Summary Table.

Table 8-1375 DDRSS_PI_145 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2244h
Figure 8-683 DDRSS_PI_145 Register
3130292827262524
PI_MONITOR_0
R-0h
2322212019181716
RESERVEDPI_MONITOR_CAP_SEL_0
R/W-XR/W-0h
15141312111098
RESERVEDPI_MONITOR_SRC_SEL_0
R/W-XR/W-0h
76543210
RESERVEDRESERVED
R/W-XR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1376 DDRSS_PI_145 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MONITOR_0R0h

Monitor register 0.
READ-ONLY.

23-17RESERVEDR/WX
16PI_MONITOR_CAP_SEL_0R/W0h

Selection of captures for pi_monitor_0.

15-12RESERVEDR/WX
11-8PI_MONITOR_SRC_SEL_0R/W0h

Selection of sources for pi_monitor_0.

7-3RESERVEDR/WX
2-0RESERVEDR/W0h

Reserved

2.5.3.147 DDRSS_PI_146 Register (Offset = 2248h) [reset = X]

DDRSS_PI_146 is shown in Figure 8-684 and described in Table 8-1378.

Return to Summary Table.

Table 8-1377 DDRSS_PI_146 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2248h
Figure 8-684 DDRSS_PI_146 Register
3130292827262524
RESERVEDPI_MONITOR_SRC_SEL_2
R/W-XR/W-0h
2322212019181716
PI_MONITOR_1
R-0h
15141312111098
RESERVEDPI_MONITOR_CAP_SEL_1
R/W-XR/W-0h
76543210
RESERVEDPI_MONITOR_SRC_SEL_1
R/W-XR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1378 DDRSS_PI_146 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_MONITOR_SRC_SEL_2R/W0h

Selection of sources for pi_monitor_2.

23-16PI_MONITOR_1R0h

Monitor register 1.
READ-ONLY.

15-9RESERVEDR/WX
8PI_MONITOR_CAP_SEL_1R/W0h

Selection of captures for pi_monitor_1.

7-4RESERVEDR/WX
3-0PI_MONITOR_SRC_SEL_1R/W0h

Selection of sources for pi_monitor_1.

2.5.3.148 DDRSS_PI_147 Register (Offset = 224Ch) [reset = X]

DDRSS_PI_147 is shown in Figure 8-685 and described in Table 8-1380.

Return to Summary Table.

Table 8-1379 DDRSS_PI_147 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 224Ch
Figure 8-685 DDRSS_PI_147 Register
3130292827262524
RESERVEDPI_MONITOR_CAP_SEL_3
R/W-XR/W-0h
2322212019181716
RESERVEDPI_MONITOR_SRC_SEL_3
R/W-XR/W-0h
15141312111098
PI_MONITOR_2
R-0h
76543210
RESERVEDPI_MONITOR_CAP_SEL_2
R/W-XR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1380 DDRSS_PI_147 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_MONITOR_CAP_SEL_3R/W0h

Selection of captures for pi_monitor_3.

23-20RESERVEDR/WX
19-16PI_MONITOR_SRC_SEL_3R/W0h

Selection of sources for pi_monitor_3.

15-8PI_MONITOR_2R0h

Monitor register 2.
READ-ONLY.

7-1RESERVEDR/WX
0PI_MONITOR_CAP_SEL_2R/W0h

Selection of captures for pi_monitor_2.

2.5.3.149 DDRSS_PI_148 Register (Offset = 2250h) [reset = X]

DDRSS_PI_148 is shown in Figure 8-686 and described in Table 8-1382.

Return to Summary Table.

Table 8-1381 DDRSS_PI_148 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2250h
Figure 8-686 DDRSS_PI_148 Register
3130292827262524
PI_MONITOR_4
R-0h
2322212019181716
RESERVEDPI_MONITOR_CAP_SEL_4
R/W-XR/W-0h
15141312111098
RESERVEDPI_MONITOR_SRC_SEL_4
R/W-XR/W-0h
76543210
PI_MONITOR_3
R-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1382 DDRSS_PI_148 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MONITOR_4R0h

Monitor register 4.
READ-ONLY.

23-17RESERVEDR/WX
16PI_MONITOR_CAP_SEL_4R/W0h

Selection of captures for pi_monitor_4.

15-12RESERVEDR/WX
11-8PI_MONITOR_SRC_SEL_4R/W0h

Selection of sources for pi_monitor_4.

7-0PI_MONITOR_3R0h

Monitor register 3.
READ-ONLY.

2.5.3.150 DDRSS_PI_149 Register (Offset = 2254h) [reset = X]

DDRSS_PI_149 is shown in Figure 8-687 and described in Table 8-1384.

Return to Summary Table.

Table 8-1383 DDRSS_PI_149 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2254h
Figure 8-687 DDRSS_PI_149 Register
3130292827262524
RESERVEDPI_MONITOR_SRC_SEL_6
R/W-XR/W-0h
2322212019181716
PI_MONITOR_5
R-0h
15141312111098
RESERVEDPI_MONITOR_CAP_SEL_5
R/W-XR/W-0h
76543210
RESERVEDPI_MONITOR_SRC_SEL_5
R/W-XR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1384 DDRSS_PI_149 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_MONITOR_SRC_SEL_6R/W0h

Selection of sources for pi_monitor_6.

23-16PI_MONITOR_5R0h

Monitor register 5.
READ-ONLY.

15-9RESERVEDR/WX
8PI_MONITOR_CAP_SEL_5R/W0h

Selection of captures for pi_monitor_5.

7-4RESERVEDR/WX
3-0PI_MONITOR_SRC_SEL_5R/W0h

Selection of sources for pi_monitor_5.

2.5.3.151 DDRSS_PI_150 Register (Offset = 2258h) [reset = X]

DDRSS_PI_150 is shown in Figure 8-688 and described in Table 8-1386.

Return to Summary Table.

Table 8-1385 DDRSS_PI_150 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2258h
Figure 8-688 DDRSS_PI_150 Register
3130292827262524
RESERVEDPI_MONITOR_CAP_SEL_7
R/W-XR/W-0h
2322212019181716
RESERVEDPI_MONITOR_SRC_SEL_7
R/W-XR/W-0h
15141312111098
PI_MONITOR_6
R-0h
76543210
RESERVEDPI_MONITOR_CAP_SEL_6
R/W-XR/W-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1386 DDRSS_PI_150 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_MONITOR_CAP_SEL_7R/W0h

Selection of captures for pi_monitor_7.

23-20RESERVEDR/WX
19-16PI_MONITOR_SRC_SEL_7R/W0h

Selection of sources for pi_monitor_7.

15-8PI_MONITOR_6R0h

Monitor register 6.
READ-ONLY.

7-1RESERVEDR/WX
0PI_MONITOR_CAP_SEL_6R/W0h

Selection of captures for pi_monitor_6.

2.5.3.152 DDRSS_PI_151 Register (Offset = 225Ch) [reset = X]

DDRSS_PI_151 is shown in Figure 8-689 and described in Table 8-1388.

Return to Summary Table.

Table 8-1387 DDRSS_PI_151 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 225Ch
Figure 8-689 DDRSS_PI_151 Register
31302928272625242322212019181716
RESERVED
R-X
1514131211109876543210
RESERVEDPI_MONITOR_7
R-XR-0h
LEGEND: R = Read Only; -n = value after reset
Table 8-1388 DDRSS_PI_151 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDRX
7-0PI_MONITOR_7R0h

Monitor register 7.
READ-ONLY.

2.5.3.153 DDRSS_PI_152 Register (Offset = 2260h) [reset = X]

DDRSS_PI_152 is shown in Figure 8-690 and described in Table 8-1390.

Return to Summary Table.

Table 8-1389 DDRSS_PI_152 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2260h
Figure 8-690 DDRSS_PI_152 Register
31302928272625242322212019181716
RESERVED
W-X
1514131211109876543210
RESERVEDPI_MONITOR_STROBE
W-XW-0h
LEGEND: W = Write Only; -n = value after reset
Table 8-1390 DDRSS_PI_152 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDWX
7-0PI_MONITOR_STROBEW0h

Strobe the pi_monitor once.
Every bit corresponds respectively with a pi_monitor.
WRITE-ONLY

2.5.3.154 DDRSS_PI_153 Register (Offset = 2264h) [reset = X]

DDRSS_PI_153 is shown in Figure 8-691 and described in Table 8-1392.

Return to Summary Table.

Table 8-1391 DDRSS_PI_153 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2264h
Figure 8-691 DDRSS_PI_153 Register
3130292827262524
RESERVEDRESERVED
R/W-XR/W-0h
2322212019181716
RESERVEDPI_FREQ_RETENTION_NUM
R/W-XR/W-0h
15141312111098
RESERVEDPI_FREQ_NUMBER_STATUS
R/W-XR-0h
76543210
RESERVEDPI_DLL_LOCK
R/W-XR-0h
LEGEND: R = Read Only; R/W = Read/Write; -n = value after reset
Table 8-1392 DDRSS_PI_153 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24RESERVEDR/W0h

Reserved

23-21RESERVEDR/WX
20-16PI_FREQ_RETENTION_NUMR/W0h

Monitor active freq number in PI for data_retention

15-13RESERVEDR/WX
12-8PI_FREQ_NUMBER_STATUSR0h

Monitor active freq number in PI.
READ-ONLY.

7-1RESERVEDR/WX
0PI_DLL_LOCKR0h

Monitor dfi_init_complete from PHY.
READ-ONLY.

2.5.3.155 DDRSS_PI_154 Register (Offset = 2268h) [reset = X]

DDRSS_PI_154 is shown in Figure 8-692 and described in Table 8-1394.

Return to Summary Table.

Table 8-1393 DDRSS_PI_154 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2268h
Figure 8-692 DDRSS_PI_154 Register
3130292827262524
RESERVEDRESERVED
R/W-XR/W-0h
2322212019181716
RESERVEDPI_POWER_REDUC_EN
R/W-XR/W-0h
15141312111098
RESERVEDRESERVED
R/W-XR/W-0h
76543210
RESERVEDPI_PHYMSTR_TYPE
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1394 DDRSS_PI_154 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24RESERVEDR/W0h

Reserved

23-17RESERVEDR/WX
16PI_POWER_REDUC_ENR/W0h

PI Power reduction enable,
1 = enabled.

15-9RESERVEDR/WX
8RESERVEDR/W0h

Reserved

7-2RESERVEDR/WX
1-0PI_PHYMSTR_TYPER/W0h

Defines how the controller should set the state of DRAM before turning control of the DFI bus over to the PI.

2.5.3.156 DDRSS_PI_155 Register (Offset = 226Ch) [reset = X]

DDRSS_PI_155 is shown in Figure 8-693 and described in Table 8-1396.

Return to Summary Table.

Table 8-1395 DDRSS_PI_155 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 226Ch
Figure 8-693 DDRSS_PI_155 Register
3130292827262524
RESERVEDRESERVED
R/W-XR/W-0h
2322212019181716
RESERVEDRESERVED
R/W-XR/W-0h
15141312111098
RESERVEDRESERVED
R/W-XR/W-0h
76543210
RESERVEDRESERVED
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1396 DDRSS_PI_155 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24RESERVEDR/W0h

Reserved

23-17RESERVEDR/WX
16RESERVEDR/W0h

Reserved

15-9RESERVEDR/WX
8RESERVEDR/W0h

Reserved

7-1RESERVEDR/WX
0RESERVEDR/W0h

Reserved

2.5.3.157 DDRSS_PI_156 Register (Offset = 2270h) [reset = X]

DDRSS_PI_156 is shown in Figure 8-694 and described in Table 8-1398.

Return to Summary Table.

Table 8-1397 DDRSS_PI_156 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2270h
Figure 8-694 DDRSS_PI_156 Register
3130292827262524
RESERVEDRESERVED
R/W-XR/W-0h
2322212019181716
RESERVEDRESERVED
R/W-XR/W-0h
15141312111098
RESERVEDRESERVED
R/W-XR/W-0h
76543210
RESERVEDRESERVED
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1398 DDRSS_PI_156 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24RESERVEDR/W0h

Reserved

23-17RESERVEDR/WX
16RESERVEDR/W0h

Reserved

15-9RESERVEDR/WX
8RESERVEDR/W0h

Reserved

7-1RESERVEDR/WX
0RESERVEDR/W0h

Reserved

2.5.3.158 DDRSS_PI_157 Register (Offset = 2274h) [reset = X]

DDRSS_PI_157 is shown in Figure 8-695 and described in Table 8-1400.

Return to Summary Table.

Table 8-1399 DDRSS_PI_157 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2274h
Figure 8-695 DDRSS_PI_157 Register
3130292827262524
RESERVEDRESERVED
R/W-XR/W-0h
2322212019181716
RESERVEDRESERVED
R/W-XR/W-0h
15141312111098
RESERVEDRESERVED
R/W-XR/W-0h
76543210
RESERVEDRESERVED
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1400 DDRSS_PI_157 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24RESERVEDR/W0h

Reserved

23-17RESERVEDR/WX
16RESERVEDR/W0h

Reserved

15-9RESERVEDR/WX
8RESERVEDR/W0h

Reserved

7-1RESERVEDR/WX
0RESERVEDR/W0h

Reserved

2.5.3.159 DDRSS_PI_158 Register (Offset = 2278h) [reset = X]

DDRSS_PI_158 is shown in Figure 8-696 and described in Table 8-1402.

Return to Summary Table.

Table 8-1401 DDRSS_PI_158 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2278h
Figure 8-696 DDRSS_PI_158 Register
3130292827262524
RESERVEDRESERVED
R/W-XR/W-0h
2322212019181716
RESERVEDRESERVED
R/W-XR/W-0h
15141312111098
RESERVEDRESERVED
R/W-XR/W-0h
76543210
RESERVEDRESERVED
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1402 DDRSS_PI_158 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24RESERVEDR/W0h

Reserved

23-17RESERVEDR/WX
16RESERVEDR/W0h

Reserved

15-9RESERVEDR/WX
8RESERVEDR/W0h

Reserved

7-1RESERVEDR/WX
0RESERVEDR/W0h

Reserved

2.5.3.160 DDRSS_PI_159 Register (Offset = 227Ch) [reset = X]

DDRSS_PI_159 is shown in Figure 8-697 and described in Table 8-1404.

Return to Summary Table.

Table 8-1403 DDRSS_PI_159 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 227Ch
Figure 8-697 DDRSS_PI_159 Register
31302928272625242322212019181716
RESERVEDPI_TREFBW_THR
R/W-XR/W-0h
1514131211109876543210
PI_TREFBW_THRPI_WRLVL_MAX_STROBE_PEND
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1404 DDRSS_PI_159 Register Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR/WX
16-8PI_TREFBW_THRR/W0h

Threshold value to control the AREF command interval.
When the number of pending AREF is over this value, the interval is expanded to be tREF/8.

7-0PI_WRLVL_MAX_STROBE_PENDR/W0h

Defines the maximum number of wrlvl_strobes that be accumulated before an AREF is prevented from being generated.

2.5.3.161 DDRSS_PI_160 Register (Offset = 2280h) [reset = X]

DDRSS_PI_160 is shown in Figure 8-698 and described in Table 8-1406.

Return to Summary Table.

Table 8-1405 DDRSS_PI_160 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2280h
Figure 8-698 DDRSS_PI_160 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
RESERVEDPI_FREQ_CHANGE_REG_COPY
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1406 DDRSS_PI_160 Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR/WX
4-0PI_FREQ_CHANGE_REG_COPYR/W0h

In non-DFI 4.0 mode, contains the frequency copy value.

2.5.3.162 DDRSS_PI_161 Register (Offset = 2284h) [reset = X]

DDRSS_PI_161 is shown in Figure 8-699 and described in Table 8-1408.

Return to Summary Table.

Table 8-1407 DDRSS_PI_161 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2284h
Figure 8-699 DDRSS_PI_161 Register
3130292827262524
RESERVEDPI_CATR
R/W-XR/W-0h
2322212019181716
RESERVEDPI_PARALLEL_CALVL_EN
R/W-XR/W-0h
15141312111098
RESERVEDRESERVED
R/W-XR/W-0h
76543210
RESERVEDPI_FREQ_SEL_FROM_REGIF
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1408 DDRSS_PI_161 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_CATRR/W0h

It indicates LP4 DRAM CA terminition ON/OFF state.
Each bit corresponds to each chip select.
1:ON
0:OFF.
This parameter is active when PI_NO_CATR_READ==1.
When PI_NO_CATR_READ==0, this param is inactive

23-17RESERVEDR/WX
16PI_PARALLEL_CALVL_ENR/W0h

Enable parallel channel CA training for LPDDR4.
1: All the channels in one rank do CA Training in parallel.
0: Each channel does CA Training in sequence

15-13RESERVEDR/WX
12-8RESERVEDR/W0h

Reserved

7-1RESERVEDR/WX
0PI_FREQ_SEL_FROM_REGIFR/W0h

In non-DFI 4.0 mode, user select the frequency copies from pi_freq_change_reg_copy.

2.5.3.163 DDRSS_PI_162 Register (Offset = 2288h) [reset = X]

DDRSS_PI_162 is shown in Figure 8-700 and described in Table 8-1410.

Return to Summary Table.

Table 8-1409 DDRSS_PI_162 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2288h
Figure 8-700 DDRSS_PI_162 Register
3130292827262524
RESERVEDPI_NOTCARE_MC_INIT_START
R/W-XR/W-0h
2322212019181716
RESERVEDPI_DISCONNECT_MC
R/W-XR/W-0h
15141312111098
RESERVEDPI_MASK_INIT_COMPLETE
R/W-XR/W-0h
76543210
RESERVEDPI_NO_CATR_READ
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1410 DDRSS_PI_162 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_NOTCARE_MC_INIT_STARTR/W0h

Defines whether PI waits for the controller to initiate dfi_init_start before PI memory initialization,
1: wait for dfi_init_start

23-17RESERVEDR/WX
16PI_DISCONNECT_MCR/W0h

PI disconnects the controller from the PHY,
1: disconnect

15-9RESERVEDR/WX
8PI_MASK_INIT_COMPLETER/W0h

Enable the masking of the dfi_init_complete signal back to the controller,
1: mask.

7-1RESERVEDR/WX
0PI_NO_CATR_READR/W0h

Defines how the LPDDR4 termination status is determined.
1: PI use PI_CATR to get DRAM CA Termination status.
0: PI reads DRAM MR0.OP7 to get DRAM CA Termination status.

2.5.3.164 DDRSS_PI_163 Register (Offset = 228Ch) [reset = X]

DDRSS_PI_163 is shown in Figure 8-701 and described in Table 8-1412.

Return to Summary Table.

Table 8-1411 DDRSS_PI_163 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 228Ch
Figure 8-701 DDRSS_PI_163 Register
3130292827262524
PI_TSDO_F2
R/W-0h
2322212019181716
PI_TSDO_F1
R/W-0h
15141312111098
PI_TSDO_F0
R/W-0h
76543210
RESERVEDPI_TRACE_MC_MR13
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1412 DDRSS_PI_163 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TSDO_F2R/W0h

The delay from the read preamble training MRS command to the data strobe drive out for frequency set 2, in PI clocks

23-16PI_TSDO_F1R/W0h

The delay from the read preamble training MRS command to the data strobe drive out for frequency set 1, in PI clocks

15-8PI_TSDO_F0R/W0h

The delay from the read preamble training MRS command to the data strobe drive out for frequency set 0, in PI clocks

7-1RESERVEDR/WX
0PI_TRACE_MC_MR13R/W0h

Defines whether PI monitors controller mr13 mrw or not.
1: monitor mc mr13 mrw and update the op7 and op6 in PI_MR13_DATA.

2.5.3.165 DDRSS_PI_164 Register (Offset = 2290h) [reset = X]

DDRSS_PI_164 is shown in Figure 8-702 and described in Table 8-1414.

Return to Summary Table.

Table 8-1413 DDRSS_PI_164 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2290h
Figure 8-702 DDRSS_PI_164 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
PI_TDELAY_RDWR_2_BUS_IDLE_F0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1414 DDRSS_PI_164 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/WX
7-0PI_TDELAY_RDWR_2_BUS_IDLE_F0R/W0h

The delay from read or write to bus idle for frequency set 0.
Recommend setting is: delay time from read command issued to last read data received.

2.5.3.166 DDRSS_PI_165 Register (Offset = 2294h) [reset = X]

DDRSS_PI_165 is shown in Figure 8-703 and described in Table 8-1416.

Return to Summary Table.

Table 8-1415 DDRSS_PI_165 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2294h
Figure 8-703 DDRSS_PI_165 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
RESERVED
R/W-X
76543210
PI_TDELAY_RDWR_2_BUS_IDLE_F1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1416 DDRSS_PI_165 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR/WX
7-0PI_TDELAY_RDWR_2_BUS_IDLE_F1R/W0h

The delay from read or write to bus idle for frequency set 1.
Recommend setting is: delay time from read command issued to last read data received.

2.5.3.167 DDRSS_PI_166 Register (Offset = 2298h) [reset = X]

DDRSS_PI_166 is shown in Figure 8-704 and described in Table 8-1418.

Return to Summary Table.

Table 8-1417 DDRSS_PI_166 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2298h
Figure 8-704 DDRSS_PI_166 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDPI_ZQINIT_F0
R/W-XR/W-0h
15141312111098
PI_ZQINIT_F0
R/W-0h
76543210
PI_TDELAY_RDWR_2_BUS_IDLE_F2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1418 DDRSS_PI_166 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/WX
19-8PI_ZQINIT_F0R/W0h

Number of cycles needed for a ZQINIT command for frequency set 0.

7-0PI_TDELAY_RDWR_2_BUS_IDLE_F2R/W0h

The delay from read or write to bus idle for frequency set 2.
Recommend setting is: delay time from read command issued to last read data received.

2.5.3.168 DDRSS_PI_167 Register (Offset = 229Ch) [reset = X]

DDRSS_PI_167 is shown in Figure 8-705 and described in Table 8-1420.

Return to Summary Table.

Table 8-1419 DDRSS_PI_167 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 229Ch
Figure 8-705 DDRSS_PI_167 Register
31302928272625242322212019181716
RESERVEDPI_ZQINIT_F2
R/W-XR/W-0h
1514131211109876543210
RESERVEDPI_ZQINIT_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1420 DDRSS_PI_167 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-16PI_ZQINIT_F2R/W0h

Number of cycles needed for a ZQINIT command for frequency set 2.

15-12RESERVEDR/WX
11-0PI_ZQINIT_F1R/W0h

Number of cycles needed for a ZQINIT command for frequency set 1.

2.5.3.169 DDRSS_PI_168 Register (Offset = 22A0h) [reset = X]

DDRSS_PI_168 is shown in Figure 8-706 and described in Table 8-1422.

Return to Summary Table.

Table 8-1421 DDRSS_PI_168 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22A0h
Figure 8-706 DDRSS_PI_168 Register
3130292827262524
RESERVEDPI_CASLAT_LIN_F1
R/W-XR/W-0h
2322212019181716
RESERVEDPI_WRLAT_F1
R/W-XR/W-0h
15141312111098
RESERVEDPI_CASLAT_LIN_F0
R/W-XR/W-0h
76543210
RESERVEDPI_WRLAT_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1422 DDRSS_PI_168 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/WX
30-24PI_CASLAT_LIN_F1R/W0h

Sets latency from read command sent to data received from/to controller for frequency set 1.
Bit (0) is half-cycle increment and the upper bits define memory CAS latency for the controller.

23RESERVEDR/WX
22-16PI_WRLAT_F1R/W0h

DRAM WRLAT value in cycles for frequency set 1.

15RESERVEDR/WX
14-8PI_CASLAT_LIN_F0R/W0h

Sets latency from read command sent to data received from/to controller for frequency set 0.
Bit (0) is half-cycle increment and the upper bits define memory CAS latency for the controller.

7RESERVEDR/WX
6-0PI_WRLAT_F0R/W0h

DRAM WRLAT value in cycles for frequency set 0.

2.5.3.170 DDRSS_PI_169 Register (Offset = 22A4h) [reset = X]

DDRSS_PI_169 is shown in Figure 8-707 and described in Table 8-1424.

Return to Summary Table.

Table 8-1423 DDRSS_PI_169 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22A4h
Figure 8-707 DDRSS_PI_169 Register
3130292827262524
RESERVEDPI_TRFC_F0
R/W-XR/W-0h
2322212019181716
PI_TRFC_F0
R/W-0h
15141312111098
RESERVEDPI_CASLAT_LIN_F2
R/W-XR/W-0h
76543210
RESERVEDPI_WRLAT_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1424 DDRSS_PI_169 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-16PI_TRFC_F0R/W0h

DRAM tRFC value in memory clocks for frequency set 0.

15RESERVEDR/WX
14-8PI_CASLAT_LIN_F2R/W0h

Sets latency from read command sent to data received from/to controller for frequency set 2.
Bit (0) is half-cycle increment and the upper bits define memory CAS latency for the controller.

7RESERVEDR/WX
6-0PI_WRLAT_F2R/W0h

DRAM WRLAT value in cycles for frequency set 2.

2.5.3.171 DDRSS_PI_170 Register (Offset = 22A8h) [reset = X]

DDRSS_PI_170 is shown in Figure 8-708 and described in Table 8-1426.

Return to Summary Table.

Table 8-1425 DDRSS_PI_170 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22A8h
Figure 8-708 DDRSS_PI_170 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TREF_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1426 DDRSS_PI_170 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/WX
19-0PI_TREF_F0R/W0h

DRAM tREF value in memory clocks for frequency set 0.

2.5.3.172 DDRSS_PI_171 Register (Offset = 22ACh) [reset = X]

DDRSS_PI_171 is shown in Figure 8-709 and described in Table 8-1428.

Return to Summary Table.

Table 8-1427 DDRSS_PI_171 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22ACh
Figure 8-709 DDRSS_PI_171 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TRFC_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1428 DDRSS_PI_171 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/WX
9-0PI_TRFC_F1R/W0h

DRAM tRFC value in memory clocks for frequency set 1.

2.5.3.173 DDRSS_PI_172 Register (Offset = 22B0h) [reset = X]

DDRSS_PI_172 is shown in Figure 8-710 and described in Table 8-1430.

Return to Summary Table.

Table 8-1429 DDRSS_PI_172 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22B0h
Figure 8-710 DDRSS_PI_172 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TREF_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1430 DDRSS_PI_172 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/WX
19-0PI_TREF_F1R/W0h

DRAM tREF value in memory clocks for frequency set 1.

2.5.3.174 DDRSS_PI_173 Register (Offset = 22B4h) [reset = X]

DDRSS_PI_173 is shown in Figure 8-711 and described in Table 8-1432.

Return to Summary Table.

Table 8-1431 DDRSS_PI_173 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22B4h
Figure 8-711 DDRSS_PI_173 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TRFC_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1432 DDRSS_PI_173 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR/WX
9-0PI_TRFC_F2R/W0h

DRAM tRFC value in memory clocks for frequency set 2.

2.5.3.175 DDRSS_PI_174 Register (Offset = 22B8h) [reset = X]

DDRSS_PI_174 is shown in Figure 8-712 and described in Table 8-1434.

Return to Summary Table.

Table 8-1433 DDRSS_PI_174 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22B8h
Figure 8-712 DDRSS_PI_174 Register
3130292827262524
RESERVEDPI_TDFI_CTRL_DELAY_F0
R/W-XR/W-2h
2322212019181716
RESERVEDPI_TREF_F2
R/W-XR/W-0h
15141312111098
PI_TREF_F2
R/W-0h
76543210
PI_TREF_F2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1434 DDRSS_PI_174 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_TDFI_CTRL_DELAY_F0R/W2h

Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks) for frequency set 0, the delay between a DFI command change and a memory command.

23-20RESERVEDR/WX
19-0PI_TREF_F2R/W0h

DRAM tREF value in memory clocks for frequency set 2.

2.5.3.176 DDRSS_PI_175 Register (Offset = 22BCh) [reset = X]

DDRSS_PI_175 is shown in Figure 8-713 and described in Table 8-1436.

Return to Summary Table.

Table 8-1435 DDRSS_PI_175 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22BCh
Figure 8-713 DDRSS_PI_175 Register
3130292827262524
RESERVEDPI_WRLVL_EN_F1
R/W-XR/W-0h
2322212019181716
RESERVEDPI_WRLVL_EN_F0
R/W-XR/W-0h
15141312111098
RESERVEDPI_TDFI_CTRL_DELAY_F2
R/W-XR/W-2h
76543210
RESERVEDPI_TDFI_CTRL_DELAY_F1
R/W-XR/W-2h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1436 DDRSS_PI_175 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-24PI_WRLVL_EN_F1R/W0h

Enable the PI write leveling module for frequency set 1.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.
Set to 1 to enable.

23-18RESERVEDR/WX
17-16PI_WRLVL_EN_F0R/W0h

Enable the PI write leveling module for frequency set 0.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.
Set to 1 to enable.

15-12RESERVEDR/WX
11-8PI_TDFI_CTRL_DELAY_F2R/W2h

Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks) for frequency set 2, the delay between a DFI command change and a memory command.

7-4RESERVEDR/WX
3-0PI_TDFI_CTRL_DELAY_F1R/W2h

Defines the DFI tCTRL_DELAY timing parameter (in DFI clocks) for frequency set 1, the delay between a DFI command change and a memory command.

2.5.3.177 DDRSS_PI_176 Register (Offset = 22C0h) [reset = X]

DDRSS_PI_176 is shown in Figure 8-714 and described in Table 8-1438.

Return to Summary Table.

Table 8-1437 DDRSS_PI_176 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22C0h
Figure 8-714 DDRSS_PI_176 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDPI_TDFI_WRLVL_WW_F0
R/W-XR/W-0h
15141312111098
PI_TDFI_WRLVL_WW_F0
R/W-0h
76543210
RESERVEDPI_WRLVL_EN_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1438 DDRSS_PI_176 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/WX
17-8PI_TDFI_WRLVL_WW_F0R/W0h

Defines the DFI tWRLVL_WW timing parameter (in DFI clocks) for frequency set 0, the minimum cycles between dfi_wrlvl_strobe assertions.

7-2RESERVEDR/WX
1-0PI_WRLVL_EN_F2R/W0h

Enable the PI write leveling module for frequency set 2.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.
Set to 1 to enable.

2.5.3.178 DDRSS_PI_177 Register (Offset = 22C4h) [reset = X]

DDRSS_PI_177 is shown in Figure 8-715 and described in Table 8-1440.

Return to Summary Table.

Table 8-1439 DDRSS_PI_177 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22C4h
Figure 8-715 DDRSS_PI_177 Register
31302928272625242322212019181716
RESERVEDPI_TDFI_WRLVL_WW_F2
R/W-XR/W-0h
1514131211109876543210
RESERVEDPI_TDFI_WRLVL_WW_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1440 DDRSS_PI_177 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-16PI_TDFI_WRLVL_WW_F2R/W0h

Defines the DFI tWRLVL_WW timing parameter (in DFI clocks) for frequency set 2, the minimum cycles between dfi_wrlvl_strobe assertions.

15-10RESERVEDR/WX
9-0PI_TDFI_WRLVL_WW_F1R/W0h

Defines the DFI tWRLVL_WW timing parameter (in DFI clocks) for frequency set 1, the minimum cycles between dfi_wrlvl_strobe assertions.

2.5.3.179 DDRSS_PI_178 Register (Offset = 22C8h) [reset = X]

DDRSS_PI_178 is shown in Figure 8-716 and described in Table 8-1442.

Return to Summary Table.

Table 8-1441 DDRSS_PI_178 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22C8h
Figure 8-716 DDRSS_PI_178 Register
3130292827262524
RESERVEDPI_ODT_EN_F1
R/W-XR/W-0h
2322212019181716
PI_TODTL_2CMD_F1
R/W-0h
15141312111098
RESERVEDPI_ODT_EN_F0
R/W-XR/W-0h
76543210
PI_TODTL_2CMD_F0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1442 DDRSS_PI_178 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR/WX
24PI_ODT_EN_F1R/W0h

Enable support of DRAM ODT.
When enabled, PI will assert and de-assert ODT output to DRAM as needed for frequency set 1.

23-16PI_TODTL_2CMD_F1R/W0h

Defines the DRAM delay from an ODT de-assertion to the next non-write, non-read command for frequency set 1.

15-9RESERVEDR/WX
8PI_ODT_EN_F0R/W0h

Enable support of DRAM ODT.
When enabled, PI will assert and de-assert ODT output to DRAM as needed for frequency set 0.

7-0PI_TODTL_2CMD_F0R/W0h

Defines the DRAM delay from an ODT de-assertion to the next non-write, non-read command for frequency set 0.

2.5.3.180 DDRSS_PI_179 Register (Offset = 22CCh) [reset = X]

DDRSS_PI_179 is shown in Figure 8-717 and described in Table 8-1444.

Return to Summary Table.

Table 8-1443 DDRSS_PI_179 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22CCh
Figure 8-717 DDRSS_PI_179 Register
3130292827262524
RESERVEDPI_TODTON_MIN_F0
R/W-XR/W-0h
2322212019181716
RESERVEDPI_ODTLON_F0
R/W-XR/W-0h
15141312111098
RESERVEDPI_ODT_EN_F2
R/W-XR/W-0h
76543210
PI_TODTL_2CMD_F2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1444 DDRSS_PI_179 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_TODTON_MIN_F0R/W0h

Defines the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on for frequency set 0.

23-20RESERVEDR/WX
19-16PI_ODTLON_F0R/W0h

Defines the latency from a CAS-2 command to the tODTon reference for frequency set 0.

15-9RESERVEDR/WX
8PI_ODT_EN_F2R/W0h

Enable support of DRAM ODT.
When enabled, PI will assert and de-assert ODT output to DRAM as needed for frequency set 2.

7-0PI_TODTL_2CMD_F2R/W0h

Defines the DRAM delay from an ODT de-assertion to the next non-write, non-read command for frequency set 2.

2.5.3.181 DDRSS_PI_180 Register (Offset = 22D0h) [reset = X]

DDRSS_PI_180 is shown in Figure 8-718 and described in Table 8-1446.

Return to Summary Table.

Table 8-1445 DDRSS_PI_180 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22D0h
Figure 8-718 DDRSS_PI_180 Register
3130292827262524
RESERVEDPI_TODTON_MIN_F2
R/W-XR/W-0h
2322212019181716
RESERVEDPI_ODTLON_F2
R/W-XR/W-0h
15141312111098
RESERVEDPI_TODTON_MIN_F1
R/W-XR/W-0h
76543210
RESERVEDPI_ODTLON_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1446 DDRSS_PI_180 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_TODTON_MIN_F2R/W0h

Defines the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on for frequency set 2.

23-20RESERVEDR/WX
19-16PI_ODTLON_F2R/W0h

Defines the latency from a CAS-2 command to the tODTon reference for frequency set 2.

15-12RESERVEDR/WX
11-8PI_TODTON_MIN_F1R/W0h

Defines the point in time when the device termination circuit leaves High-Z and ODT resistance begins to turn on for frequency set 1.

7-4RESERVEDR/WX
3-0PI_ODTLON_F1R/W0h

Defines the latency from a CAS-2 command to the tODTon reference for frequency set 1.

2.5.3.182 DDRSS_PI_181 Register (Offset = 22D4h) [reset = X]

DDRSS_PI_181 is shown in Figure 8-719 and described in Table 8-1448.

Return to Summary Table.

Table 8-1447 DDRSS_PI_181 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22D4h
Figure 8-719 DDRSS_PI_181 Register
3130292827262524
RESERVEDPI_RDLVL_GATE_EN_F1
R/W-XR/W-0h
2322212019181716
RESERVEDPI_RDLVL_EN_F1
R/W-XR/W-0h
15141312111098
RESERVEDPI_RDLVL_GATE_EN_F0
R/W-XR/W-0h
76543210
RESERVEDPI_RDLVL_EN_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1448 DDRSS_PI_181 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-24PI_RDLVL_GATE_EN_F1R/W0h

Enable the PI gate training module for frequency set 1.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.
Set to 1 to enable.

23-18RESERVEDR/WX
17-16PI_RDLVL_EN_F1R/W0h

Enable the PI data eye training module for frequency set 1.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.
Set to 1 to enable.

15-10RESERVEDR/WX
9-8PI_RDLVL_GATE_EN_F0R/W0h

Enable the PI gate training module for frequency set 0.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.
Set to 1 to enable.

7-2RESERVEDR/WX
1-0PI_RDLVL_EN_F0R/W0h

Enable the PI data eye training module for frequency set 0.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.
Set to 1 to enable.

2.5.3.183 DDRSS_PI_182 Register (Offset = 22D8h) [reset = X]

DDRSS_PI_182 is shown in Figure 8-720 and described in Table 8-1450.

Return to Summary Table.

Table 8-1449 DDRSS_PI_182 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22D8h
Figure 8-720 DDRSS_PI_182 Register
3130292827262524
RESERVEDPI_RDLVL_RXCAL_EN_F0
R/W-XR/W-0h
2322212019181716
RESERVEDPI_RDLVL_PAT0_EN_F0
R/W-XR/W-0h
15141312111098
RESERVEDPI_RDLVL_GATE_EN_F2
R/W-XR/W-0h
76543210
RESERVEDPI_RDLVL_EN_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1450 DDRSS_PI_182 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-24PI_RDLVL_RXCAL_EN_F0R/W0h

Enable RX Offset calibration (PATTERN 14,15) for read training for frequency set 0.
bit1 for normal
bit0 for initialization.

23-18RESERVEDR/WX
17-16PI_RDLVL_PAT0_EN_F0R/W0h

Enable PATTERN-0 for read training for frequency set 0.
bit1 for normal
bit0 for initialization.

15-10RESERVEDR/WX
9-8PI_RDLVL_GATE_EN_F2R/W0h

Enable the PI gate training module for frequency set 2.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.
Set to 1 to enable.

7-2RESERVEDR/WX
1-0PI_RDLVL_EN_F2R/W0h

Enable the PI data eye training module for frequency set 2.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.
Set to 1 to enable.

2.5.3.184 DDRSS_PI_183 Register (Offset = 22DCh) [reset = X]

DDRSS_PI_183 is shown in Figure 8-721 and described in Table 8-1452.

Return to Summary Table.

Table 8-1451 DDRSS_PI_183 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22DCh
Figure 8-721 DDRSS_PI_183 Register
3130292827262524
RESERVEDPI_RDLVL_RXCAL_EN_F1
R/W-XR/W-0h
2322212019181716
RESERVEDPI_RDLVL_PAT0_EN_F1
R/W-XR/W-0h
15141312111098
RESERVEDPI_RDLVL_MULTI_EN_F0
R/W-XR/W-0h
76543210
RESERVEDPI_RDLVL_DFE_EN_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1452 DDRSS_PI_183 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-24PI_RDLVL_RXCAL_EN_F1R/W0h

Enable RX Offset calibration (PATTERN 14,15) for read training for frequency set 1.
bit1 for normal
bit0 for initialization.

23-18RESERVEDR/WX
17-16PI_RDLVL_PAT0_EN_F1R/W0h

Enable PATTERN-0 for read training for frequency set 1.
bit1 for normal
bit0 for initialization.

15-10RESERVEDR/WX
9-8PI_RDLVL_MULTI_EN_F0R/W0h

Enable Multi-pattern (from PI_RDLVL_PATTERN_START, total PI_RDLVL_PATTERN_NUM) for read training for frequency set 0.
bit1 for normal
bit0 for initialization.

7-2RESERVEDR/WX
1-0PI_RDLVL_DFE_EN_F0R/W0h

Enable DFE (PATTERN 8,9) for read training for frequency set 0.
bit1 for normal
bit0 for initialization.

2.5.3.185 DDRSS_PI_184 Register (Offset = 22E0h) [reset = X]

DDRSS_PI_184 is shown in Figure 8-722 and described in Table 8-1454.

Return to Summary Table.

Table 8-1453 DDRSS_PI_184 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22E0h
Figure 8-722 DDRSS_PI_184 Register
3130292827262524
RESERVEDPI_RDLVL_RXCAL_EN_F2
R/W-XR/W-0h
2322212019181716
RESERVEDPI_RDLVL_PAT0_EN_F2
R/W-XR/W-0h
15141312111098
RESERVEDPI_RDLVL_MULTI_EN_F1
R/W-XR/W-0h
76543210
RESERVEDPI_RDLVL_DFE_EN_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1454 DDRSS_PI_184 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-24PI_RDLVL_RXCAL_EN_F2R/W0h

Enable RX Offset calibration (PATTERN 14,15) for read training for frequency set 2.
bit1 for normal
bit0 for initialization.

23-18RESERVEDR/WX
17-16PI_RDLVL_PAT0_EN_F2R/W0h

Enable PATTERN-0 for read training for frequency set 2.
bit1 for normal
bit0 for initialization.

15-10RESERVEDR/WX
9-8PI_RDLVL_MULTI_EN_F1R/W0h

Enable Multi-pattern (from PI_RDLVL_PATTERN_START, total PI_RDLVL_PATTERN_NUM) for read training for frequency set 1.
bit1 for normal
bit0 for initialization.

7-2RESERVEDR/WX
1-0PI_RDLVL_DFE_EN_F1R/W0h

Enable DFE (PATTERN 8,9) for read training for frequency set 1.
bit1 for normal
bit0 for initialization.

2.5.3.186 DDRSS_PI_185 Register (Offset = 22E4h) [reset = X]

DDRSS_PI_185 is shown in Figure 8-723 and described in Table 8-1456.

Return to Summary Table.

Table 8-1455 DDRSS_PI_185 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22E4h
Figure 8-723 DDRSS_PI_185 Register
3130292827262524
RESERVEDPI_RDLAT_ADJ_F1
R/W-XR/W-0h
2322212019181716
RESERVEDPI_RDLAT_ADJ_F0
R/W-XR/W-0h
15141312111098
RESERVEDPI_RDLVL_MULTI_EN_F2
R/W-XR/W-0h
76543210
RESERVEDPI_RDLVL_DFE_EN_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1456 DDRSS_PI_185 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/WX
30-24PI_RDLAT_ADJ_F1R/W0h

Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal for frequency set 1.

23RESERVEDR/WX
22-16PI_RDLAT_ADJ_F0R/W0h

Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal for frequency set 0.

15-10RESERVEDR/WX
9-8PI_RDLVL_MULTI_EN_F2R/W0h

Enable Multi-pattern (from PI_RDLVL_PATTERN_START, total PI_RDLVL_PATTERN_NUM) for read training for frequency set 2.
bit1 for normal
bit0 for initialization.

7-2RESERVEDR/WX
1-0PI_RDLVL_DFE_EN_F2R/W0h

Enable DFE (PATTERN 8,9) for read training for frequency set 2.
bit1 for normal
bit0 for initialization.

2.5.3.187 DDRSS_PI_186 Register (Offset = 22E8h) [reset = X]

DDRSS_PI_186 is shown in Figure 8-724 and described in Table 8-1458.

Return to Summary Table.

Table 8-1457 DDRSS_PI_186 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22E8h
Figure 8-724 DDRSS_PI_186 Register
3130292827262524
RESERVEDPI_WRLAT_ADJ_F2
R/W-XR/W-0h
2322212019181716
RESERVEDPI_WRLAT_ADJ_F1
R/W-XR/W-0h
15141312111098
RESERVEDPI_WRLAT_ADJ_F0
R/W-XR/W-0h
76543210
RESERVEDPI_RDLAT_ADJ_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1458 DDRSS_PI_186 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/WX
30-24PI_WRLAT_ADJ_F2R/W0h

Adjusts the relative timing in memory clocks between DFI write commands and the dfi_wrdata_en signal for frequency set 2.

23RESERVEDR/WX
22-16PI_WRLAT_ADJ_F1R/W0h

Adjusts the relative timing in memory clocks between DFI write commands and the dfi_wrdata_en signal for frequency set 1.

15RESERVEDR/WX
14-8PI_WRLAT_ADJ_F0R/W0h

Adjusts the relative timing in memory clocks between DFI write commands and the dfi_wrdata_en signal for frequency set 0.

7RESERVEDR/WX
6-0PI_RDLAT_ADJ_F2R/W0h

Adjusts the relative timing between DFI read commands and the dfi_rddata_en signal for frequency set 2.

2.5.3.188 DDRSS_PI_187 Register (Offset = 22ECh) [reset = X]

DDRSS_PI_187 is shown in Figure 8-725 and described in Table 8-1460.

Return to Summary Table.

Table 8-1459 DDRSS_PI_187 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22ECh
Figure 8-725 DDRSS_PI_187 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDPI_TDFI_PHY_WRDATA_F2
R/W-XR/W-1h
15141312111098
RESERVEDPI_TDFI_PHY_WRDATA_F1
R/W-XR/W-1h
76543210
RESERVEDPI_TDFI_PHY_WRDATA_F0
R/W-XR/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1460 DDRSS_PI_187 Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR/WX
18-16PI_TDFI_PHY_WRDATA_F2R/W1h

Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks) for frequency set 2, the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal.

15-11RESERVEDR/WX
10-8PI_TDFI_PHY_WRDATA_F1R/W1h

Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks) for frequency set 1, the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal.

7-3RESERVEDR/WX
2-0PI_TDFI_PHY_WRDATA_F0R/W1h

Defines the DFI tPHY_WRDATA timing parameter (in DFI PHY clocks) for frequency set 0, the maximum cycles between a dfi_wrdata_en assertion and a dfi_wrdata signal.

2.5.3.189 DDRSS_PI_188 Register (Offset = 22F0h) [reset = X]

DDRSS_PI_188 is shown in Figure 8-726 and described in Table 8-1462.

Return to Summary Table.

Table 8-1461 DDRSS_PI_188 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22F0h
Figure 8-726 DDRSS_PI_188 Register
31302928272625242322212019181716
RESERVEDPI_TDFI_CALVL_CAPTURE_F0
R/W-XR/W-0h
1514131211109876543210
RESERVEDPI_TDFI_CALVL_CC_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1462 DDRSS_PI_188 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-16PI_TDFI_CALVL_CAPTURE_F0R/W0h

Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks) for frequency set 0, the minimum cycles between a calibration command and a dfi_calvl_capture pulse.

15-10RESERVEDR/WX
9-0PI_TDFI_CALVL_CC_F0R/W0h

Defines the DFI tCALVL_CC timing parameter (in DFI clocks) for frequency set 0, the minimum cycles between calibration commands.

2.5.3.190 DDRSS_PI_189 Register (Offset = 22F4h) [reset = X]

DDRSS_PI_189 is shown in Figure 8-727 and described in Table 8-1464.

Return to Summary Table.

Table 8-1463 DDRSS_PI_189 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22F4h
Figure 8-727 DDRSS_PI_189 Register
31302928272625242322212019181716
RESERVEDPI_TDFI_CALVL_CAPTURE_F1
R/W-XR/W-0h
1514131211109876543210
RESERVEDPI_TDFI_CALVL_CC_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1464 DDRSS_PI_189 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-16PI_TDFI_CALVL_CAPTURE_F1R/W0h

Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks) for frequency set 1, the minimum cycles between a calibration command and a dfi_calvl_capture pulse.

15-10RESERVEDR/WX
9-0PI_TDFI_CALVL_CC_F1R/W0h

Defines the DFI tCALVL_CC timing parameter (in DFI clocks) for frequency set 1, the minimum cycles between calibration commands.

2.5.3.191 DDRSS_PI_190 Register (Offset = 22F8h) [reset = X]

DDRSS_PI_190 is shown in Figure 8-728 and described in Table 8-1466.

Return to Summary Table.

Table 8-1465 DDRSS_PI_190 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22F8h
Figure 8-728 DDRSS_PI_190 Register
31302928272625242322212019181716
RESERVEDPI_TDFI_CALVL_CAPTURE_F2
R/W-XR/W-0h
1514131211109876543210
RESERVEDPI_TDFI_CALVL_CC_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1466 DDRSS_PI_190 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-16PI_TDFI_CALVL_CAPTURE_F2R/W0h

Defines the DFI tCALVL_CAPTURE timing parameter (in DFI clocks) for frequency set 2, the minimum cycles between a calibration command and a dfi_calvl_capture pulse.

15-10RESERVEDR/WX
9-0PI_TDFI_CALVL_CC_F2R/W0h

Defines the DFI tCALVL_CC timing parameter (in DFI clocks) for frequency set 2, the minimum cycles between calibration commands.

2.5.3.192 DDRSS_PI_191 Register (Offset = 22FCh) [reset = X]

DDRSS_PI_191 is shown in Figure 8-729 and described in Table 8-1468.

Return to Summary Table.

Table 8-1467 DDRSS_PI_191 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 22FCh
Figure 8-729 DDRSS_PI_191 Register
3130292827262524
RESERVEDPI_TMRZ_F0
R/W-XR/W-0h
2322212019181716
RESERVEDPI_CALVL_EN_F2
R/W-XR/W-0h
15141312111098
RESERVEDPI_CALVL_EN_F1
R/W-XR/W-0h
76543210
RESERVEDPI_CALVL_EN_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1468 DDRSS_PI_191 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24PI_TMRZ_F0R/W0h

Defines the delay between a MRW CA exit command and the DQ tristate in memory clocks for frequency set 0.

23-18RESERVEDR/WX
17-16PI_CALVL_EN_F2R/W0h

Enable the PI CA training module.
Bit(1) represents the support when non-initialization for frequency set 2.
Bit(0)represents the support when initialization.
Set to 1 to enable.

15-10RESERVEDR/WX
9-8PI_CALVL_EN_F1R/W0h

Enable the PI CA training module.
Bit(1) represents the support when non-initialization for frequency set 1.
Bit(0)represents the support when initialization.
Set to 1 to enable.

7-2RESERVEDR/WX
1-0PI_CALVL_EN_F0R/W0h

Enable the PI CA training module.
Bit(1) represents the support when non-initialization for frequency set 0.
Bit(0)represents the support when initialization.
Set to 1 to enable.

2.5.3.193 DDRSS_PI_192 Register (Offset = 2300h) [reset = X]

DDRSS_PI_192 is shown in Figure 8-730 and described in Table 8-1470.

Return to Summary Table.

Table 8-1469 DDRSS_PI_192 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2300h
Figure 8-730 DDRSS_PI_192 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDPI_TMRZ_F1
R/W-XR/W-0h
15141312111098
RESERVEDPI_TCAENT_F0
R/W-XR/W-0h
76543210
PI_TCAENT_F0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1470 DDRSS_PI_192 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR/WX
20-16PI_TMRZ_F1R/W0h

Defines the delay between a MRW CA exit command and the DQ tristate in memory clocks for frequency set 1.

15-14RESERVEDR/WX
13-0PI_TCAENT_F0R/W0h

Defines the DRAM tCAENT term, in memory clocks for frequency set 0.

2.5.3.194 DDRSS_PI_193 Register (Offset = 2304h) [reset = X]

DDRSS_PI_193 is shown in Figure 8-731 and described in Table 8-1472.

Return to Summary Table.

Table 8-1471 DDRSS_PI_193 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2304h
Figure 8-731 DDRSS_PI_193 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDPI_TMRZ_F2
R/W-XR/W-0h
15141312111098
RESERVEDPI_TCAENT_F1
R/W-XR/W-0h
76543210
PI_TCAENT_F1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1472 DDRSS_PI_193 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR/WX
20-16PI_TMRZ_F2R/W0h

Defines the delay between a MRW CA exit command and the DQ tristate in memory clocks for frequency set 2.

15-14RESERVEDR/WX
13-0PI_TCAENT_F1R/W0h

Defines the DRAM tCAENT term, in memory clocks for frequency set 1.

2.5.3.195 DDRSS_PI_194 Register (Offset = 2308h) [reset = X]

DDRSS_PI_194 is shown in Figure 8-732 and described in Table 8-1474.

Return to Summary Table.

Table 8-1473 DDRSS_PI_194 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2308h
Figure 8-732 DDRSS_PI_194 Register
3130292827262524
RESERVEDPI_TDFI_CASEL_F0
R/W-XR/W-0h
2322212019181716
RESERVEDPI_TDFI_CACSCA_F0
R/W-XR/W-0h
15141312111098
RESERVEDPI_TCAENT_F2
R/W-XR/W-0h
76543210
PI_TCAENT_F2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1474 DDRSS_PI_194 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24PI_TDFI_CASEL_F0R/W0h

Defines the DFI tcalvl_ca_sel timing parameter, the width of dfi_calvl_ca_sel in PHY DFI clock cycles for frequency set 0.

23-21RESERVEDR/WX
20-16PI_TDFI_CACSCA_F0R/W0h

Defines the DFI tcalvl_cs_ca timing parameter, the number of PHY DFI clocks from the assertion of dfi_calvl_ca_sel to the assertion of dfi_cs for frequency set 0.

15-14RESERVEDR/WX
13-0PI_TCAENT_F2R/W0h

Defines the DRAM tCAENT term, in memory clocks for frequency set 2.

2.5.3.196 DDRSS_PI_195 Register (Offset = 230Ch) [reset = X]

DDRSS_PI_195 is shown in Figure 8-733 and described in Table 8-1476.

Return to Summary Table.

Table 8-1475 DDRSS_PI_195 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 230Ch
Figure 8-733 DDRSS_PI_195 Register
31302928272625242322212019181716
RESERVEDPI_TVREF_LONG_F0
R/W-XR/W-0h
1514131211109876543210
RESERVEDPI_TVREF_SHORT_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1476 DDRSS_PI_195 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-16PI_TVREF_LONG_F0R/W0h

Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter gt 1 for frequency set 0.

15-10RESERVEDR/WX
9-0PI_TVREF_SHORT_F0R/W0h

Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter = 1 for frequency set 0.

2.5.3.197 DDRSS_PI_196 Register (Offset = 2310h) [reset = X]

DDRSS_PI_196 is shown in Figure 8-734 and described in Table 8-1478.

Return to Summary Table.

Table 8-1477 DDRSS_PI_196 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2310h
Figure 8-734 DDRSS_PI_196 Register
3130292827262524
RESERVEDPI_TVREF_SHORT_F1
R/W-XR/W-0h
2322212019181716
PI_TVREF_SHORT_F1
R/W-0h
15141312111098
RESERVEDPI_TDFI_CASEL_F1
R/W-XR/W-0h
76543210
RESERVEDPI_TDFI_CACSCA_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1478 DDRSS_PI_196 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-16PI_TVREF_SHORT_F1R/W0h

Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter = 1 for frequency set 1.

15-13RESERVEDR/WX
12-8PI_TDFI_CASEL_F1R/W0h

Defines the DFI tcalvl_ca_sel timing parameter, the width of dfi_calvl_ca_sel in PHY DFI clock cycles for frequency set 1.

7-5RESERVEDR/WX
4-0PI_TDFI_CACSCA_F1R/W0h

Defines the DFI tcalvl_cs_ca timing parameter, the number of PHY DFI clocks from the assertion of dfi_calvl_ca_sel to the assertion of dfi_cs for frequency set 1.

2.5.3.198 DDRSS_PI_197 Register (Offset = 2314h) [reset = X]

DDRSS_PI_197 is shown in Figure 8-735 and described in Table 8-1480.

Return to Summary Table.

Table 8-1479 DDRSS_PI_197 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2314h
Figure 8-735 DDRSS_PI_197 Register
3130292827262524
RESERVEDPI_TDFI_CASEL_F2
R/W-XR/W-0h
2322212019181716
RESERVEDPI_TDFI_CACSCA_F2
R/W-XR/W-0h
15141312111098
RESERVEDPI_TVREF_LONG_F1
R/W-XR/W-0h
76543210
PI_TVREF_LONG_F1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1480 DDRSS_PI_197 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-24PI_TDFI_CASEL_F2R/W0h

Defines the DFI tcalvl_ca_sel timing parameter, the width of dfi_calvl_ca_sel in PHY DFI clock cycles for frequency set 2.

23-21RESERVEDR/WX
20-16PI_TDFI_CACSCA_F2R/W0h

Defines the DFI tcalvl_cs_ca timing parameter, the number of PHY DFI clocks from the assertion of dfi_calvl_ca_sel to the assertion of dfi_cs for frequency set 2.

15-10RESERVEDR/WX
9-0PI_TVREF_LONG_F1R/W0h

Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter gt 1 for frequency set 1.

2.5.3.199 DDRSS_PI_198 Register (Offset = 2318h) [reset = X]

DDRSS_PI_198 is shown in Figure 8-736 and described in Table 8-1482.

Return to Summary Table.

Table 8-1481 DDRSS_PI_198 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2318h
Figure 8-736 DDRSS_PI_198 Register
31302928272625242322212019181716
RESERVEDPI_TVREF_LONG_F2
R/W-XR/W-0h
1514131211109876543210
RESERVEDPI_TVREF_SHORT_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1482 DDRSS_PI_198 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-16PI_TVREF_LONG_F2R/W0h

Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter gt 1 for frequency set 2.

15-10RESERVEDR/WX
9-0PI_TVREF_SHORT_F2R/W0h

Defines the delay in PI clock cycles between the dfi_calvl_strobe to the next command if the pi_calvl_vref_stepsize parameter = 1 for frequency set 2.

2.5.3.200 DDRSS_PI_199 Register (Offset = 231Ch) [reset = X]

DDRSS_PI_199 is shown in Figure 8-737 and described in Table 8-1484.

Return to Summary Table.

Table 8-1483 DDRSS_PI_199 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 231Ch
Figure 8-737 DDRSS_PI_199 Register
3130292827262524
RESERVEDPI_CALVL_VREF_INITIAL_STOP_POINT_F1
R/W-XR/W-0h
2322212019181716
RESERVEDPI_CALVL_VREF_INITIAL_START_POINT_F1
R/W-XR/W-0h
15141312111098
RESERVEDPI_CALVL_VREF_INITIAL_STOP_POINT_F0
R/W-XR/W-0h
76543210
RESERVEDPI_CALVL_VREF_INITIAL_START_POINT_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1484 DDRSS_PI_199 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/WX
30-24PI_CALVL_VREF_INITIAL_STOP_POINT_F1R/W0h

The end point of initial training for the Vref(ca) training for frequency set 1 { vrefca_range, vref_ca_setting
[5:0]}.

23RESERVEDR/WX
22-16PI_CALVL_VREF_INITIAL_START_POINT_F1R/W0h

The start point of initial training for the Vref(ca) training for frequency set 1 { vrefca_range, vref_ca_setting
[5:0]}.

15RESERVEDR/WX
14-8PI_CALVL_VREF_INITIAL_STOP_POINT_F0R/W0h

The end point of initial training for the Vref(ca) training for frequency set 0 { vrefca_range, vref_ca_setting
[5:0]}.

7RESERVEDR/WX
6-0PI_CALVL_VREF_INITIAL_START_POINT_F0R/W0h

The start point of initial training for the Vref(ca) training for frequency set 0 { vrefca_range, vref_ca_setting
[5:0]}.

2.5.3.201 DDRSS_PI_200 Register (Offset = 2320h) [reset = X]

DDRSS_PI_200 is shown in Figure 8-738 and described in Table 8-1486.

Return to Summary Table.

Table 8-1485 DDRSS_PI_200 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2320h
Figure 8-738 DDRSS_PI_200 Register
3130292827262524
RESERVEDPI_CALVL_VREF_DELTA_F1
R/W-XR/W-0h
2322212019181716
RESERVEDPI_CALVL_VREF_DELTA_F0
R/W-XR/W-0h
15141312111098
RESERVEDPI_CALVL_VREF_INITIAL_STOP_POINT_F2
R/W-XR/W-0h
76543210
RESERVEDPI_CALVL_VREF_INITIAL_START_POINT_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1486 DDRSS_PI_200 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_CALVL_VREF_DELTA_F1R/W0h

The delta fro the current CA vref for non-initial CA training for frequency set 1.

23-20RESERVEDR/WX
19-16PI_CALVL_VREF_DELTA_F0R/W0h

The delta fro the current CA vref for non-initial CA training for frequency set 0.

15RESERVEDR/WX
14-8PI_CALVL_VREF_INITIAL_STOP_POINT_F2R/W0h

The end point of initial training for the Vref(ca) training for frequency set 2 { vrefca_range, vref_ca_setting
[5:0]}.

7RESERVEDR/WX
6-0PI_CALVL_VREF_INITIAL_START_POINT_F2R/W0h

The start point of initial training for the Vref(ca) training for frequency set 2 { vrefca_range, vref_ca_setting
[5:0]}.

2.5.3.202 DDRSS_PI_201 Register (Offset = 2324h) [reset = X]

DDRSS_PI_201 is shown in Figure 8-739 and described in Table 8-1488.

Return to Summary Table.

Table 8-1487 DDRSS_PI_201 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2324h
Figure 8-739 DDRSS_PI_201 Register
3130292827262524
PI_TMRWCKEL_F0
R/W-0h
2322212019181716
RESERVEDPI_TXP_F0
R/W-XR/W-0h
15141312111098
RESERVEDPI_TDFI_CALVL_STROBE_F0
R/W-XR/W-0h
76543210
RESERVEDPI_CALVL_VREF_DELTA_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1488 DDRSS_PI_201 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TMRWCKEL_F0R/W0h

Valid Clock and CS Requirement before CKE deassert after MRW Command for frequency set 0.

23-21RESERVEDR/WX
20-16PI_TXP_F0R/W0h

CKE assert to next valid command delay for frequency set 0.

15-12RESERVEDR/WX
11-8PI_TDFI_CALVL_STROBE_F0R/W0h

Minimum number of DFI PHY clocks from dfi_calvl_data to dfi_calvl_strobe mode for frequency set 0.

7-4RESERVEDR/WX
3-0PI_CALVL_VREF_DELTA_F2R/W0h

The delta fro the current CA vref for non-initial CA training for frequency set 2.

2.5.3.203 DDRSS_PI_202 Register (Offset = 2328h) [reset = X]

DDRSS_PI_202 is shown in Figure 8-740 and described in Table 8-1490.

Return to Summary Table.

Table 8-1489 DDRSS_PI_202 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2328h
Figure 8-740 DDRSS_PI_202 Register
3130292827262524
PI_TMRWCKEL_F1
R/W-0h
2322212019181716
RESERVEDPI_TXP_F1
R/W-XR/W-0h
15141312111098
RESERVEDPI_TDFI_CALVL_STROBE_F1
R/W-XR/W-0h
76543210
RESERVEDPI_TCKELCK_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1490 DDRSS_PI_202 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TMRWCKEL_F1R/W0h

Valid Clock and CS Requirement before CKE deassert after MRW Command for frequency set 1.

23-21RESERVEDR/WX
20-16PI_TXP_F1R/W0h

CKE assert to next valid command delay for frequency set 1.

15-12RESERVEDR/WX
11-8PI_TDFI_CALVL_STROBE_F1R/W0h

Minimum number of DFI PHY clocks from dfi_calvl_data to dfi_calvl_strobe mode for frequency set 1.

7-5RESERVEDR/WX
4-0PI_TCKELCK_F0R/W0h

Valid Clock Requirement after CKE deassert for frequency set 0.

2.5.3.204 DDRSS_PI_203 Register (Offset = 232Ch) [reset = X]

DDRSS_PI_203 is shown in Figure 8-741 and described in Table 8-1492.

Return to Summary Table.

Table 8-1491 DDRSS_PI_203 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 232Ch
Figure 8-741 DDRSS_PI_203 Register
3130292827262524
PI_TMRWCKEL_F2
R/W-0h
2322212019181716
RESERVEDPI_TXP_F2
R/W-XR/W-0h
15141312111098
RESERVEDPI_TDFI_CALVL_STROBE_F2
R/W-XR/W-0h
76543210
RESERVEDPI_TCKELCK_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1492 DDRSS_PI_203 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TMRWCKEL_F2R/W0h

Valid Clock and CS Requirement before CKE deassert after MRW Command for frequency set 2.

23-21RESERVEDR/WX
20-16PI_TXP_F2R/W0h

CKE assert to next valid command delay for frequency set 2.

15-12RESERVEDR/WX
11-8PI_TDFI_CALVL_STROBE_F2R/W0h

Minimum number of DFI PHY clocks from dfi_calvl_data to dfi_calvl_strobe mode for frequency set 2.

7-5RESERVEDR/WX
4-0PI_TCKELCK_F1R/W0h

Valid Clock Requirement after CKE deassert for frequency set 1.

2.5.3.205 DDRSS_PI_204 Register (Offset = 2330h) [reset = X]

DDRSS_PI_204 is shown in Figure 8-742 and described in Table 8-1494.

Return to Summary Table.

Table 8-1493 DDRSS_PI_204 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2330h
Figure 8-742 DDRSS_PI_204 Register
31302928272625242322212019181716
RESERVEDPI_TDFI_INIT_START_F0
R/W-XR/W-0h
1514131211109876543210
PI_TDFI_INIT_START_F0RESERVEDPI_TCKELCK_F2
R/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1494 DDRSS_PI_204 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/WX
17-8PI_TDFI_INIT_START_F0R/W0h

Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency set 0, the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY.

7-5RESERVEDR/WX
4-0PI_TCKELCK_F2R/W0h

Valid Clock Requirement after CKE deassert for frequency set 2.

2.5.3.206 DDRSS_PI_205 Register (Offset = 2334h) [reset = X]

DDRSS_PI_205 is shown in Figure 8-743 and described in Table 8-1496.

Return to Summary Table.

Table 8-1495 DDRSS_PI_205 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2334h
Figure 8-743 DDRSS_PI_205 Register
31302928272625242322212019181716
RESERVEDPI_TDFI_INIT_START_F1
R/W-XR/W-0h
1514131211109876543210
PI_TDFI_INIT_COMPLETE_F0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1496 DDRSS_PI_205 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-16PI_TDFI_INIT_START_F1R/W0h

Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency set 1, the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY.

15-0PI_TDFI_INIT_COMPLETE_F0R/W0h

Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency set 0, the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY.

2.5.3.207 DDRSS_PI_206 Register (Offset = 2338h) [reset = X]

DDRSS_PI_206 is shown in Figure 8-744 and described in Table 8-1498.

Return to Summary Table.

Table 8-1497 DDRSS_PI_206 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2338h
Figure 8-744 DDRSS_PI_206 Register
31302928272625242322212019181716
RESERVEDPI_TDFI_INIT_START_F2
R/W-XR/W-0h
1514131211109876543210
PI_TDFI_INIT_COMPLETE_F1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1498 DDRSS_PI_206 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-16PI_TDFI_INIT_START_F2R/W0h

Defines the DFI tINIT_START timing parameter (in DFI clocks) for frequency set 2, the maximum number of cycles between a dfi_init_start assertion and a dfi_init_complete de-assertion from the PHY.

15-0PI_TDFI_INIT_COMPLETE_F1R/W0h

Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency set 1, the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY.

2.5.3.208 DDRSS_PI_207 Register (Offset = 233Ch) [reset = X]

DDRSS_PI_207 is shown in Figure 8-745 and described in Table 8-1500.

Return to Summary Table.

Table 8-1499 DDRSS_PI_207 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 233Ch
Figure 8-745 DDRSS_PI_207 Register
31302928272625242322212019181716
RESERVEDPI_TCKEHDQS_F0
R/W-XR/W-0h
1514131211109876543210
PI_TDFI_INIT_COMPLETE_F2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1500 DDRSS_PI_207 Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR/WX
21-16PI_TCKEHDQS_F0R/W0h

The DRAM timing tCKEHDQS, minimum delay from CKE high to strobe high impedance for frequency set 0.

15-0PI_TDFI_INIT_COMPLETE_F2R/W0h

Defines the DFI tINIT_COMPLETE timing parameter (in DFI clocks) for frequency set 2, the maximum cycles between a dfi_init_start de-assertion and a dfi_init_complete assertion from the PHY.

2.5.3.209 DDRSS_PI_208 Register (Offset = 2340h) [reset = X]

DDRSS_PI_208 is shown in Figure 8-746 and described in Table 8-1502.

Return to Summary Table.

Table 8-1501 DDRSS_PI_208 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2340h
Figure 8-746 DDRSS_PI_208 Register
31302928272625242322212019181716
RESERVEDPI_TCKEHDQS_F1
R/W-XR/W-0h
1514131211109876543210
RESERVEDPI_TFC_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1502 DDRSS_PI_208 Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR/WX
21-16PI_TCKEHDQS_F1R/W0h

The DRAM timing tCKEHDQS, minimum delay from CKE high to strobe high impedance for frequency set 1.

15-10RESERVEDR/WX
9-0PI_TFC_F0R/W0h

The delay in PHY clock cycles from setting MR13.OP7 to any valid command for frequency set 0.

2.5.3.210 DDRSS_PI_209 Register (Offset = 2344h) [reset = X]

DDRSS_PI_209 is shown in Figure 8-747 and described in Table 8-1504.

Return to Summary Table.

Table 8-1503 DDRSS_PI_209 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2344h
Figure 8-747 DDRSS_PI_209 Register
31302928272625242322212019181716
RESERVEDPI_TCKEHDQS_F2
R/W-XR/W-0h
1514131211109876543210
RESERVEDPI_TFC_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1504 DDRSS_PI_209 Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR/WX
21-16PI_TCKEHDQS_F2R/W0h

The DRAM timing tCKEHDQS, minimum delay from CKE high to strobe high impedance for frequency set 2.

15-10RESERVEDR/WX
9-0PI_TFC_F1R/W0h

The delay in PHY clock cycles from setting MR13.OP7 to any valid command for frequency set 1.

2.5.3.211 DDRSS_PI_210 Register (Offset = 2348h) [reset = X]

DDRSS_PI_210 is shown in Figure 8-748 and described in Table 8-1506.

Return to Summary Table.

Table 8-1505 DDRSS_PI_210 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2348h
Figure 8-748 DDRSS_PI_210 Register
31302928272625242322212019181716
RESERVEDPI_TDFI_WDQLVL_WR_F0
R/W-XR/W-0h
1514131211109876543210
RESERVEDPI_TFC_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1506 DDRSS_PI_210 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-16PI_TDFI_WDQLVL_WR_F0R/W0h

Switch time from write to read for frequency set 0.

15-10RESERVEDR/WX
9-0PI_TFC_F2R/W0h

The delay in PHY clock cycles from setting MR13.OP7 to any valid command for frequency set 2.

2.5.3.212 DDRSS_PI_211 Register (Offset = 234Ch) [reset = X]

DDRSS_PI_211 is shown in Figure 8-749 and described in Table 8-1508.

Return to Summary Table.

Table 8-1507 DDRSS_PI_211 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 234Ch
Figure 8-749 DDRSS_PI_211 Register
3130292827262524
RESERVEDPI_WDQLVL_VREF_INITIAL_STOP_POINT_F0
R/W-XR/W-0h
2322212019181716
RESERVEDPI_WDQLVL_VREF_INITIAL_START_POINT_F0
R/W-XR/W-0h
15141312111098
RESERVEDPI_TDFI_WDQLVL_RW_F0
R/W-XR/W-0h
76543210
PI_TDFI_WDQLVL_RW_F0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1508 DDRSS_PI_211 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/WX
30-24PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0R/W0h

Write DQ training vref initial training stop value for frequency set 0.

23RESERVEDR/WX
22-16PI_WDQLVL_VREF_INITIAL_START_POINT_F0R/W0h

Write DQ training vref initial training start value for frequency set 0.

15-10RESERVEDR/WX
9-0PI_TDFI_WDQLVL_RW_F0R/W0h

Switch time from read to write for frequency set 0.

2.5.3.213 DDRSS_PI_212 Register (Offset = 2350h) [reset = X]

DDRSS_PI_212 is shown in Figure 8-750 and described in Table 8-1510.

Return to Summary Table.

Table 8-1509 DDRSS_PI_212 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2350h
Figure 8-750 DDRSS_PI_212 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDPI_NTP_TRAIN_EN_F0
R/W-XR/W-0h
15141312111098
RESERVEDPI_WDQLVL_EN_F0
R/W-XR/W-0h
76543210
RESERVEDPI_WDQLVL_VREF_DELTA_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1510 DDRSS_PI_212 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/WX
17-16PI_NTP_TRAIN_EN_F0R/W0h

Indicates whether the no topology WDQ training is enabled.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.

15-10RESERVEDR/WX
9-8PI_WDQLVL_EN_F0R/W0h

Indicates if Write DQ leveling is enabled for frequency set 0.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.

7-4RESERVEDR/WX
3-0PI_WDQLVL_VREF_DELTA_F0R/W0h

The delta from the current Write DQ vref adjustment for non-initial wdq training for frequency set 0.

2.5.3.214 DDRSS_PI_213 Register (Offset = 2354h) [reset = X]

DDRSS_PI_213 is shown in Figure 8-751 and described in Table 8-1512.

Return to Summary Table.

Table 8-1511 DDRSS_PI_213 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2354h
Figure 8-751 DDRSS_PI_213 Register
31302928272625242322212019181716
RESERVEDPI_TDFI_WDQLVL_RW_F1
R/W-XR/W-0h
1514131211109876543210
RESERVEDPI_TDFI_WDQLVL_WR_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1512 DDRSS_PI_213 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-16PI_TDFI_WDQLVL_RW_F1R/W0h

Switch time from read to write for frequency set 1.

15-10RESERVEDR/WX
9-0PI_TDFI_WDQLVL_WR_F1R/W0h

Switch time from write to read for frequency set 1.

2.5.3.215 DDRSS_PI_214 Register (Offset = 2358h) [reset = X]

DDRSS_PI_214 is shown in Figure 8-752 and described in Table 8-1514.

Return to Summary Table.

Table 8-1513 DDRSS_PI_214 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2358h
Figure 8-752 DDRSS_PI_214 Register
3130292827262524
RESERVEDPI_WDQLVL_EN_F1
R/W-XR/W-0h
2322212019181716
RESERVEDPI_WDQLVL_VREF_DELTA_F1
R/W-XR/W-0h
15141312111098
RESERVEDPI_WDQLVL_VREF_INITIAL_STOP_POINT_F1
R/W-XR/W-0h
76543210
RESERVEDPI_WDQLVL_VREF_INITIAL_START_POINT_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1514 DDRSS_PI_214 Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR/WX
25-24PI_WDQLVL_EN_F1R/W0h

Indicates if Write DQ leveling is enabled for frequency set 1.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.

23-20RESERVEDR/WX
19-16PI_WDQLVL_VREF_DELTA_F1R/W0h

The delta from the current Write DQ vref adjustment for non-initial wdq training for frequency set 1.

15RESERVEDR/WX
14-8PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1R/W0h

Write DQ training vref initial training stop value for frequency set 1.

7RESERVEDR/WX
6-0PI_WDQLVL_VREF_INITIAL_START_POINT_F1R/W0h

Write DQ training vref initial training start value for frequency set 1.

2.5.3.216 DDRSS_PI_215 Register (Offset = 235Ch) [reset = X]

DDRSS_PI_215 is shown in Figure 8-753 and described in Table 8-1516.

Return to Summary Table.

Table 8-1515 DDRSS_PI_215 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 235Ch
Figure 8-753 DDRSS_PI_215 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDPI_TDFI_WDQLVL_WR_F2
R/W-XR/W-0h
15141312111098
PI_TDFI_WDQLVL_WR_F2
R/W-0h
76543210
RESERVEDPI_NTP_TRAIN_EN_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1516 DDRSS_PI_215 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/WX
17-8PI_TDFI_WDQLVL_WR_F2R/W0h

Switch time from write to read for frequency set 2.

7-2RESERVEDR/WX
1-0PI_NTP_TRAIN_EN_F1R/W0h

Indicates whether the no topology WDQ training is enabled.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.

2.5.3.217 DDRSS_PI_216 Register (Offset = 2360h) [reset = X]

DDRSS_PI_216 is shown in Figure 8-754 and described in Table 8-1518.

Return to Summary Table.

Table 8-1517 DDRSS_PI_216 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2360h
Figure 8-754 DDRSS_PI_216 Register
3130292827262524
RESERVEDPI_WDQLVL_VREF_INITIAL_STOP_POINT_F2
R/W-XR/W-0h
2322212019181716
RESERVEDPI_WDQLVL_VREF_INITIAL_START_POINT_F2
R/W-XR/W-0h
15141312111098
RESERVEDPI_TDFI_WDQLVL_RW_F2
R/W-XR/W-0h
76543210
PI_TDFI_WDQLVL_RW_F2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1518 DDRSS_PI_216 Register Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR/WX
30-24PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2R/W0h

Write DQ training vref initial training stop value for frequency set 2.

23RESERVEDR/WX
22-16PI_WDQLVL_VREF_INITIAL_START_POINT_F2R/W0h

Write DQ training vref initial training start value for frequency set 2.

15-10RESERVEDR/WX
9-0PI_TDFI_WDQLVL_RW_F2R/W0h

Switch time from read to write for frequency set 2.

2.5.3.218 DDRSS_PI_217 Register (Offset = 2364h) [reset = X]

DDRSS_PI_217 is shown in Figure 8-755 and described in Table 8-1520.

Return to Summary Table.

Table 8-1519 DDRSS_PI_217 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2364h
Figure 8-755 DDRSS_PI_217 Register
3130292827262524
PI_TRTP_F0
R/W-0h
2322212019181716
RESERVEDPI_NTP_TRAIN_EN_F2
R/W-XR/W-0h
15141312111098
RESERVEDPI_WDQLVL_EN_F2
R/W-XR/W-0h
76543210
RESERVEDPI_WDQLVL_VREF_DELTA_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1520 DDRSS_PI_217 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TRTP_F0R/W0h

DRAM tRTP value in cycles for frequency set 0.

23-18RESERVEDR/WX
17-16PI_NTP_TRAIN_EN_F2R/W0h

Indicates whether the no topology WDQ training is enabled.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.

15-10RESERVEDR/WX
9-8PI_WDQLVL_EN_F2R/W0h

Indicates if Write DQ leveling is enabled for frequency set 2.
Bit(1) represents the support when non-initialization.
Bit(0)represents the support when initialization.

7-4RESERVEDR/WX
3-0PI_WDQLVL_VREF_DELTA_F2R/W0h

The delta from the current Write DQ vref adjustment for non-initial wdq training for frequency set 2.

2.5.3.219 DDRSS_PI_218 Register (Offset = 2368h) [reset = X]

DDRSS_PI_218 is shown in Figure 8-756 and described in Table 8-1522.

Return to Summary Table.

Table 8-1521 DDRSS_PI_218 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2368h
Figure 8-756 DDRSS_PI_218 Register
3130292827262524
PI_TWR_F0
R/W-0h
2322212019181716
RESERVEDPI_TWTR_F0
R/W-XR/W-0h
15141312111098
PI_TRCD_F0
R/W-0h
76543210
PI_TRP_F0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1522 DDRSS_PI_218 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TWR_F0R/W0h

DRAM tWR value in cycles for frequency set 0.

23-22RESERVEDR/WX
21-16PI_TWTR_F0R/W0h

DRAM tWTR value in cycles for frequency set 0.

15-8PI_TRCD_F0R/W0h

DRAM tRCD value in cycles for frequency set 0.

7-0PI_TRP_F0R/W0h

DRAM tRP value in cycles for frequency set 0.

2.5.3.220 DDRSS_PI_219 Register (Offset = 236Ch) [reset = X]

DDRSS_PI_219 is shown in Figure 8-757 and described in Table 8-1524.

Return to Summary Table.

Table 8-1523 DDRSS_PI_219 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 236Ch
Figure 8-757 DDRSS_PI_219 Register
31302928272625242322212019181716
PI_TRAS_MIN_F0RESERVEDPI_TRAS_MAX_F0
R/W-0hR/W-XR/W-0h
1514131211109876543210
PI_TRAS_MAX_F0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1524 DDRSS_PI_219 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TRAS_MIN_F0R/W0h

DRAM tRAS_MIN value in cycles for frequency set 0.

23-17RESERVEDR/WX
16-0PI_TRAS_MAX_F0R/W0h

DRAM tRAS_MAX value in cycles for frequency set 0.

2.5.3.221 DDRSS_PI_220 Register (Offset = 2370h) [reset = X]

DDRSS_PI_220 is shown in Figure 8-758 and described in Table 8-1526.

Return to Summary Table.

Table 8-1525 DDRSS_PI_220 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2370h
Figure 8-758 DDRSS_PI_220 Register
3130292827262524
PI_TMRD_F0
R/W-0h
2322212019181716
PI_TSR_F0
R/W-0h
15141312111098
RESERVEDPI_TCCDMW_F0
R/W-XR/W-0h
76543210
RESERVEDPI_TDQSCK_MAX_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1526 DDRSS_PI_220 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TMRD_F0R/W0h

DRAM tMRD value in cycles for frequency set 0.

23-16PI_TSR_F0R/W0h

Min cycles from sref entry to sref exit for frequency set 0.

15-14RESERVEDR/WX
13-8PI_TCCDMW_F0R/W0h

LPDDR4 DRAM tCCDMW in cycles for frequency set 0.

7-4RESERVEDR/WX
3-0PI_TDQSCK_MAX_F0R/W0h

Additional delay needed for tDQSCK for frequency set 0.

2.5.3.222 DDRSS_PI_221 Register (Offset = 2374h) [reset = 0h]

DDRSS_PI_221 is shown in Figure 8-759 and described in Table 8-1528.

Return to Summary Table.

Table 8-1527 DDRSS_PI_221 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2374h
Figure 8-759 DDRSS_PI_221 Register
31302928272625242322212019181716
PI_TRCD_F1PI_TRP_F1
R/W-0hR/W-0h
1514131211109876543210
PI_TRTP_F1PI_TMRW_F0
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1528 DDRSS_PI_221 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TRCD_F1R/W0h

DRAM tRCD value in cycles for frequency set 1.

23-16PI_TRP_F1R/W0h

DRAM tRP value in cycles for frequency set 1.

15-8PI_TRTP_F1R/W0h

DRAM tRTP value in cycles for frequency set 1.

7-0PI_TMRW_F0R/W0h

DRAM tMRW value in cycles for frequency set 0.

2.5.3.223 DDRSS_PI_222 Register (Offset = 2378h) [reset = X]

DDRSS_PI_222 is shown in Figure 8-760 and described in Table 8-1530.

Return to Summary Table.

Table 8-1529 DDRSS_PI_222 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2378h
Figure 8-760 DDRSS_PI_222 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
PI_TWR_F1
R/W-0h
76543210
RESERVEDPI_TWTR_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1530 DDRSS_PI_222 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/WX
15-8PI_TWR_F1R/W0h

DRAM tWR value in cycles for frequency set 1.

7-6RESERVEDR/WX
5-0PI_TWTR_F1R/W0h

DRAM tWTR value in cycles for frequency set 1.

2.5.3.224 DDRSS_PI_223 Register (Offset = 237Ch) [reset = X]

DDRSS_PI_223 is shown in Figure 8-761 and described in Table 8-1532.

Return to Summary Table.

Table 8-1531 DDRSS_PI_223 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 237Ch
Figure 8-761 DDRSS_PI_223 Register
31302928272625242322212019181716
PI_TRAS_MIN_F1RESERVEDPI_TRAS_MAX_F1
R/W-0hR/W-XR/W-0h
1514131211109876543210
PI_TRAS_MAX_F1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1532 DDRSS_PI_223 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TRAS_MIN_F1R/W0h

DRAM tRAS_MIN value in cycles for frequency set 1.

23-17RESERVEDR/WX
16-0PI_TRAS_MAX_F1R/W0h

DRAM tRAS_MAX value in cycles for frequency set 1.

2.5.3.225 DDRSS_PI_224 Register (Offset = 2380h) [reset = X]

DDRSS_PI_224 is shown in Figure 8-762 and described in Table 8-1534.

Return to Summary Table.

Table 8-1533 DDRSS_PI_224 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2380h
Figure 8-762 DDRSS_PI_224 Register
3130292827262524
PI_TMRD_F1
R/W-0h
2322212019181716
PI_TSR_F1
R/W-0h
15141312111098
RESERVEDPI_TCCDMW_F1
R/W-XR/W-0h
76543210
RESERVEDPI_TDQSCK_MAX_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1534 DDRSS_PI_224 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TMRD_F1R/W0h

DRAM tMRD value in cycles for frequency set 1.

23-16PI_TSR_F1R/W0h

Min cycles from sref entry to sref exit for frequency set 1.

15-14RESERVEDR/WX
13-8PI_TCCDMW_F1R/W0h

LPDDR4 DRAM tCCDMW in cycles for frequency set 1.

7-4RESERVEDR/WX
3-0PI_TDQSCK_MAX_F1R/W0h

Additional delay needed for tDQSCK for frequency set 1.

2.5.3.226 DDRSS_PI_225 Register (Offset = 2384h) [reset = 0h]

DDRSS_PI_225 is shown in Figure 8-763 and described in Table 8-1536.

Return to Summary Table.

Table 8-1535 DDRSS_PI_225 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2384h
Figure 8-763 DDRSS_PI_225 Register
31302928272625242322212019181716
PI_TRCD_F2PI_TRP_F2
R/W-0hR/W-0h
1514131211109876543210
PI_TRTP_F2PI_TMRW_F1
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1536 DDRSS_PI_225 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TRCD_F2R/W0h

DRAM tRCD value in cycles for frequency set 2.

23-16PI_TRP_F2R/W0h

DRAM tRP value in cycles for frequency set 2.

15-8PI_TRTP_F2R/W0h

DRAM tRTP value in cycles for frequency set 2.

7-0PI_TMRW_F1R/W0h

DRAM tMRW value in cycles for frequency set 1.

2.5.3.227 DDRSS_PI_226 Register (Offset = 2388h) [reset = X]

DDRSS_PI_226 is shown in Figure 8-764 and described in Table 8-1538.

Return to Summary Table.

Table 8-1537 DDRSS_PI_226 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2388h
Figure 8-764 DDRSS_PI_226 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVED
R/W-X
15141312111098
PI_TWR_F2
R/W-0h
76543210
RESERVEDPI_TWTR_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1538 DDRSS_PI_226 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/WX
15-8PI_TWR_F2R/W0h

DRAM tWR value in cycles for frequency set 2.

7-6RESERVEDR/WX
5-0PI_TWTR_F2R/W0h

DRAM tWTR value in cycles for frequency set 2.

2.5.3.228 DDRSS_PI_227 Register (Offset = 238Ch) [reset = X]

DDRSS_PI_227 is shown in Figure 8-765 and described in Table 8-1540.

Return to Summary Table.

Table 8-1539 DDRSS_PI_227 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 238Ch
Figure 8-765 DDRSS_PI_227 Register
31302928272625242322212019181716
PI_TRAS_MIN_F2RESERVEDPI_TRAS_MAX_F2
R/W-0hR/W-XR/W-0h
1514131211109876543210
PI_TRAS_MAX_F2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1540 DDRSS_PI_227 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TRAS_MIN_F2R/W0h

DRAM tRAS_MIN value in cycles for frequency set 2.

23-17RESERVEDR/WX
16-0PI_TRAS_MAX_F2R/W0h

DRAM tRAS_MAX value in cycles for frequency set 2.

2.5.3.229 DDRSS_PI_228 Register (Offset = 2390h) [reset = X]

DDRSS_PI_228 is shown in Figure 8-766 and described in Table 8-1542.

Return to Summary Table.

Table 8-1541 DDRSS_PI_228 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2390h
Figure 8-766 DDRSS_PI_228 Register
3130292827262524
PI_TMRD_F2
R/W-0h
2322212019181716
PI_TSR_F2
R/W-0h
15141312111098
RESERVEDPI_TCCDMW_F2
R/W-XR/W-0h
76543210
RESERVEDPI_TDQSCK_MAX_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1542 DDRSS_PI_228 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_TMRD_F2R/W0h

DRAM tMRD value in cycles for frequency set 2.

23-16PI_TSR_F2R/W0h

Min cycles from sref entry to sref exit for frequency set 2.

15-14RESERVEDR/WX
13-8PI_TCCDMW_F2R/W0h

LPDDR4 DRAM tCCDMW in cycles for frequency set 2.

7-4RESERVEDR/WX
3-0PI_TDQSCK_MAX_F2R/W0h

Additional delay needed for tDQSCK for frequency set 2.

2.5.3.230 DDRSS_PI_229 Register (Offset = 2394h) [reset = X]

DDRSS_PI_229 is shown in Figure 8-767 and described in Table 8-1544.

Return to Summary Table.

Table 8-1543 DDRSS_PI_229 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2394h
Figure 8-767 DDRSS_PI_229 Register
31302928272625242322212019181716
RESERVEDPI_TDFI_CTRLUPD_MAX_F0
R/W-XR/W-0h
1514131211109876543210
PI_TDFI_CTRLUPD_MAX_F0PI_TMRW_F2
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1544 DDRSS_PI_229 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR/WX
28-8PI_TDFI_CTRLUPD_MAX_F0R/W0h

Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks) for frequency set 0, the maximum cycles that dfi_ctrlupd_req can be asserted.
If programmed to a non-zero, a timing violation will cause an interrupt and bit (1) set in the PI_UPDATE_ERROR_STATUS parameter.

7-0PI_TMRW_F2R/W0h

DRAM tMRW value in cycles for frequency set 2.

2.5.3.231 DDRSS_PI_230 Register (Offset = 2398h) [reset = 0h]

DDRSS_PI_230 is shown in Figure 8-768 and described in Table 8-1546.

Return to Summary Table.

Table 8-1545 DDRSS_PI_230 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2398h
Figure 8-768 DDRSS_PI_230 Register
313029282726252423222120191817161514131211109876543210
PI_TDFI_CTRLUPD_INTERVAL_F0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1546 DDRSS_PI_230 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TDFI_CTRLUPD_INTERVAL_F0R/W0h

Defines the DFI tCTRLUPD_INTERVAL timing parameter (in DFI clocks) for frequency set 0, the maximum cycles between dfi_ctrlupd_req assertions.
If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PI_UPDATE_ERROR_STATUS parameter.

2.5.3.232 DDRSS_PI_231 Register (Offset = 239Ch) [reset = X]

DDRSS_PI_231 is shown in Figure 8-769 and described in Table 8-1548.

Return to Summary Table.

Table 8-1547 DDRSS_PI_231 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 239Ch
Figure 8-769 DDRSS_PI_231 Register
31302928272625242322212019181716
RESERVEDPI_TDFI_CTRLUPD_MAX_F1
R/W-XR/W-0h
1514131211109876543210
PI_TDFI_CTRLUPD_MAX_F1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1548 DDRSS_PI_231 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR/WX
20-0PI_TDFI_CTRLUPD_MAX_F1R/W0h

Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks) for frequency set 1, the maximum cycles that dfi_ctrlupd_req can be asserted.
If programmed to a non-zero, a timing violation will cause an interrupt and bit (1) set in the PI_UPDATE_ERROR_STATUS parameter.

2.5.3.233 DDRSS_PI_232 Register (Offset = 23A0h) [reset = 0h]

DDRSS_PI_232 is shown in Figure 8-770 and described in Table 8-1550.

Return to Summary Table.

Table 8-1549 DDRSS_PI_232 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23A0h
Figure 8-770 DDRSS_PI_232 Register
313029282726252423222120191817161514131211109876543210
PI_TDFI_CTRLUPD_INTERVAL_F1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1550 DDRSS_PI_232 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TDFI_CTRLUPD_INTERVAL_F1R/W0h

Defines the DFI tCTRLUPD_INTERVAL timing parameter (in DFI clocks) for frequency set 1, the maximum cycles between dfi_ctrlupd_req assertions.
If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PI_UPDATE_ERROR_STATUS parameter.

2.5.3.234 DDRSS_PI_233 Register (Offset = 23A4h) [reset = X]

DDRSS_PI_233 is shown in Figure 8-771 and described in Table 8-1552.

Return to Summary Table.

Table 8-1551 DDRSS_PI_233 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23A4h
Figure 8-771 DDRSS_PI_233 Register
31302928272625242322212019181716
RESERVEDPI_TDFI_CTRLUPD_MAX_F2
R/W-XR/W-0h
1514131211109876543210
PI_TDFI_CTRLUPD_MAX_F2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1552 DDRSS_PI_233 Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR/WX
20-0PI_TDFI_CTRLUPD_MAX_F2R/W0h

Defines the DFI tCTRLUPD_MAX timing parameter (in DFI clocks) for frequency set 2, the maximum cycles that dfi_ctrlupd_req can be asserted.
If programmed to a non-zero, a timing violation will cause an interrupt and bit (1) set in the PI_UPDATE_ERROR_STATUS parameter.

2.5.3.235 DDRSS_PI_234 Register (Offset = 23A8h) [reset = 0h]

DDRSS_PI_234 is shown in Figure 8-772 and described in Table 8-1554.

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Table 8-1553 DDRSS_PI_234 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23A8h
Figure 8-772 DDRSS_PI_234 Register
313029282726252423222120191817161514131211109876543210
PI_TDFI_CTRLUPD_INTERVAL_F2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1554 DDRSS_PI_234 Register Field Descriptions
BitFieldTypeResetDescription
31-0PI_TDFI_CTRLUPD_INTERVAL_F2R/W0h

Defines the DFI tCTRLUPD_INTERVAL timing parameter (in DFI clocks) for frequency set 2, the maximum cycles between dfi_ctrlupd_req assertions.
If programmed to a non-zero, a timing violation will cause an interrupt and bit (0) set in the PI_UPDATE_ERROR_STATUS parameter.

2.5.3.236 DDRSS_PI_235 Register (Offset = 23ACh) [reset = 0h]

DDRSS_PI_235 is shown in Figure 8-773 and described in Table 8-1556.

Return to Summary Table.

Table 8-1555 DDRSS_PI_235 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23ACh
Figure 8-773 DDRSS_PI_235 Register
313029282726252423222120191817161514131211109876543210
PI_TXSR_F1PI_TXSR_F0
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1556 DDRSS_PI_235 Register Field Descriptions
BitFieldTypeResetDescription
31-16PI_TXSR_F1R/W0h

DRAM TXSR value for frequency set 1 in cycles.

15-0PI_TXSR_F0R/W0h

DRAM TXSR value for frequency set 0 in cycles.

2.5.3.237 DDRSS_PI_236 Register (Offset = 23B0h) [reset = X]

DDRSS_PI_236 is shown in Figure 8-774 and described in Table 8-1558.

Return to Summary Table.

Table 8-1557 DDRSS_PI_236 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23B0h
Figure 8-774 DDRSS_PI_236 Register
3130292827262524
RESERVEDPI_TEXCKE_F1
R/W-XR/W-0h
2322212019181716
RESERVEDPI_TEXCKE_F0
R/W-XR/W-0h
15141312111098
PI_TXSR_F2
R/W-0h
76543210
PI_TXSR_F2
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1558 DDRSS_PI_236 Register Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR/WX
29-24PI_TEXCKE_F1R/W0h

DRAM CKE low after SREF command timing for frequency set 1.

23-22RESERVEDR/WX
21-16PI_TEXCKE_F0R/W0h

DRAM CKE low after SREF command timing for frequency set 0.

15-0PI_TXSR_F2R/W0h

DRAM TXSR value for frequency set 2 in cycles.

2.5.3.238 DDRSS_PI_237 Register (Offset = 23B4h) [reset = X]

DDRSS_PI_237 is shown in Figure 8-775 and described in Table 8-1560.

Return to Summary Table.

Table 8-1559 DDRSS_PI_237 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23B4h
Figure 8-775 DDRSS_PI_237 Register
3130292827262524
PI_TINIT_F0
R/W-0h
2322212019181716
PI_TINIT_F0
R/W-0h
15141312111098
PI_TINIT_F0
R/W-0h
76543210
RESERVEDPI_TEXCKE_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1560 DDRSS_PI_237 Register Field Descriptions
BitFieldTypeResetDescription
31-8PI_TINIT_F0R/W0h

DRAM tINIT value for frequency set 0 in cycles.

7-6RESERVEDR/WX
5-0PI_TEXCKE_F2R/W0h

DRAM CKE low after SREF command timing for frequency set 2.

2.5.3.239 DDRSS_PI_238 Register (Offset = 23B8h) [reset = X]

DDRSS_PI_238 is shown in Figure 8-776 and described in Table 8-1562.

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Table 8-1561 DDRSS_PI_238 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23B8h
Figure 8-776 DDRSS_PI_238 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TINIT3_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1562 DDRSS_PI_238 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-0PI_TINIT3_F0R/W0h

DRAM tINIT3 value for frequency set 0 in cycles.

2.5.3.240 DDRSS_PI_239 Register (Offset = 23BCh) [reset = X]

DDRSS_PI_239 is shown in Figure 8-777 and described in Table 8-1564.

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Table 8-1563 DDRSS_PI_239 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23BCh
Figure 8-777 DDRSS_PI_239 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TINIT4_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1564 DDRSS_PI_239 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-0PI_TINIT4_F0R/W0h

DRAM tINIT4 value for frequency set 0 in cycles.

2.5.3.241 DDRSS_PI_240 Register (Offset = 23C0h) [reset = X]

DDRSS_PI_240 is shown in Figure 8-778 and described in Table 8-1566.

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Table 8-1565 DDRSS_PI_240 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23C0h
Figure 8-778 DDRSS_PI_240 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TINIT5_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1566 DDRSS_PI_240 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-0PI_TINIT5_F0R/W0h

DRAM tINIT5 value for frequency set 0 in cycles.

2.5.3.242 DDRSS_PI_241 Register (Offset = 23C4h) [reset = X]

DDRSS_PI_241 is shown in Figure 8-779 and described in Table 8-1568.

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Table 8-1567 DDRSS_PI_241 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23C4h
Figure 8-779 DDRSS_PI_241 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TXSNR_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1568 DDRSS_PI_241 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/WX
15-0PI_TXSNR_F0R/W0h

DRAM tXSNR value for frequency set 0 in cycles.

2.5.3.243 DDRSS_PI_242 Register (Offset = 23C8h) [reset = X]

DDRSS_PI_242 is shown in Figure 8-780 and described in Table 8-1570.

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Table 8-1569 DDRSS_PI_242 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23C8h
Figure 8-780 DDRSS_PI_242 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TINIT_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1570 DDRSS_PI_242 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-0PI_TINIT_F1R/W0h

DRAM tINIT value for frequency set 1 in cycles.

2.5.3.244 DDRSS_PI_243 Register (Offset = 23CCh) [reset = X]

DDRSS_PI_243 is shown in Figure 8-781 and described in Table 8-1572.

Return to Summary Table.

Table 8-1571 DDRSS_PI_243 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23CCh
Figure 8-781 DDRSS_PI_243 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TINIT3_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1572 DDRSS_PI_243 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-0PI_TINIT3_F1R/W0h

DRAM tINIT3 value for frequency set 1 in cycles.

2.5.3.245 DDRSS_PI_244 Register (Offset = 23D0h) [reset = X]

DDRSS_PI_244 is shown in Figure 8-782 and described in Table 8-1574.

Return to Summary Table.

Table 8-1573 DDRSS_PI_244 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23D0h
Figure 8-782 DDRSS_PI_244 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TINIT4_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1574 DDRSS_PI_244 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-0PI_TINIT4_F1R/W0h

DRAM tINIT4 value for frequency set 1 in cycles.

2.5.3.246 DDRSS_PI_245 Register (Offset = 23D4h) [reset = X]

DDRSS_PI_245 is shown in Figure 8-783 and described in Table 8-1576.

Return to Summary Table.

Table 8-1575 DDRSS_PI_245 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23D4h
Figure 8-783 DDRSS_PI_245 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TINIT5_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1576 DDRSS_PI_245 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-0PI_TINIT5_F1R/W0h

DRAM tINIT5 value for frequency set 1 in cycles.

2.5.3.247 DDRSS_PI_246 Register (Offset = 23D8h) [reset = X]

DDRSS_PI_246 is shown in Figure 8-784 and described in Table 8-1578.

Return to Summary Table.

Table 8-1577 DDRSS_PI_246 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23D8h
Figure 8-784 DDRSS_PI_246 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TXSNR_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1578 DDRSS_PI_246 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR/WX
15-0PI_TXSNR_F1R/W0h

DRAM tXSNR value for frequency set 1 in cycles.

2.5.3.248 DDRSS_PI_247 Register (Offset = 23DCh) [reset = X]

DDRSS_PI_247 is shown in Figure 8-785 and described in Table 8-1580.

Return to Summary Table.

Table 8-1579 DDRSS_PI_247 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23DCh
Figure 8-785 DDRSS_PI_247 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TINIT_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1580 DDRSS_PI_247 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-0PI_TINIT_F2R/W0h

DRAM tINIT value for frequency set 2 in cycles.

2.5.3.249 DDRSS_PI_248 Register (Offset = 23E0h) [reset = X]

DDRSS_PI_248 is shown in Figure 8-786 and described in Table 8-1582.

Return to Summary Table.

Table 8-1581 DDRSS_PI_248 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23E0h
Figure 8-786 DDRSS_PI_248 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TINIT3_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1582 DDRSS_PI_248 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-0PI_TINIT3_F2R/W0h

DRAM tINIT3 value for frequency set 2 in cycles.

2.5.3.250 DDRSS_PI_249 Register (Offset = 23E4h) [reset = X]

DDRSS_PI_249 is shown in Figure 8-787 and described in Table 8-1584.

Return to Summary Table.

Table 8-1583 DDRSS_PI_249 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23E4h
Figure 8-787 DDRSS_PI_249 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TINIT4_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1584 DDRSS_PI_249 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-0PI_TINIT4_F2R/W0h

DRAM tINIT4 value for frequency set 2 in cycles.

2.5.3.251 DDRSS_PI_250 Register (Offset = 23E8h) [reset = X]

DDRSS_PI_250 is shown in Figure 8-788 and described in Table 8-1586.

Return to Summary Table.

Table 8-1585 DDRSS_PI_250 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23E8h
Figure 8-788 DDRSS_PI_250 Register
313029282726252423222120191817161514131211109876543210
RESERVEDPI_TINIT5_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1586 DDRSS_PI_250 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR/WX
23-0PI_TINIT5_F2R/W0h

DRAM tINIT5 value for frequency set 2 in cycles.

2.5.3.252 DDRSS_PI_251 Register (Offset = 23ECh) [reset = X]

DDRSS_PI_251 is shown in Figure 8-789 and described in Table 8-1588.

Return to Summary Table.

Table 8-1587 DDRSS_PI_251 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23ECh
Figure 8-789 DDRSS_PI_251 Register
313029282726252423222120191817161514131211109876543210
RESERVEDRESERVEDPI_TXSNR_F2
R/W-XR/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1588 DDRSS_PI_251 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-16RESERVEDR/W0h

Reserved

15-0PI_TXSNR_F2R/W0h

DRAM tXSNR value for frequency set 2 in cycles.

2.5.3.253 DDRSS_PI_252 Register (Offset = 23F0h) [reset = X]

DDRSS_PI_252 is shown in Figure 8-790 and described in Table 8-1590.

Return to Summary Table.

Table 8-1589 DDRSS_PI_252 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23F0h
Figure 8-790 DDRSS_PI_252 Register
31302928272625242322212019181716
RESERVEDPI_TZQCAL_F0
R/W-XR/W-0h
1514131211109876543210
RESERVEDRESERVED
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1590 DDRSS_PI_252 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-16PI_TZQCAL_F0R/W0h

Holds the DRAM ZQCAL value for frequency set 0 in cycles.

15-12RESERVEDR/WX
11-0RESERVEDR/W0h

Reserved

2.5.3.254 DDRSS_PI_253 Register (Offset = 23F4h) [reset = X]

DDRSS_PI_253 is shown in Figure 8-791 and described in Table 8-1592.

Return to Summary Table.

Table 8-1591 DDRSS_PI_253 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23F4h
Figure 8-791 DDRSS_PI_253 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDRESERVED
R/W-XR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDPI_TZQLAT_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1592 DDRSS_PI_253 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/WX
19-8RESERVEDR/W0h

Reserved

7RESERVEDR/WX
6-0PI_TZQLAT_F0R/W0h

Holds the DRAM ZQLAT value for frequency set 0 in cycles.

2.5.3.255 DDRSS_PI_254 Register (Offset = 23F8h) [reset = X]

DDRSS_PI_254 is shown in Figure 8-792 and described in Table 8-1594.

Return to Summary Table.

Table 8-1593 DDRSS_PI_254 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23F8h
Figure 8-792 DDRSS_PI_254 Register
31302928272625242322212019181716
RESERVEDPI_TZQCAL_F1
R/W-XR/W-0h
1514131211109876543210
RESERVEDRESERVED
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1594 DDRSS_PI_254 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-16PI_TZQCAL_F1R/W0h

Holds the DRAM ZQCAL value for frequency set 1 in cycles.

15-12RESERVEDR/WX
11-0RESERVEDR/W0h

Reserved

2.5.3.256 DDRSS_PI_255 Register (Offset = 23FCh) [reset = X]

DDRSS_PI_255 is shown in Figure 8-793 and described in Table 8-1596.

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Table 8-1595 DDRSS_PI_255 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 23FCh
Figure 8-793 DDRSS_PI_255 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDRESERVED
R/W-XR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDPI_TZQLAT_F1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1596 DDRSS_PI_255 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/WX
19-8RESERVEDR/W0h

Reserved

7RESERVEDR/WX
6-0PI_TZQLAT_F1R/W0h

Holds the DRAM ZQLAT value for frequency set 1 in cycles.

2.5.3.257 DDRSS_PI_256 Register (Offset = 2400h) [reset = X]

DDRSS_PI_256 is shown in Figure 8-794 and described in Table 8-1598.

Return to Summary Table.

Table 8-1597 DDRSS_PI_256 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2400h
Figure 8-794 DDRSS_PI_256 Register
31302928272625242322212019181716
RESERVEDPI_TZQCAL_F2
R/W-XR/W-0h
1514131211109876543210
RESERVEDRESERVED
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1598 DDRSS_PI_256 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-16PI_TZQCAL_F2R/W0h

Holds the DRAM ZQCAL value for frequency set 2 in cycles.

15-12RESERVEDR/WX
11-0RESERVEDR/W0h

Reserved

2.5.3.258 DDRSS_PI_257 Register (Offset = 2404h) [reset = X]

DDRSS_PI_257 is shown in Figure 8-795 and described in Table 8-1600.

Return to Summary Table.

Table 8-1599 DDRSS_PI_257 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2404h
Figure 8-795 DDRSS_PI_257 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDRESERVED
R/W-XR/W-0h
15141312111098
RESERVED
R/W-0h
76543210
RESERVEDPI_TZQLAT_F2
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1600 DDRSS_PI_257 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/WX
19-8RESERVEDR/W0h

Reserved

7RESERVEDR/WX
6-0PI_TZQLAT_F2R/W0h

Holds the DRAM ZQLAT value for frequency set 2 in cycles.

2.5.3.259 DDRSS_PI_258 Register (Offset = 2408h) [reset = X]

DDRSS_PI_258 is shown in Figure 8-796 and described in Table 8-1602.

Return to Summary Table.

Table 8-1601 DDRSS_PI_258 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2408h
Figure 8-796 DDRSS_PI_258 Register
31302928272625242322212019181716
RESERVEDRESERVED
R/W-XR/W-0h
1514131211109876543210
RESERVEDRESERVED
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1602 DDRSS_PI_258 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-16RESERVEDR/W0h

Reserved

15-12RESERVEDR/WX
11-0RESERVEDR/W0h

Reserved

2.5.3.260 DDRSS_PI_259 Register (Offset = 240Ch) [reset = X]

DDRSS_PI_259 is shown in Figure 8-797 and described in Table 8-1604.

Return to Summary Table.

Table 8-1603 DDRSS_PI_259 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 240Ch
Figure 8-797 DDRSS_PI_259 Register
3130292827262524
PI_MR13_DATA_0
R/W-0h
2322212019181716
RESERVEDPI_WDQ_OSC_DELTA_INDEX_F2
R/W-XR/W-0h
15141312111098
RESERVEDPI_WDQ_OSC_DELTA_INDEX_F1
R/W-XR/W-0h
76543210
RESERVEDPI_WDQ_OSC_DELTA_INDEX_F0
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1604 DDRSS_PI_259 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR13_DATA_0R/W0h

Data to program into memory mode register 13 for chip select 0.

23-20RESERVEDR/WX
19-16PI_WDQ_OSC_DELTA_INDEX_F2R/W0h

WDQ DQS delay delta index for OSC triggered periodic training for frequency set 2.
If the value is n, the delay is 2n/512 cycle.

15-12RESERVEDR/WX
11-8PI_WDQ_OSC_DELTA_INDEX_F1R/W0h

WDQ DQS delay delta index for OSC triggered periodic training for frequency set 1.
If the value is n, the delay is 2n/512 cycle.

7-4RESERVEDR/WX
3-0PI_WDQ_OSC_DELTA_INDEX_F0R/W0h

WDQ DQS delay delta index for OSC triggered periodic training for frequency set 0.
If the value is n, the delay is 2n/512 cycle.

2.5.3.261 DDRSS_PI_260 Register (Offset = 2410h) [reset = 0h]

DDRSS_PI_260 is shown in Figure 8-798 and described in Table 8-1606.

Return to Summary Table.

Table 8-1605 DDRSS_PI_260 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2410h
Figure 8-798 DDRSS_PI_260 Register
31302928272625242322212019181716
PI_MR20_DATA_0PI_MR17_DATA_0
R/W-0hR/W-0h
1514131211109876543210
PI_MR16_DATA_0PI_MR15_DATA_0
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1606 DDRSS_PI_260 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR20_DATA_0R/W0h

Data to program into memory mode register 20 for chip select 0.

23-16PI_MR17_DATA_0R/W0h

Data to program into memory mode register 17 for chip select 0.

15-8PI_MR16_DATA_0R/W0h

Data to program into memory mode register 16 for chip select 0.

7-0PI_MR15_DATA_0R/W0h

Data to program into memory mode register 15 for chip select 0.

2.5.3.262 DDRSS_PI_261 Register (Offset = 2414h) [reset = 0h]

DDRSS_PI_261 is shown in Figure 8-799 and described in Table 8-1608.

Return to Summary Table.

Table 8-1607 DDRSS_PI_261 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2414h
Figure 8-799 DDRSS_PI_261 Register
31302928272625242322212019181716
PI_MR15_DATA_1PI_MR13_DATA_1
R/W-0hR/W-0h
1514131211109876543210
PI_MR40_DATA_0PI_MR32_DATA_0
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1608 DDRSS_PI_261 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR15_DATA_1R/W0h

Data to program into memory mode register 15 for chip select 1.

23-16PI_MR13_DATA_1R/W0h

Data to program into memory mode register 13 for chip select 1.

15-8PI_MR40_DATA_0R/W0h

Data to program into memory mode register 40 for chip select 0.

7-0PI_MR32_DATA_0R/W0h

Data to program into memory mode register 32 for chip select 0.

2.5.3.263 DDRSS_PI_262 Register (Offset = 2418h) [reset = 0h]

DDRSS_PI_262 is shown in Figure 8-800 and described in Table 8-1610.

Return to Summary Table.

Table 8-1609 DDRSS_PI_262 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2418h
Figure 8-800 DDRSS_PI_262 Register
31302928272625242322212019181716
PI_MR32_DATA_1PI_MR20_DATA_1
R/W-0hR/W-0h
1514131211109876543210
PI_MR17_DATA_1PI_MR16_DATA_1
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1610 DDRSS_PI_262 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR32_DATA_1R/W0h

Data to program into memory mode register 32 for chip select 1.

23-16PI_MR20_DATA_1R/W0h

Data to program into memory mode register 20 for chip select 1.

15-8PI_MR17_DATA_1R/W0h

Data to program into memory mode register 17 for chip select 1.

7-0PI_MR16_DATA_1R/W0h

Data to program into memory mode register 16 for chip select 1.

2.5.3.264 DDRSS_PI_263 Register (Offset = 241Ch) [reset = 0h]

DDRSS_PI_263 is shown in Figure 8-801 and described in Table 8-1612.

Return to Summary Table.

Table 8-1611 DDRSS_PI_263 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 241Ch
Figure 8-801 DDRSS_PI_263 Register
31302928272625242322212019181716
PI_MR16_DATA_2PI_MR15_DATA_2
R/W-0hR/W-0h
1514131211109876543210
PI_MR13_DATA_2PI_MR40_DATA_1
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1612 DDRSS_PI_263 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR16_DATA_2R/W0h

Data to program into memory mode register 16 for chip select 2.

23-16PI_MR15_DATA_2R/W0h

Data to program into memory mode register 15 for chip select 2.

15-8PI_MR13_DATA_2R/W0h

Data to program into memory mode register 13 for chip select 2.

7-0PI_MR40_DATA_1R/W0h

Data to program into memory mode register 40 for chip select 1.

2.5.3.265 DDRSS_PI_264 Register (Offset = 2420h) [reset = 0h]

DDRSS_PI_264 is shown in Figure 8-802 and described in Table 8-1614.

Return to Summary Table.

Table 8-1613 DDRSS_PI_264 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2420h
Figure 8-802 DDRSS_PI_264 Register
31302928272625242322212019181716
PI_MR40_DATA_2PI_MR32_DATA_2
R/W-0hR/W-0h
1514131211109876543210
PI_MR20_DATA_2PI_MR17_DATA_2
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1614 DDRSS_PI_264 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR40_DATA_2R/W0h

Data to program into memory mode register 40 for chip select 2.

23-16PI_MR32_DATA_2R/W0h

Data to program into memory mode register 32 for chip select 2.

15-8PI_MR20_DATA_2R/W0h

Data to program into memory mode register 20 for chip select 2.

7-0PI_MR17_DATA_2R/W0h

Data to program into memory mode register 17 for chip select 2.

2.5.3.266 DDRSS_PI_265 Register (Offset = 2424h) [reset = 0h]

DDRSS_PI_265 is shown in Figure 8-803 and described in Table 8-1616.

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Table 8-1615 DDRSS_PI_265 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2424h
Figure 8-803 DDRSS_PI_265 Register
31302928272625242322212019181716
PI_MR17_DATA_3PI_MR16_DATA_3
R/W-0hR/W-0h
1514131211109876543210
PI_MR15_DATA_3PI_MR13_DATA_3
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1616 DDRSS_PI_265 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR17_DATA_3R/W0h

Data to program into memory mode register 17 for chip select 3.

23-16PI_MR16_DATA_3R/W0h

Data to program into memory mode register 16 for chip select 3.

15-8PI_MR15_DATA_3R/W0h

Data to program into memory mode register 15 for chip select 3.

7-0PI_MR13_DATA_3R/W0h

Data to program into memory mode register 13 for chip select 3.

2.5.3.267 DDRSS_PI_266 Register (Offset = 2428h) [reset = X]

DDRSS_PI_266 is shown in Figure 8-804 and described in Table 8-1618.

Return to Summary Table.

Table 8-1617 DDRSS_PI_266 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2428h
Figure 8-804 DDRSS_PI_266 Register
31302928272625242322212019181716
RESERVEDPI_CKE_MUX_0PI_MR40_DATA_3
R/W-XR/W-0hR/W-0h
1514131211109876543210
PI_MR32_DATA_3PI_MR20_DATA_3
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1618 DDRSS_PI_266 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_CKE_MUX_0R/W0h

Command pin CKE_0 mux selector

23-16PI_MR40_DATA_3R/W0h

Data to program into memory mode register 40 for chip select 3.

15-8PI_MR32_DATA_3R/W0h

Data to program into memory mode register 32 for chip select 3.

7-0PI_MR20_DATA_3R/W0h

Data to program into memory mode register 20 for chip select 3.

2.5.3.268 DDRSS_PI_267 Register (Offset = 242Ch) [reset = X]

DDRSS_PI_267 is shown in Figure 8-805 and described in Table 8-1620.

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Table 8-1619 DDRSS_PI_267 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 242Ch
Figure 8-805 DDRSS_PI_267 Register
31302928272625242322212019181716
RESERVEDPI_CS_MUX_0RESERVEDPI_CKE_MUX_3
R/W-XR/W-0hR/W-XR/W-0h
1514131211109876543210
RESERVEDPI_CKE_MUX_2RESERVEDPI_CKE_MUX_1
R/W-XR/W-0hR/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1620 DDRSS_PI_267 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_CS_MUX_0R/W0h

Command pin CS_0 mux selector

23-20RESERVEDR/WX
19-16PI_CKE_MUX_3R/W0h

Command pin CKE_3 mux selector

15-12RESERVEDR/WX
11-8PI_CKE_MUX_2R/W0h

Command pin CKE_2 mux selector

7-4RESERVEDR/WX
3-0PI_CKE_MUX_1R/W0h

Command pin CKE_1 mux selector

2.5.3.269 DDRSS_PI_268 Register (Offset = 2430h) [reset = X]

DDRSS_PI_268 is shown in Figure 8-806 and described in Table 8-1622.

Return to Summary Table.

Table 8-1621 DDRSS_PI_268 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2430h
Figure 8-806 DDRSS_PI_268 Register
3130292827262524
RESERVEDPI_RESET_N_MUX_0
R/W-XR/W-0h
2322212019181716
RESERVEDPI_CS_MUX_3
R/W-XR/W-0h
15141312111098
RESERVEDPI_CS_MUX_2
R/W-XR/W-0h
76543210
RESERVEDPI_CS_MUX_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1622 DDRSS_PI_268 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_RESET_N_MUX_0R/W0h

Command pin RESET_N_0 mux selector

23-20RESERVEDR/WX
19-16PI_CS_MUX_3R/W0h

Command pin CS_3 mux selector

15-12RESERVEDR/WX
11-8PI_CS_MUX_2R/W0h

Command pin CS_2 mux selector

7-4RESERVEDR/WX
3-0PI_CS_MUX_1R/W0h

Command pin CS_1 mux selector

2.5.3.270 DDRSS_PI_269 Register (Offset = 2434h) [reset = X]

DDRSS_PI_269 is shown in Figure 8-807 and described in Table 8-1624.

Return to Summary Table.

Table 8-1623 DDRSS_PI_269 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2434h
Figure 8-807 DDRSS_PI_269 Register
3130292827262524
PI_MRSINGLE_DATA_0
R/W-0h
2322212019181716
RESERVEDPI_RESET_N_MUX_3
R/W-XR/W-0h
15141312111098
RESERVEDPI_RESET_N_MUX_2
R/W-XR/W-0h
76543210
RESERVEDPI_RESET_N_MUX_1
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1624 DDRSS_PI_269 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MRSINGLE_DATA_0R/W0h

Data to program into memory mode register single write to chip select 0.

23-20RESERVEDR/WX
19-16PI_RESET_N_MUX_3R/W0h

Command pin RESET_N_3 mux selector

15-12RESERVEDR/WX
11-8PI_RESET_N_MUX_2R/W0h

Command pin RESET_N_2 mux selector

7-4RESERVEDR/WX
3-0PI_RESET_N_MUX_1R/W0h

Command pin RESET_N_1 mux selector

2.5.3.271 DDRSS_PI_270 Register (Offset = 2438h) [reset = X]

DDRSS_PI_270 is shown in Figure 8-808 and described in Table 8-1626.

Return to Summary Table.

Table 8-1625 DDRSS_PI_270 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2438h
Figure 8-808 DDRSS_PI_270 Register
3130292827262524
RESERVEDPI_ZQ_CAL_START_MAP_0
R/W-XR/W-1h
2322212019181716
PI_MRSINGLE_DATA_3
R/W-0h
15141312111098
PI_MRSINGLE_DATA_2
R/W-0h
76543210
PI_MRSINGLE_DATA_1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1626 DDRSS_PI_270 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_ZQ_CAL_START_MAP_0R/W1h

Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 0 of the ZQ START initialization and periodic command sequences.
Clear to all zeros for no ZQ START commands.

23-16PI_MRSINGLE_DATA_3R/W0h

Data to program into memory mode register single write to chip select 3.

15-8PI_MRSINGLE_DATA_2R/W0h

Data to program into memory mode register single write to chip select 2.

7-0PI_MRSINGLE_DATA_1R/W0h

Data to program into memory mode register single write to chip select 1.

2.5.3.272 DDRSS_PI_271 Register (Offset = 243Ch) [reset = X]

DDRSS_PI_271 is shown in Figure 8-809 and described in Table 8-1628.

Return to Summary Table.

Table 8-1627 DDRSS_PI_271 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 243Ch
Figure 8-809 DDRSS_PI_271 Register
3130292827262524
RESERVEDPI_ZQ_CAL_START_MAP_2
R/W-XR/W-4h
2322212019181716
RESERVEDPI_ZQ_CAL_LATCH_MAP_1
R/W-XR/W-2h
15141312111098
RESERVEDPI_ZQ_CAL_START_MAP_1
R/W-XR/W-2h
76543210
RESERVEDPI_ZQ_CAL_LATCH_MAP_0
R/W-XR/W-1h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1628 DDRSS_PI_271 Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR/WX
27-24PI_ZQ_CAL_START_MAP_2R/W4h

Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 2 of the ZQ START initialization and periodic command sequences.
Clear to all zeros for no ZQ START commands.

23-20RESERVEDR/WX
19-16PI_ZQ_CAL_LATCH_MAP_1R/W2h

Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 1 of the ZQ LATCH initialization and periodic command sequences.
Clear to all zeros for no ZQ LATCH commands.

15-12RESERVEDR/WX
11-8PI_ZQ_CAL_START_MAP_1R/W2h

Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 1 of the ZQ START initialization and periodic command sequences.
Clear to all zeros for no ZQ START commands.

7-4RESERVEDR/WX
3-0PI_ZQ_CAL_LATCH_MAP_0R/W1h

Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 0 of the ZQ LATCH initialization and periodic command sequences.
Clear to all zeros for no ZQ LATCH commands.

2.5.3.273 DDRSS_PI_272 Register (Offset = 2440h) [reset = X]

DDRSS_PI_272 is shown in Figure 8-810 and described in Table 8-1630.

Return to Summary Table.

Table 8-1629 DDRSS_PI_272 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2440h
Figure 8-810 DDRSS_PI_272 Register
3130292827262524
RESERVED
R/W-X
2322212019181716
RESERVEDPI_ZQ_CAL_LATCH_MAP_3
R/W-XR/W-8h
15141312111098
RESERVEDPI_ZQ_CAL_START_MAP_3
R/W-XR/W-8h
76543210
RESERVEDPI_ZQ_CAL_LATCH_MAP_2
R/W-XR/W-4h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1630 DDRSS_PI_272 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR/WX
19-16PI_ZQ_CAL_LATCH_MAP_3R/W8h

Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 3 of the ZQ LATCH initialization and periodic command sequences.
Clear to all zeros for no ZQ LATCH commands.

15-12RESERVEDR/WX
11-8PI_ZQ_CAL_START_MAP_3R/W8h

Defines which chip select(s) will receive ZQ calibration start commands simultaneously on iteration 3 of the ZQ START initialization and periodic command sequences.
Clear to all zeros for no ZQ START commands.

7-4RESERVEDR/WX
3-0PI_ZQ_CAL_LATCH_MAP_2R/W4h

Defines which chip select(s) will receive ZQ calibration latch commands simultaneously on iteration 2 of the ZQ LATCH initialization and periodic command sequences.
Clear to all zeros for no ZQ LATCH commands.

2.5.3.274 DDRSS_PI_273 Register (Offset = 2444h) [reset = 0h]

DDRSS_PI_273 is shown in Figure 8-811 and described in Table 8-1632.

Return to Summary Table.

Table 8-1631 DDRSS_PI_273 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2444h
Figure 8-811 DDRSS_PI_273 Register
31302928272625242322212019181716
PI_DQS_OSC_BASE_VALUE_1_0
R/W-0h
1514131211109876543210
PI_DQS_OSC_BASE_VALUE_0_0
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1632 DDRSS_PI_273 Register Field Descriptions
BitFieldTypeResetDescription
31-16PI_DQS_OSC_BASE_VALUE_1_0R/W0h

Base value for comparison of oscillator measurement for device 1 of rank 0

15-0PI_DQS_OSC_BASE_VALUE_0_0R/W0h

Base value for comparison of oscillator measurement for device 0 of rank 0

2.5.3.275 DDRSS_PI_274 Register (Offset = 2448h) [reset = 0h]

DDRSS_PI_274 is shown in Figure 8-812 and described in Table 8-1634.

Return to Summary Table.

Table 8-1633 DDRSS_PI_274 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2448h
Figure 8-812 DDRSS_PI_274 Register
31302928272625242322212019181716
PI_DQS_OSC_BASE_VALUE_1_1
R/W-0h
1514131211109876543210
PI_DQS_OSC_BASE_VALUE_0_1
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1634 DDRSS_PI_274 Register Field Descriptions
BitFieldTypeResetDescription
31-16PI_DQS_OSC_BASE_VALUE_1_1R/W0h

Base value for comparison of oscillator measurement for device 1 of rank 1

15-0PI_DQS_OSC_BASE_VALUE_0_1R/W0h

Base value for comparison of oscillator measurement for device 0 of rank 1

2.5.3.276 DDRSS_PI_275 Register (Offset = 244Ch) [reset = 0h]

DDRSS_PI_275 is shown in Figure 8-813 and described in Table 8-1636.

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Table 8-1635 DDRSS_PI_275 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 244Ch
Figure 8-813 DDRSS_PI_275 Register
31302928272625242322212019181716
PI_MR11_DATA_F0_0PI_MR3_DATA_F0_0
R/W-0hR/W-0h
1514131211109876543210
PI_MR2_DATA_F0_0PI_MR1_DATA_F0_0
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1636 DDRSS_PI_275 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR11_DATA_F0_0R/W0h

Data to program into memory mode register 11 for chip select 0 for frequency set 0.

23-16PI_MR3_DATA_F0_0R/W0h

Data to program into memory mode register 3 for chip select 0 for frequency set 0.

15-8PI_MR2_DATA_F0_0R/W0h

Data to program into memory mode register 2 for chip select 0 for frequency set 0.

7-0PI_MR1_DATA_F0_0R/W0h

Data to program into memory mode register 1 for chip select 0 for frequency set 0.

2.5.3.277 DDRSS_PI_276 Register (Offset = 2450h) [reset = 0h]

DDRSS_PI_276 is shown in Figure 8-814 and described in Table 8-1638.

Return to Summary Table.

Table 8-1637 DDRSS_PI_276 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2450h
Figure 8-814 DDRSS_PI_276 Register
31302928272625242322212019181716
PI_MR23_DATA_F0_0PI_MR22_DATA_F0_0
R/W-0hR/W-0h
1514131211109876543210
PI_MR14_DATA_F0_0PI_MR12_DATA_F0_0
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1638 DDRSS_PI_276 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR23_DATA_F0_0R/W0h

Data to program into memory mode register 23 for chip select 0 for frequency set 0.

23-16PI_MR22_DATA_F0_0R/W0h

Data to program into memory mode register 22 for chip select 0 for frequency set 0.

15-8PI_MR14_DATA_F0_0R/W0h

Data to program into memory mode register 14 for chip select 0 for frequency set 0.

7-0PI_MR12_DATA_F0_0R/W0h

Data to program into memory mode register 12 for chip select 0 for frequency set 0.

2.5.3.278 DDRSS_PI_277 Register (Offset = 2454h) [reset = 0h]

DDRSS_PI_277 is shown in Figure 8-815 and described in Table 8-1640.

Return to Summary Table.

Table 8-1639 DDRSS_PI_277 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2454h
Figure 8-815 DDRSS_PI_277 Register
31302928272625242322212019181716
PI_MR11_DATA_F1_0PI_MR3_DATA_F1_0
R/W-0hR/W-0h
1514131211109876543210
PI_MR2_DATA_F1_0PI_MR1_DATA_F1_0
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1640 DDRSS_PI_277 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR11_DATA_F1_0R/W0h

Data to program into memory mode register 11 for chip select 0 for frequency set 1.

23-16PI_MR3_DATA_F1_0R/W0h

Data to program into memory mode register 3 for chip select 0 for frequency set 1.

15-8PI_MR2_DATA_F1_0R/W0h

Data to program into memory mode register 2 for chip select 0 for frequency set 1.

7-0PI_MR1_DATA_F1_0R/W0h

Data to program into memory mode register 1 for chip select 0 for frequency set 1.

2.5.3.279 DDRSS_PI_278 Register (Offset = 2458h) [reset = 0h]

DDRSS_PI_278 is shown in Figure 8-816 and described in Table 8-1642.

Return to Summary Table.

Table 8-1641 DDRSS_PI_278 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2458h
Figure 8-816 DDRSS_PI_278 Register
31302928272625242322212019181716
PI_MR23_DATA_F1_0PI_MR22_DATA_F1_0
R/W-0hR/W-0h
1514131211109876543210
PI_MR14_DATA_F1_0PI_MR12_DATA_F1_0
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1642 DDRSS_PI_278 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR23_DATA_F1_0R/W0h

Data to program into memory mode register 23 for chip select 0 for frequency set 1.

23-16PI_MR22_DATA_F1_0R/W0h

Data to program into memory mode register 22 for chip select 0 for frequency set 1.

15-8PI_MR14_DATA_F1_0R/W0h

Data to program into memory mode register 14 for chip select 0 for frequency set 1.

7-0PI_MR12_DATA_F1_0R/W0h

Data to program into memory mode register 12 for chip select 0 for frequency set 1.

2.5.3.280 DDRSS_PI_279 Register (Offset = 245Ch) [reset = 0h]

DDRSS_PI_279 is shown in Figure 8-817 and described in Table 8-1644.

Return to Summary Table.

Table 8-1643 DDRSS_PI_279 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 245Ch
Figure 8-817 DDRSS_PI_279 Register
31302928272625242322212019181716
PI_MR11_DATA_F2_0PI_MR3_DATA_F2_0
R/W-0hR/W-0h
1514131211109876543210
PI_MR2_DATA_F2_0PI_MR1_DATA_F2_0
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1644 DDRSS_PI_279 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR11_DATA_F2_0R/W0h

Data to program into memory mode register 11 for chip select 0 for frequency set 2.

23-16PI_MR3_DATA_F2_0R/W0h

Data to program into memory mode register 3 for chip select 0 for frequency set 2.

15-8PI_MR2_DATA_F2_0R/W0h

Data to program into memory mode register 2 for chip select 0 for frequency set 2.

7-0PI_MR1_DATA_F2_0R/W0h

Data to program into memory mode register 1 for chip select 0 for frequency set 2.

2.5.3.281 DDRSS_PI_280 Register (Offset = 2460h) [reset = 0h]

DDRSS_PI_280 is shown in Figure 8-818 and described in Table 8-1646.

Return to Summary Table.

Table 8-1645 DDRSS_PI_280 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2460h
Figure 8-818 DDRSS_PI_280 Register
31302928272625242322212019181716
PI_MR23_DATA_F2_0PI_MR22_DATA_F2_0
R/W-0hR/W-0h
1514131211109876543210
PI_MR14_DATA_F2_0PI_MR12_DATA_F2_0
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1646 DDRSS_PI_280 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR23_DATA_F2_0R/W0h

Data to program into memory mode register 23 for chip select 0 for frequency set 2.

23-16PI_MR22_DATA_F2_0R/W0h

Data to program into memory mode register 22 for chip select 0 for frequency set 2.

15-8PI_MR14_DATA_F2_0R/W0h

Data to program into memory mode register 14 for chip select 0 for frequency set 2.

7-0PI_MR12_DATA_F2_0R/W0h

Data to program into memory mode register 12 for chip select 0 for frequency set 2.

2.5.3.282 DDRSS_PI_281 Register (Offset = 2464h) [reset = 0h]

DDRSS_PI_281 is shown in Figure 8-819 and described in Table 8-1648.

Return to Summary Table.

Table 8-1647 DDRSS_PI_281 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2464h
Figure 8-819 DDRSS_PI_281 Register
31302928272625242322212019181716
PI_MR11_DATA_F0_1PI_MR3_DATA_F0_1
R/W-0hR/W-0h
1514131211109876543210
PI_MR2_DATA_F0_1PI_MR1_DATA_F0_1
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1648 DDRSS_PI_281 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR11_DATA_F0_1R/W0h

Data to program into memory mode register 11 for chip select 1 for frequency set 0.

23-16PI_MR3_DATA_F0_1R/W0h

Data to program into memory mode register 3 for chip select 1 for frequency set 0.

15-8PI_MR2_DATA_F0_1R/W0h

Data to program into memory mode register 2 for chip select 1 for frequency set 0.

7-0PI_MR1_DATA_F0_1R/W0h

Data to program into memory mode register 1 for chip select 1 for frequency set 0.

2.5.3.283 DDRSS_PI_282 Register (Offset = 2468h) [reset = 0h]

DDRSS_PI_282 is shown in Figure 8-820 and described in Table 8-1650.

Return to Summary Table.

Table 8-1649 DDRSS_PI_282 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2468h
Figure 8-820 DDRSS_PI_282 Register
31302928272625242322212019181716
PI_MR23_DATA_F0_1PI_MR22_DATA_F0_1
R/W-0hR/W-0h
1514131211109876543210
PI_MR14_DATA_F0_1PI_MR12_DATA_F0_1
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1650 DDRSS_PI_282 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR23_DATA_F0_1R/W0h

Data to program into memory mode register 23 for chip select 1 for frequency set 0.

23-16PI_MR22_DATA_F0_1R/W0h

Data to program into memory mode register 22 for chip select 1 for frequency set 0.

15-8PI_MR14_DATA_F0_1R/W0h

Data to program into memory mode register 14 for chip select 1 for frequency set 0.

7-0PI_MR12_DATA_F0_1R/W0h

Data to program into memory mode register 12 for chip select 1 for frequency set 0.

2.5.3.284 DDRSS_PI_283 Register (Offset = 246Ch) [reset = 0h]

DDRSS_PI_283 is shown in Figure 8-821 and described in Table 8-1652.

Return to Summary Table.

Table 8-1651 DDRSS_PI_283 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 246Ch
Figure 8-821 DDRSS_PI_283 Register
31302928272625242322212019181716
PI_MR11_DATA_F1_1PI_MR3_DATA_F1_1
R/W-0hR/W-0h
1514131211109876543210
PI_MR2_DATA_F1_1PI_MR1_DATA_F1_1
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1652 DDRSS_PI_283 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR11_DATA_F1_1R/W0h

Data to program into memory mode register 11 for chip select 1 for frequency set 1.

23-16PI_MR3_DATA_F1_1R/W0h

Data to program into memory mode register 3 for chip select 1 for frequency set 1.

15-8PI_MR2_DATA_F1_1R/W0h

Data to program into memory mode register 2 for chip select 1 for frequency set 1.

7-0PI_MR1_DATA_F1_1R/W0h

Data to program into memory mode register 1 for chip select 1 for frequency set 1.

2.5.3.285 DDRSS_PI_284 Register (Offset = 2470h) [reset = 0h]

DDRSS_PI_284 is shown in Figure 8-822 and described in Table 8-1654.

Return to Summary Table.

Table 8-1653 DDRSS_PI_284 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2470h
Figure 8-822 DDRSS_PI_284 Register
31302928272625242322212019181716
PI_MR23_DATA_F1_1PI_MR22_DATA_F1_1
R/W-0hR/W-0h
1514131211109876543210
PI_MR14_DATA_F1_1PI_MR12_DATA_F1_1
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1654 DDRSS_PI_284 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR23_DATA_F1_1R/W0h

Data to program into memory mode register 23 for chip select 1 for frequency set 1.

23-16PI_MR22_DATA_F1_1R/W0h

Data to program into memory mode register 22 for chip select 1 for frequency set 1.

15-8PI_MR14_DATA_F1_1R/W0h

Data to program into memory mode register 14 for chip select 1 for frequency set 1.

7-0PI_MR12_DATA_F1_1R/W0h

Data to program into memory mode register 12 for chip select 1 for frequency set 1.

2.5.3.286 DDRSS_PI_285 Register (Offset = 2474h) [reset = 0h]

DDRSS_PI_285 is shown in Figure 8-823 and described in Table 8-1656.

Return to Summary Table.

Table 8-1655 DDRSS_PI_285 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2474h
Figure 8-823 DDRSS_PI_285 Register
31302928272625242322212019181716
PI_MR11_DATA_F2_1PI_MR3_DATA_F2_1
R/W-0hR/W-0h
1514131211109876543210
PI_MR2_DATA_F2_1PI_MR1_DATA_F2_1
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1656 DDRSS_PI_285 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR11_DATA_F2_1R/W0h

Data to program into memory mode register 11 for chip select 1 for frequency set 2.

23-16PI_MR3_DATA_F2_1R/W0h

Data to program into memory mode register 3 for chip select 1 for frequency set 2.

15-8PI_MR2_DATA_F2_1R/W0h

Data to program into memory mode register 2 for chip select 1 for frequency set 2.

7-0PI_MR1_DATA_F2_1R/W0h

Data to program into memory mode register 1 for chip select 1 for frequency set 2.

2.5.3.287 DDRSS_PI_286 Register (Offset = 2478h) [reset = 0h]

DDRSS_PI_286 is shown in Figure 8-824 and described in Table 8-1658.

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Table 8-1657 DDRSS_PI_286 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2478h
Figure 8-824 DDRSS_PI_286 Register
31302928272625242322212019181716
PI_MR23_DATA_F2_1PI_MR22_DATA_F2_1
R/W-0hR/W-0h
1514131211109876543210
PI_MR14_DATA_F2_1PI_MR12_DATA_F2_1
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1658 DDRSS_PI_286 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR23_DATA_F2_1R/W0h

Data to program into memory mode register 23 for chip select 1 for frequency set 2.

23-16PI_MR22_DATA_F2_1R/W0h

Data to program into memory mode register 22 for chip select 1 for frequency set 2.

15-8PI_MR14_DATA_F2_1R/W0h

Data to program into memory mode register 14 for chip select 1 for frequency set 2.

7-0PI_MR12_DATA_F2_1R/W0h

Data to program into memory mode register 12 for chip select 1 for frequency set 2.

2.5.3.288 DDRSS_PI_287 Register (Offset = 247Ch) [reset = 0h]

DDRSS_PI_287 is shown in Figure 8-825 and described in Table 8-1660.

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Table 8-1659 DDRSS_PI_287 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 247Ch
Figure 8-825 DDRSS_PI_287 Register
31302928272625242322212019181716
PI_MR11_DATA_F0_2PI_MR3_DATA_F0_2
R/W-0hR/W-0h
1514131211109876543210
PI_MR2_DATA_F0_2PI_MR1_DATA_F0_2
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1660 DDRSS_PI_287 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR11_DATA_F0_2R/W0h

Data to program into memory mode register 11 for chip select 2 for frequency set 0.

23-16PI_MR3_DATA_F0_2R/W0h

Data to program into memory mode register 3 for chip select 2 for frequency set 0.

15-8PI_MR2_DATA_F0_2R/W0h

Data to program into memory mode register 2 for chip select 2 for frequency set 0.

7-0PI_MR1_DATA_F0_2R/W0h

Data to program into memory mode register 1 for chip select 2 for frequency set 0.

2.5.3.289 DDRSS_PI_288 Register (Offset = 2480h) [reset = 0h]

DDRSS_PI_288 is shown in Figure 8-826 and described in Table 8-1662.

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Table 8-1661 DDRSS_PI_288 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2480h
Figure 8-826 DDRSS_PI_288 Register
31302928272625242322212019181716
PI_MR23_DATA_F0_2PI_MR22_DATA_F0_2
R/W-0hR/W-0h
1514131211109876543210
PI_MR14_DATA_F0_2PI_MR12_DATA_F0_2
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1662 DDRSS_PI_288 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR23_DATA_F0_2R/W0h

Data to program into memory mode register 23 for chip select 2 for frequency set 0.

23-16PI_MR22_DATA_F0_2R/W0h

Data to program into memory mode register 22 for chip select 2 for frequency set 0.

15-8PI_MR14_DATA_F0_2R/W0h

Data to program into memory mode register 14 for chip select 2 for frequency set 0.

7-0PI_MR12_DATA_F0_2R/W0h

Data to program into memory mode register 12 for chip select 2 for frequency set 0.

2.5.3.290 DDRSS_PI_289 Register (Offset = 2484h) [reset = 0h]

DDRSS_PI_289 is shown in Figure 8-827 and described in Table 8-1664.

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Table 8-1663 DDRSS_PI_289 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2484h
Figure 8-827 DDRSS_PI_289 Register
31302928272625242322212019181716
PI_MR11_DATA_F1_2PI_MR3_DATA_F1_2
R/W-0hR/W-0h
1514131211109876543210
PI_MR2_DATA_F1_2PI_MR1_DATA_F1_2
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1664 DDRSS_PI_289 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR11_DATA_F1_2R/W0h

Data to program into memory mode register 11 for chip select 2 for frequency set 1.

23-16PI_MR3_DATA_F1_2R/W0h

Data to program into memory mode register 3 for chip select 2 for frequency set 1.

15-8PI_MR2_DATA_F1_2R/W0h

Data to program into memory mode register 2 for chip select 2 for frequency set 1.

7-0PI_MR1_DATA_F1_2R/W0h

Data to program into memory mode register 1 for chip select 2 for frequency set 1.

2.5.3.291 DDRSS_PI_290 Register (Offset = 2488h) [reset = 0h]

DDRSS_PI_290 is shown in Figure 8-828 and described in Table 8-1666.

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Table 8-1665 DDRSS_PI_290 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2488h
Figure 8-828 DDRSS_PI_290 Register
31302928272625242322212019181716
PI_MR23_DATA_F1_2PI_MR22_DATA_F1_2
R/W-0hR/W-0h
1514131211109876543210
PI_MR14_DATA_F1_2PI_MR12_DATA_F1_2
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1666 DDRSS_PI_290 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR23_DATA_F1_2R/W0h

Data to program into memory mode register 23 for chip select 2 for frequency set 1.

23-16PI_MR22_DATA_F1_2R/W0h

Data to program into memory mode register 22 for chip select 2 for frequency set 1.

15-8PI_MR14_DATA_F1_2R/W0h

Data to program into memory mode register 14 for chip select 2 for frequency set 1.

7-0PI_MR12_DATA_F1_2R/W0h

Data to program into memory mode register 12 for chip select 2 for frequency set 1.

2.5.3.292 DDRSS_PI_291 Register (Offset = 248Ch) [reset = 0h]

DDRSS_PI_291 is shown in Figure 8-829 and described in Table 8-1668.

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Table 8-1667 DDRSS_PI_291 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 248Ch
Figure 8-829 DDRSS_PI_291 Register
31302928272625242322212019181716
PI_MR11_DATA_F2_2PI_MR3_DATA_F2_2
R/W-0hR/W-0h
1514131211109876543210
PI_MR2_DATA_F2_2PI_MR1_DATA_F2_2
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1668 DDRSS_PI_291 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR11_DATA_F2_2R/W0h

Data to program into memory mode register 11 for chip select 2 for frequency set 2.

23-16PI_MR3_DATA_F2_2R/W0h

Data to program into memory mode register 3 for chip select 2 for frequency set 2.

15-8PI_MR2_DATA_F2_2R/W0h

Data to program into memory mode register 2 for chip select 2 for frequency set 2.

7-0PI_MR1_DATA_F2_2R/W0h

Data to program into memory mode register 1 for chip select 2 for frequency set 2.

2.5.3.293 DDRSS_PI_292 Register (Offset = 2490h) [reset = 0h]

DDRSS_PI_292 is shown in Figure 8-830 and described in Table 8-1670.

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Table 8-1669 DDRSS_PI_292 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2490h
Figure 8-830 DDRSS_PI_292 Register
31302928272625242322212019181716
PI_MR23_DATA_F2_2PI_MR22_DATA_F2_2
R/W-0hR/W-0h
1514131211109876543210
PI_MR14_DATA_F2_2PI_MR12_DATA_F2_2
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1670 DDRSS_PI_292 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR23_DATA_F2_2R/W0h

Data to program into memory mode register 23 for chip select 2 for frequency set 2.

23-16PI_MR22_DATA_F2_2R/W0h

Data to program into memory mode register 22 for chip select 2 for frequency set 2.

15-8PI_MR14_DATA_F2_2R/W0h

Data to program into memory mode register 14 for chip select 2 for frequency set 2.

7-0PI_MR12_DATA_F2_2R/W0h

Data to program into memory mode register 12 for chip select 2 for frequency set 2.

2.5.3.294 DDRSS_PI_293 Register (Offset = 2494h) [reset = 0h]

DDRSS_PI_293 is shown in Figure 8-831 and described in Table 8-1672.

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Table 8-1671 DDRSS_PI_293 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2494h
Figure 8-831 DDRSS_PI_293 Register
31302928272625242322212019181716
PI_MR11_DATA_F0_3PI_MR3_DATA_F0_3
R/W-0hR/W-0h
1514131211109876543210
PI_MR2_DATA_F0_3PI_MR1_DATA_F0_3
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1672 DDRSS_PI_293 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR11_DATA_F0_3R/W0h

Data to program into memory mode register 11 for chip select 3 for frequency set 0.

23-16PI_MR3_DATA_F0_3R/W0h

Data to program into memory mode register 3 for chip select 3 for frequency set 0.

15-8PI_MR2_DATA_F0_3R/W0h

Data to program into memory mode register 2 for chip select 3 for frequency set 0.

7-0PI_MR1_DATA_F0_3R/W0h

Data to program into memory mode register 1 for chip select 3 for frequency set 0.

2.5.3.295 DDRSS_PI_294 Register (Offset = 2498h) [reset = 0h]

DDRSS_PI_294 is shown in Figure 8-832 and described in Table 8-1674.

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Table 8-1673 DDRSS_PI_294 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 2498h
Figure 8-832 DDRSS_PI_294 Register
31302928272625242322212019181716
PI_MR23_DATA_F0_3PI_MR22_DATA_F0_3
R/W-0hR/W-0h
1514131211109876543210
PI_MR14_DATA_F0_3PI_MR12_DATA_F0_3
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1674 DDRSS_PI_294 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR23_DATA_F0_3R/W0h

Data to program into memory mode register 23 for chip select 3 for frequency set 0.

23-16PI_MR22_DATA_F0_3R/W0h

Data to program into memory mode register 22 for chip select 3 for frequency set 0.

15-8PI_MR14_DATA_F0_3R/W0h

Data to program into memory mode register 14 for chip select 3 for frequency set 0.

7-0PI_MR12_DATA_F0_3R/W0h

Data to program into memory mode register 12 for chip select 3 for frequency set 0.

2.5.3.296 DDRSS_PI_295 Register (Offset = 249Ch) [reset = 0h]

DDRSS_PI_295 is shown in Figure 8-833 and described in Table 8-1676.

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Table 8-1675 DDRSS_PI_295 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 249Ch
Figure 8-833 DDRSS_PI_295 Register
31302928272625242322212019181716
PI_MR11_DATA_F1_3PI_MR3_DATA_F1_3
R/W-0hR/W-0h
1514131211109876543210
PI_MR2_DATA_F1_3PI_MR1_DATA_F1_3
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1676 DDRSS_PI_295 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR11_DATA_F1_3R/W0h

Data to program into memory mode register 11 for chip select 3 for frequency set 1.

23-16PI_MR3_DATA_F1_3R/W0h

Data to program into memory mode register 3 for chip select 3 for frequency set 1.

15-8PI_MR2_DATA_F1_3R/W0h

Data to program into memory mode register 2 for chip select 3 for frequency set 1.

7-0PI_MR1_DATA_F1_3R/W0h

Data to program into memory mode register 1 for chip select 3 for frequency set 1.

2.5.3.297 DDRSS_PI_296 Register (Offset = 24A0h) [reset = 0h]

DDRSS_PI_296 is shown in Figure 8-834 and described in Table 8-1678.

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Table 8-1677 DDRSS_PI_296 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 24A0h
Figure 8-834 DDRSS_PI_296 Register
31302928272625242322212019181716
PI_MR23_DATA_F1_3PI_MR22_DATA_F1_3
R/W-0hR/W-0h
1514131211109876543210
PI_MR14_DATA_F1_3PI_MR12_DATA_F1_3
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1678 DDRSS_PI_296 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR23_DATA_F1_3R/W0h

Data to program into memory mode register 23 for chip select 3 for frequency set 1.

23-16PI_MR22_DATA_F1_3R/W0h

Data to program into memory mode register 22 for chip select 3 for frequency set 1.

15-8PI_MR14_DATA_F1_3R/W0h

Data to program into memory mode register 14 for chip select 3 for frequency set 1.

7-0PI_MR12_DATA_F1_3R/W0h

Data to program into memory mode register 12 for chip select 3 for frequency set 1.

2.5.3.298 DDRSS_PI_297 Register (Offset = 24A4h) [reset = 0h]

DDRSS_PI_297 is shown in Figure 8-835 and described in Table 8-1680.

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Table 8-1679 DDRSS_PI_297 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 24A4h
Figure 8-835 DDRSS_PI_297 Register
31302928272625242322212019181716
PI_MR11_DATA_F2_3PI_MR3_DATA_F2_3
R/W-0hR/W-0h
1514131211109876543210
PI_MR2_DATA_F2_3PI_MR1_DATA_F2_3
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1680 DDRSS_PI_297 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR11_DATA_F2_3R/W0h

Data to program into memory mode register 11 for chip select 3 for frequency set 2.

23-16PI_MR3_DATA_F2_3R/W0h

Data to program into memory mode register 3 for chip select 3 for frequency set 2.

15-8PI_MR2_DATA_F2_3R/W0h

Data to program into memory mode register 2 for chip select 3 for frequency set 2.

7-0PI_MR1_DATA_F2_3R/W0h

Data to program into memory mode register 1 for chip select 3 for frequency set 2.

2.5.3.299 DDRSS_PI_298 Register (Offset = 24A8h) [reset = 0h]

DDRSS_PI_298 is shown in Figure 8-836 and described in Table 8-1682.

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Table 8-1681 DDRSS_PI_298 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 24A8h
Figure 8-836 DDRSS_PI_298 Register
31302928272625242322212019181716
PI_MR23_DATA_F2_3PI_MR22_DATA_F2_3
R/W-0hR/W-0h
1514131211109876543210
PI_MR14_DATA_F2_3PI_MR12_DATA_F2_3
R/W-0hR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1682 DDRSS_PI_298 Register Field Descriptions
BitFieldTypeResetDescription
31-24PI_MR23_DATA_F2_3R/W0h

Data to program into memory mode register 23 for chip select 3 for frequency set 2.

23-16PI_MR22_DATA_F2_3R/W0h

Data to program into memory mode register 22 for chip select 3 for frequency set 2.

15-8PI_MR14_DATA_F2_3R/W0h

Data to program into memory mode register 14 for chip select 3 for frequency set 2.

7-0PI_MR12_DATA_F2_3R/W0h

Data to program into memory mode register 12 for chip select 3 for frequency set 2.

2.5.3.300 DDRSS_PI_299 Register (Offset = 24ACh) [reset = X]

DDRSS_PI_299 is shown in Figure 8-837 and described in Table 8-1684.

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Table 8-1683 DDRSS_PI_299 Instances
InstancePhysical Address
COMPUTE_CLUSTER0_CTL_CFG_PI0299 24ACh
Figure 8-837 DDRSS_PI_299 Register
31302928272625242322212019181716
RESERVED
R/W-X
1514131211109876543210
RESERVEDPI_PARITY_ERROR_REGIF
R/W-XR/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 8-1684 DDRSS_PI_299 Register Field Descriptions
BitFieldTypeResetDescription
31-11RESERVEDR/WX
10-0PI_PARITY_ERROR_REGIFR/W0h

Inject parity error to regisster interface signals for PI.
WRITE-ONLY