SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Figure 12-317 shows all of the MCSPI interface signals in master mode.
Table 12-608 describes the MCSPI I/O signals in master mode.
Module Pin | Device Level Signal | I/O(1) | Description | Module Pin Reset Value(2) |
---|---|---|---|---|
MCU_MCSPI[1-0] | ||||
SPICLK | MCU_SPI[1-0]_CLK | O | MCSPI Serial clock output for master mode. | HiZ |
SPIDAT[0] | MCU_SPI[1-0]_D0 | O(3) | MCSPI Data I/O for master mode. | HiZ |
SPIDAT[1] | MCU_SPI[1-0]_D1 | I(4) | MCSPI Data I/O for master mode. | HiZ |
SPIEN[i] | MCU_SPI[1-0]_CSi | O | MCSPI Chip-select i output for master mode | HiZ |
MCSPI[7-5] and MCSPI[3-0] | ||||
SPICLK | SPI[7-5]_CLK and SPI[3-0]_CLK | O | MCSPI Serial clock output for master mode. | HiZ |
SPIDAT[0] | SPI[7-5]_D0 and SPI[3-0]_D0 | O(3) | MCSPI Data I/O for master mode. | HiZ |
SPIDAT[1] | SPI[7-5]_D1 and SPI[3-0]_D1 | I(4) | MCSPI Data I/O for master mode. | HiZ |
SPIEN[i] | SPI[7-5]_CSi and SPI[3-0]_CSi | O | MCSPI Chip-select i output for master mode | HiZ |
For SPI[7-5]_CLK, SPI[3-0]_CLK, and MCU_SPI[1-0]_CLK signals to work properly, the RXACTIVE bit of the appropriate CTRLMMR_WKUP_PADCONFIGx/ CTRLMMR_PADCONFIGy registers should be set to 0x1 because of retiming purposes.
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.