SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Some register settings within the PHY are chip select based. The DDRSS_PHY_6[0] PHY_PER_CS_TRAINING_INDEX_0 bit allows access to a particular chip select copy. The PHY_PER_CS_TRAINING_INDEX_0 bit is associated with data slice 0. The following bits are associated with the other data slices:
Some register settings in the PHY are frequency based. As already described, the DDRSS_PHY_1281[17-16] PHY_FREQ_SEL_INDEX field allows access to a particular frequency copy. When writing to frequency based registers, if the DDRSS_PHY_1281[8] PHY_FREQ_SEL_MULTICAST_EN bit is set to 0x1, then all frequency copies receive the same data. Table 8-88 shows the frequency based register settings.
Register Settings | Category |
---|---|
Data Slice | |
DDRSS_PHY_103[3-0] PHY_SW_MASTER_MODE_0 DDRSS_PHY_359[3-0] PHY_SW_MASTER_MODE_1 DDRSS_PHY_615[3-0] PHY_SW_MASTER_MODE_2 DDRSS_PHY_871[3-0] PHY_SW_MASTER_MODE_3 | Master delay line |
DDRSS_PHY_103[18-8] PHY_MASTER_DELAY_START_0 DDRSS_PHY_359[18-8] PHY_MASTER_DELAY_START_0 DDRSS_PHY_615[18-8] PHY_MASTER_DELAY_START_0 DDRSS_PHY_871[18-8] PHY_MASTER_DELAY_START_0 | |
DDRSS_PHY_103[29-24] PHY_MASTER_DELAY_STEP_0 DDRSS_PHY_359[29-24] PHY_MASTER_DELAY_STEP_0 DDRSS_PHY_615[29-24] PHY_MASTER_DELAY_STEP_0 DDRSS_PHY_871[29-24] PHY_MASTER_DELAY_STEP_0 | |
DDRSS_PHY_104[7-0] PHY_MASTER_DELAY_WAIT_0 DDRSS_PHY_360[7-0] PHY_MASTER_DELAY_WAIT_1 DDRSS_PHY_616[7-0] PHY_MASTER_DELAY_WAIT_2 DDRSS_PHY_872[7-0] PHY_MASTER_DELAY_WAIT_3 | |
DDRSS_PHY_104[15-8] PHY_MASTER_DELAY_HALF_MEASURE_0 DDRSS_PHY_360[15-8] PHY_MASTER_DELAY_HALF_MEASURE_1 DDRSS_PHY_616[15-8] PHY_MASTER_DELAY_HALF_MEASURE_2 DDRSS_PHY_872[15-8] PHY_MASTER_DELAY_HALF_MEASURE_3 | |
DDRSS_PHY_110[1-0] PHY_WRPATH_GATE_DISABLE_0 DDRSS_PHY_366[1-0] PHY_WRPATH_GATE_DISABLE_1 DDRSS_PHY_622[1-0] PHY_WRPATH_GATE_DISABLE_2 DDRSS_PHY_878[1-0] PHY_WRPATH_GATE_DISABLE_3 | Write path |
DDRSS_PHY_110[10-8] PHY_WRPATH_GATE_TIMING_0 DDRSS_PHY_366[10-8] PHY_WRPATH_GATE_TIMING_1 DDRSS_PHY_622[10-8] PHY_WRPATH_GATE_TIMING_2 DDRSS_PHY_878[10-8] PHY_WRPATH_GATE_TIMING_3 | |
DDRSS_PHY_139[9-8] PHY_DQ_FFE_0 DDRSS_PHY_395[9-8] PHY_DQ_FFE_1 DDRSS_PHY_651[9-8] PHY_DQ_FFE_2 DDRSS_PHY_907[9-8] PHY_DQ_FFE_3 | |
DDRSS_PHY_139[17-16] PHY_DQS_FFE_0 DDRSS_PHY_395[17-16] PHY_DQS_FFE_1 DDRSS_PHY_651[17-16] PHY_DQS_FFE_2 DDRSS_PHY_907[17-16] PHY_DQS_FFE_3 | |
DDRSS_PHY_104[31-24] PHY_WRLVL_DLY_STEP_0 DDRSS_PHY_360[31-24] PHY_WRLVL_DLY_STEP_1 DDRSS_PHY_616[31-24] PHY_WRLVL_DLY_STEP_2 DDRSS_PHY_872[31-24] PHY_WRLVL_DLY_STEP_3 | Write leveling |
DDRSS_PHY_105[3-0] PHY_WRLVL_DLY_FINE_STEP_0 DDRSS_PHY_361[3-0] PHY_WRLVL_DLY_FINE_STEP_1 DDRSS_PHY_617[3-0] PHY_WRLVL_DLY_FINE_STEP_2 DDRSS_PHY_873[3-0] PHY_WRLVL_DLY_FINE_STEP_3 | |
DDRSS_PHY_105[13-8] PHY_WRLVL_RESP_WAIT_CNT_0 DDRSS_PHY_361[13-8] PHY_WRLVL_RESP_WAIT_CNT_1 DDRSS_PHY_617[13-8] PHY_WRLVL_RESP_WAIT_CNT_2 DDRSS_PHY_873[13-8] PHY_WRLVL_RESP_WAIT_CNT_3 | |
DDRSS_PHY_107[7-0] PHY_WDQLVL_DLY_STEP_0 DDRSS_PHY_363[7-0] PHY_WDQLVL_DLY_STEP_1 DDRSS_PHY_619[7-0] PHY_WDQLVL_DLY_STEP_2 DDRSS_PHY_875[7-0] PHY_WDQLVL_DLY_STEP_3 | Write DQ training |
DDRSS_PHY_107[11-8] PHY_WDQLVL_QTR_DLY_STEP_0 DDRSS_PHY_363[11-8] PHY_WDQLVL_QTR_DLY_STEP_1 DDRSS_PHY_619[11-8] PHY_WDQLVL_QTR_DLY_STEP_2 DDRSS_PHY_875[11-8] PHY_WDQLVL_QTR_DLY_STEP_3 | |
DDRSS_PHY_86[16] PHY_NTP_TRAIN_EN_0 DDRSS_PHY_342[16] PHY_NTP_TRAIN_EN_1 DDRSS_PHY_598[16] PHY_NTP_TRAIN_EN_2 DDRSS_PHY_854[16] PHY_NTP_TRAIN_EN_3 | |
DDRSS_PHY_86[31-24] PHY_NTP_WDQ_STEP_SIZE_0 DDRSS_PHY_342[31-24] PHY_NTP_WDQ_STEP_SIZE_1 DDRSS_PHY_598[31-24] PHY_NTP_WDQ_STEP_SIZE_2 DDRSS_PHY_854[31-24] PHY_NTP_WDQ_STEP_SIZE_3 | |
DDRSS_PHY_87[10-0] PHY_NTP_WDQ_START_0 DDRSS_PHY_343[10-0] PHY_NTP_WDQ_START_1 DDRSS_PHY_599[10-0] PHY_NTP_WDQ_START_2 DDRSS_PHY_855[10-0] PHY_NTP_WDQ_START_3 | |
DDRSS_PHY_87[26-16] PHY_NTP_WDQ_STOP_0 DDRSS_PHY_343[26-16] PHY_NTP_WDQ_STOP_1 DDRSS_PHY_599[26-16] PHY_NTP_WDQ_STOP_2 DDRSS_PHY_855[26-16] PHY_NTP_WDQ_STOP_3 | |
DDRSS_PHY_88[17-8] PHY_WDQLVL_DVW_MIN_0 DDRSS_PHY_344[17-8] PHY_WDQLVL_DVW_MIN_1 DDRSS_PHY_600[17-8] PHY_WDQLVL_DVW_MIN_2 DDRSS_PHY_856[17-8] PHY_WDQLVL_DVW_MIN_3 | |
DDRSS_PHY_88[24] PHY_SW_WDQLVL_DVW_MIN_EN_0 DDRSS_PHY_344[24] PHY_SW_WDQLVL_DVW_MIN_EN_1 DDRSS_PHY_600[24] PHY_SW_WDQLVL_DVW_MIN_EN_2 DDRSS_PHY_856[24] PHY_SW_WDQLVL_DVW_MIN_EN_3 | |
DDRSS_PHY_89[5-0] PHY_WDQLVL_PER_START_OFFSET_0 DDRSS_PHY_345[5-0] PHY_WDQLVL_PER_START_OFFSET_1 DDRSS_PHY_601[5-0] PHY_WDQLVL_PER_START_OFFSET_2 DDRSS_PHY_857[5-0] PHY_WDQLVL_PER_START_OFFSET_3 | |
DDRSS_PHY_113[6-0] PHY_WDQ_OSC_DELTA_0 DDRSS_PHY_369[6-0] PHY_WDQ_OSC_DELTA_1 DDRSS_PHY_625[6-0] PHY_WDQ_OSC_DELTA_2 DDRSS_PHY_881[6-0] PHY_WDQ_OSC_DELTA_3 | |
DDRSS_PHY_136[15-8] PHY_DATA_DC_DQ0_CLK_ADJUST_0 DDRSS_PHY_136[23-16] PHY_DATA_DC_DQ1_CLK_ADJUST_0 DDRSS_PHY_136[31-24] PHY_DATA_DC_DQ2_CLK_ADJUST_0 DDRSS_PHY_137[7-0] PHY_DATA_DC_DQ3_CLK_ADJUST_0 DDRSS_PHY_137[15-8] PHY_DATA_DC_DQ4_CLK_ADJUST_0 DDRSS_PHY_137[23-16] PHY_DATA_DC_DQ5_CLK_ADJUST_0 DDRSS_PHY_137[31-24] PHY_DATA_DC_DQ6_CLK_ADJUST_0 DDRSS_PHY_138[7-0] PHY_DATA_DC_DQ7_CLK_ADJUST_0 DDRSS_PHY_392[15-8] PHY_DATA_DC_DQ0_CLK_ADJUST_1 DDRSS_PHY_392[23-16] PHY_DATA_DC_DQ1_CLK_ADJUST_1 DDRSS_PHY_392[31-24] PHY_DATA_DC_DQ2_CLK_ADJUST_1 DDRSS_PHY_393[7-0] PHY_DATA_DC_DQ3_CLK_ADJUST_1 DDRSS_PHY_393[15-8] PHY_DATA_DC_DQ4_CLK_ADJUST_1 DDRSS_PHY_393[23-16] PHY_DATA_DC_DQ5_CLK_ADJUST_1 DDRSS_PHY_393[31-24] PHY_DATA_DC_DQ6_CLK_ADJUST_1 DDRSS_PHY_394[7-0] PHY_DATA_DC_DQ7_CLK_ADJUST_1 DDRSS_PHY_648[15-8] PHY_DATA_DC_DQ0_CLK_ADJUST_2 DDRSS_PHY_648[23-16] PHY_DATA_DC_DQ1_CLK_ADJUST_2 DDRSS_PHY_648[31-24] PHY_DATA_DC_DQ2_CLK_ADJUST_2 DDRSS_PHY_649[7-0] PHY_DATA_DC_DQ3_CLK_ADJUST_2 DDRSS_PHY_649[15-8] PHY_DATA_DC_DQ4_CLK_ADJUST_2 DDRSS_PHY_649[23-16] PHY_DATA_DC_DQ5_CLK_ADJUST_2 DDRSS_PHY_649[31-24] PHY_DATA_DC_DQ6_CLK_ADJUST_2 DDRSS_PHY_650[7-0] PHY_DATA_DC_DQ7_CLK_ADJUST_2 DDRSS_PHY_904[15-8] PHY_DATA_DC_DQ0_CLK_ADJUST_3 DDRSS_PHY_904[23-16] PHY_DATA_DC_DQ1_CLK_ADJUST_3 DDRSS_PHY_904[31-24] PHY_DATA_DC_DQ2_CLK_ADJUST_3 DDRSS_PHY_905[7-0] PHY_DATA_DC_DQ3_CLK_ADJUST_3 DDRSS_PHY_905[15-8] PHY_DATA_DC_DQ4_CLK_ADJUST_3 DDRSS_PHY_905[23-16] PHY_DATA_DC_DQ5_CLK_ADJUST_3 DDRSS_PHY_905[31-24] PHY_DATA_DC_DQ6_CLK_ADJUST_3 DDRSS_PHY_906[7-0] PHY_DATA_DC_DQ7_CLK_ADJUST_3 | Duty cycle correction |
DDRSS_PHY_138[15-8] PHY_DATA_DC_DM_CLK_ADJUST_0 DDRSS_PHY_394[15-8] PHY_DATA_DC_DM_CLK_ADJUST_1 DDRSS_PHY_650[15-8] PHY_DATA_DC_DM_CLK_ADJUST_2 DDRSS_PHY_906[15-8] PHY_DATA_DC_DM_CLK_ADJUST_3 | Duty cycle correction |
DDRSS_PHY_136[7-0] PHY_DATA_DC_DQS_CLK_ADJUST_0 DDRSS_PHY_392[7-0] PHY_DATA_DC_DQS_CLK_ADJUST_1 DDRSS_PHY_648[7-0] PHY_DATA_DC_DQS_CLK_ADJUST_2 DDRSS_PHY_904[7-0] PHY_DATA_DC_DQS_CLK_ADJUST_3 | |
DDRSS_PHY_110[17-16] PHY_DATA_DC_INIT_DISABLE_0 DDRSS_PHY_366[17-16] PHY_DATA_DC_INIT_DISABLE_1 DDRSS_PHY_622[17-16] PHY_DATA_DC_INIT_DISABLE_2 DDRSS_PHY_878[17-16] PHY_DATA_DC_INIT_DISABLE_3 | |
DDRSS_PHY_112[0] PHY_DATA_DC_WRLVL_ENABLE_0 DDRSS_PHY_368[0] PHY_DATA_DC_WRLVL_ENABLE_1 DDRSS_PHY_624[0] PHY_DATA_DC_WRLVL_ENABLE_2 DDRSS_PHY_880[0] PHY_DATA_DC_WRLVL_ENABLE_3 | |
DDRSS_PHY_112[8] PHY_DATA_DC_WDQLVL_ENABLE_0 DDRSS_PHY_368[8] PHY_DATA_DC_WDQLVL_ENABLE_1 DDRSS_PHY_624[8] PHY_DATA_DC_WDQLVL_ENABLE_2 DDRSS_PHY_880[8] PHY_DATA_DC_WDQLVL_ENABLE_3 | |
DDRSS_PHY_111[26-16] PHY_DATA_DC_DQ_INIT_SLV_DELAY_0 DDRSS_PHY_367[26-16] PHY_DATA_DC_DQ_INIT_SLV_DELAY_1 DDRSS_PHY_623[26-16] PHY_DATA_DC_DQ_INIT_SLV_DELAY_2 DDRSS_PHY_879[26-16] PHY_DATA_DC_DQ_INIT_SLV_DELAY_3 | |
DDRSS_PHY_111[9-0] PHY_DATA_DC_DQS_INIT_SLV_DELAY_0 DDRSS_PHY_367[9-0] PHY_DATA_DC_DQS_INIT_SLV_DELAY_1 DDRSS_PHY_623[9-0] PHY_DATA_DC_DQS_INIT_SLV_DELAY_2 DDRSS_PHY_879[9-0] PHY_DATA_DC_DQS_INIT_SLV_DELAY_3 | |
DDRSS_PHY_97[18-16] PHY_DATA_DC_CAL_CLK_SEL_0 DDRSS_PHY_353[18-16] PHY_DATA_DC_CAL_CLK_SEL_1 DDRSS_PHY_609[18-16] PHY_DATA_DC_CAL_CLK_SEL_2 DDRSS_PHY_865[18-16] PHY_DATA_DC_CAL_CLK_SEL_3 | |
DDRSS_PHY_112[23-16] PHY_DATA_DC_DM_CLK_SE_THRSHLD_0 DDRSS_PHY_368[23-16] PHY_DATA_DC_DM_CLK_SE_THRSHLD_1 DDRSS_PHY_624[23-16] PHY_DATA_DC_DM_CLK_SE_THRSHLD_2 DDRSS_PHY_880[23-16] PHY_DATA_DC_DM_CLK_SE_THRSHLD_3 | |
DDRSS_PHY_112[31-24] PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0 DDRSS_PHY_368[31-24] PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1 DDRSS_PHY_624[31-24] PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2 DDRSS_PHY_880[31-24] PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3 | |
DDRSS_PHY_93[9-0] PHY_RDDQ0_SLAVE_DELAY_0 DDRSS_PHY_93[25-16] PHY_RDDQ1_SLAVE_DELAY_0 DDRSS_PHY_94[9-0] PHY_RDDQ2_SLAVE_DELAY_0 DDRSS_PHY_94[25-16] PHY_RDDQ3_SLAVE_DELAY_0 DDRSS_PHY_95[9-0] PHY_RDDQ4_SLAVE_DELAY_0 DDRSS_PHY_95[25-16] PHY_RDDQ5_SLAVE_DELAY_0 DDRSS_PHY_96[9-0] PHY_RDDQ6_SLAVE_DELAY_0 DDRSS_PHY_96[25-16] PHY_RDDQ7_SLAVE_DELAY_0 DDRSS_PHY_349[9-0] PHY_RDDQ0_SLAVE_DELAY_1 DDRSS_PHY_349[25-16] PHY_RDDQ1_SLAVE_DELAY_1 DDRSS_PHY_350[9-0] PHY_RDDQ2_SLAVE_DELAY_1 DDRSS_PHY_350[25-16] PHY_RDDQ3_SLAVE_DELAY_1 DDRSS_PHY_351[9-0] PHY_RDDQ4_SLAVE_DELAY_1 DDRSS_PHY_351[25-16] PHY_RDDQ5_SLAVE_DELAY_1 DDRSS_PHY_352[9-0] PHY_RDDQ6_SLAVE_DELAY_1 DDRSS_PHY_352[25-16] PHY_RDDQ7_SLAVE_DELAY_1 DDRSS_PHY_605[9-0] PHY_RDDQ0_SLAVE_DELAY_2 DDRSS_PHY_605[25-16] PHY_RDDQ1_SLAVE_DELAY_2 DDRSS_PHY_606[9-0] PHY_RDDQ2_SLAVE_DELAY_2 DDRSS_PHY_606[25-16] PHY_RDDQ3_SLAVE_DELAY_2 DDRSS_PHY_607[9-0] PHY_RDDQ4_SLAVE_DELAY_2 DDRSS_PHY_607[25-16] PHY_RDDQ5_SLAVE_DELAY_2 DDRSS_PHY_608[9-0] PHY_RDDQ6_SLAVE_DELAY_2 DDRSS_PHY_608[25-16] PHY_RDDQ7_SLAVE_DELAY_2 DDRSS_PHY_861[9-0] PHY_RDDQ0_SLAVE_DELAY_3 DDRSS_PHY_861[25-16] PHY_RDDQ1_SLAVE_DELAY_3 DDRSS_PHY_862[9-0] PHY_RDDQ2_SLAVE_DELAY_3 DDRSS_PHY_862[25-16] PHY_RDDQ3_SLAVE_DELAY_3 DDRSS_PHY_863[9-0] PHY_RDDQ4_SLAVE_DELAY_3 DDRSS_PHY_863[25-16] PHY_RDDQ5_SLAVE_DELAY DDRSS_PHY_864[9-0] PHY_RDDQ6_SLAVE_DELAY_3 DDRSS_PHY_864[25-16] PHY_RDDQ7_SLAVE_DELAY_3 | Read path |
DDRSS_PHY_97[9-0] PHY_RDDM_SLAVE_DELAY_0 DDRSS_PHY_353[9-0] PHY_RDDM_SLAVE_DELAY_1 DDRSS_PHY_609[9-0] PHY_RDDM_SLAVE_DELAY_2 DDRSS_PHY_865[9-0] PHY_RDDM_SLAVE_DELAY_3 | Read path |
DDRSS_PHY_101[25-24] PHY_RDDATA_EN_IE_DLY_0 DDRSS_PHY_357[25-24] PHY_RDDATA_EN_IE_DLY_1 DDRSS_PHY_613[25-24] PHY_RDDATA_EN_IE_DLY_2 DDRSS_PHY_869[25-24] PHY_RDDATA_EN_IE_DLY_3 | |
DDRSS_PHY_102[1-0] PHY_IE_MODE_0 DDRSS_PHY_358[1-0] PHY_IE_MODE_1 DDRSS_PHY_614[1-0] PHY_IE_MODE_2 DDRSS_PHY_870[1-0] PHY_IE_MODE_3 | |
DDRSS_PHY_102[20-16] PHY_RDDATA_EN_TSEL_DLY_0 DDRSS_PHY_358[20-16] PHY_RDDATA_EN_TSEL_DLY_1 DDRSS_PHY_614[20-16] PHY_RDDATA_EN_TSEL_DLY_2 DDRSS_PHY_870[20-16] PHY_RDDATA_EN_TSEL_DLY_3 | |
DDRSS_PHY_102[28-24] PHY_RDDATA_EN_OE_DLY_0 DDRSS_PHY_358[28-24] PHY_RDDATA_EN_OE_DLY_1 DDRSS_PHY_614[28-24] PHY_RDDATA_EN_OE_DLY_2 DDRSS_PHY_870[28-24] PHY_RDDATA_EN_OE_DLY_3 | |
DDRSS_PHY_113[20-16] PHY_RDDATA_EN_DLY_0 DDRSS_PHY_369[20-16] PHY_RDDATA_EN_DLY_1 DDRSS_PHY_625[20-16] PHY_RDDATA_EN_DLY_2 DDRSS_PHY_881[20-16] PHY_RDDATA_EN_DLY_3 | |
DDRSS_PHY_104[19-16] PHY_RPTR_UPDATE_0 DDRSS_PHY_360[19-16] PHY_RPTR_UPDATE_1 DDRSS_PHY_616[19-16] PHY_RPTR_UPDATE_2 DDRSS_PHY_872[19-16] PHY_RPTR_UPDATE_3 | |
DDRSS_PHY_105[19-16] PHY_GTLVL_DLY_STEP_0 DDRSS_PHY_361[19-16] PHY_GTLVL_DLY_STEP_1 DDRSS_PHY_617[19-16] PHY_GTLVL_DLY_STEP_2 DDRSS_PHY_873[19-16] PHY_GTLVL_DLY_STEP_3 | Gate training |
DDRSS_PHY_105[28-24] PHY_GTLVL_RESP_WAIT_CNT_0 DDRSS_PHY_361[28-24] PHY_GTLVL_RESP_WAIT_CNT_1 DDRSS_PHY_617[28-24] PHY_GTLVL_RESP_WAIT_CNT_2 DDRSS_PHY_873[28-24] PHY_GTLVL_RESP_WAIT_CNT_3 | |
DDRSS_PHY_106[9-0] PHY_GTLVL_BACK_STEP_0 DDRSS_PHY_362[9-0] PHY_GTLVL_BACK_STEP_1 DDRSS_PHY_618[9-0] PHY_GTLVL_BACK_STEP_2 DDRSS_PHY_874[9-0] PHY_GTLVL_BACK_STEP_3 | |
DDRSS_PHY_106[25-16] PHY_GTLVL_FINAL_STEP_0 DDRSS_PHY_362[25-16] PHY_GTLVL_FINAL_STEP_1 DDRSS_PHY_618[25-16] PHY_GTLVL_FINAL_STEP_2 DDRSS_PHY_874[25-16] PHY_GTLVL_FINAL_STEP_3 | |
DDRSS_PHY_107[27-24] PHY_RDLVL_DLY_STEP_0 DDRSS_PHY_363[27-24] PHY_RDLVL_DLY_STEP_1 DDRSS_PHY_619[27-24] PHY_RDLVL_DLY_STEP_2 DDRSS_PHY_875[27-24] PHY_RDLVL_DLY_STEP_3 | Read data eye training |
DDRSS_PHY_108[9-0] PHY_RDLVL_MAX_EDGE_0 DDRSS_PHY_364[9-0] PHY_RDLVL_MAX_EDGE_1 DDRSS_PHY_620[9-0] PHY_RDLVL_MAX_EDGE_2 DDRSS_PHY_876[9-0] PHY_RDLVL_MAX_EDGE_3 | |
DDRSS_PHY_109[9-0] PHY_RDLVL_DVW_MIN_0 DDRSS_PHY_365[9-0] PHY_RDLVL_DVW_MIN_1 DDRSS_PHY_621[9-0] PHY_RDLVL_DVW_MIN_2 DDRSS_PHY_877[9-0] PHY_RDLVL_DVW_MIN_3 | |
DDRSS_PHY_109[16] PHY_SW_RDLVL_DVW_MIN_EN_0 DDRSS_PHY_365[16] PHY_SW_RDLVL_DVW_MIN_EN_1 DDRSS_PHY_621[16] PHY_SW_RDLVL_DVW_MIN_EN_2 DDRSS_PHY_877[16] PHY_SW_RDLVL_DVW_MIN_EN_3 | |
DDRSS_PHY_109[29-24] PHY_RDLVL_PER_START_OFFSET_0 DDRSS_PHY_365[29-24] PHY_RDLVL_PER_START_OFFSET_1 DDRSS_PHY_621[29-24] PHY_RDLVL_PER_START_OFFSET_2 DDRSS_PHY_877[29-24] PHY_RDLVL_PER_START_OFFSET_3 | |
DDRSS_PHY_135[9-0] PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0 DDRSS_PHY_391[9-0] PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1 DDRSS_PHY_647[9-0] PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2 DDRSS_PHY_903[9-0] PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3 | |
DDRSS_PHY_85[30-24] PHY_VREF_INITIAL_START_POINT_0 DDRSS_PHY_341[30-24] PHY_VREF_INITIAL_START_POINT_1 DDRSS_PHY_597[30-24] PHY_VREF_INITIAL_START_POINT_2 DDRSS_PHY_853[30-24] PHY_VREF_INITIAL_START_POINT_3 | |
DDRSS_PHY_86[6-0] PHY_VREF_INITIAL_STOP_POINT_0 DDRSS_PHY_342[6-0] PHY_VREF_INITIAL_STOP_POINT_1 DDRSS_PHY_598[6-0] PHY_VREF_INITIAL_STOP_POINT_2 DDRSS_PHY_854[6-0] PHY_VREF_INITIAL_STOP_POINT_3 | |
DDRSS_PHY_100[27-16] PHY_PAD_VREF_CTRL_DQ_0 DDRSS_PHY_356[27-16] PHY_PAD_VREF_CTRL_DQ_1 DDRSS_PHY_612[27-16] PHY_PAD_VREF_CTRL_DQ_2 DDRSS_PHY_868[27-16] PHY_PAD_VREF_CTRL_DQ_3 | |
DDRSS_PHY_98[7-0] PHY_DQ_OE_TIMING_0 DDRSS_PHY_354[7-0] PHY_DQ_OE_TIMING_1 DDRSS_PHY_610[7-0] PHY_DQ_OE_TIMING_2 DDRSS_PHY_866[7-0] PHY_DQ_OE_TIMING_3 | Timing |
DDRSS_PHY_98[15-8] PHY_DQ_TSEL_RD_TIMING_0 DDRSS_PHY_354[15-8] PHY_DQ_TSEL_RD_TIMING_1 DDRSS_PHY_610[15-8] PHY_DQ_TSEL_RD_TIMING_2 DDRSS_PHY_866[15-8] PHY_DQ_TSEL_RD_TIMING_3 | |
DDRSS_PHY_98[23-16] PHY_DQ_TSEL_WR_TIMING_0 DDRSS_PHY_354[23-16] PHY_DQ_TSEL_WR_TIMING_1 DDRSS_PHY_610[23-16] PHY_DQ_TSEL_WR_TIMING_2 DDRSS_PHY_866[23-16] PHY_DQ_TSEL_WR_TIMING_3 | |
DDRSS_PHY_98[31-24] PHY_DQS_OE_TIMING_0 DDRSS_PHY_354[31-24] PHY_DQS_OE_TIMING_1 DDRSS_PHY_610[31-24] PHY_DQS_OE_TIMING_2 DDRSS_PHY_866[31-24] PHY_DQS_OE_TIMING_3 | |
DDRSS_PHY_99[15-8] PHY_DQS_TSEL_RD_TIMING_0 DDRSS_PHY_355[15-8] PHY_DQS_TSEL_RD_TIMING_1 DDRSS_PHY_611[15-8] PHY_DQS_TSEL_RD_TIMING_2 DDRSS_PHY_867[15-8] PHY_DQS_TSEL_RD_TIMING_3 | |
DDRSS_PHY_99[31-24] PHY_DQS_TSEL_WR_TIMING_0 DDRSS_PHY_355[31-24] PHY_DQS_TSEL_WR_TIMING_1 DDRSS_PHY_611[31-24] PHY_DQS_TSEL_WR_TIMING_2 DDRSS_PHY_867[31-24] PHY_DQS_TSEL_WR_TIMING_3 | |
DDRSS_PHY_84[2-0] PHY_DQ_TSEL_ENABLE_0 DDRSS_PHY_340[2-0] PHY_DQ_TSEL_ENABLE_1 DDRSS_PHY_596[2-0] PHY_DQ_TSEL_ENABLE_2 DDRSS_PHY_852[2-0] PHY_DQ_TSEL_ENABLE_3 | |
DDRSS_PHY_84[23-8] PHY_DQ_TSEL_SELECT_0 DDRSS_PHY_340[23-8] PHY_DQ_TSEL_SELECT_1 DDRSS_PHY_596[23-8] PHY_DQ_TSEL_SELECT_2 DDRSS_PHY_852[23-8] PHY_DQ_TSEL_SELECT_3 | |
DDRSS_PHY_84[26-24] PHY_DQS_TSEL_ENABLE_0 DDRSS_PHY_340[26-24] PHY_DQS_TSEL_ENABLE_1 DDRSS_PHY_596[26-24] PHY_DQS_TSEL_ENABLE_2 DDRSS_PHY_852[26-24] PHY_DQS_TSEL_ENABLE_3 | |
DDRSS_PHY_85[15-0] PHY_DQS_TSEL_SELECT_0 DDRSS_PHY_341[15-0] PHY_DQS_TSEL_SELECT_1 DDRSS_PHY_597[15-0] PHY_DQS_TSEL_SELECT_2 DDRSS_PHY_853[15-0] PHY_DQS_TSEL_SELECT_3 | |
DDRSS_PHY_99[23-16] PHY_DQS_OE_RD_TIMING_0 DDRSS_PHY_355[23-16] PHY_DQS_OE_RD_TIMING_1 DDRSS_PHY_611[23-16] PHY_DQS_OE_RD_TIMING_2 DDRSS_PHY_867[23-16] PHY_DQS_OE_RD_TIMING_3 | |
DDRSS_PHY_101[15-8] PHY_DQ_IE_TIMING_0 DDRSS_PHY_357[15-8] PHY_DQ_IE_TIMING_1 DDRSS_PHY_613[15-8] PHY_DQ_IE_TIMING_2 DDRSS_PHY_869[15-8] PHY_DQ_IE_TIMING_3 | |
DDRSS_PHY_101[23-16] PHY_DQS_IE_TIMING_0 DDRSS_PHY_357[23-16] PHY_DQS_IE_TIMING_1 DDRSS_PHY_613[23-16] PHY_DQS_IE_TIMING_2 DDRSS_PHY_869[23-16] PHY_DQS_IE_TIMING_3 | |
DDRSS_PHY_92[21-16] PHY_PAD_DSLICE_IO_CFG_0 DDRSS_PHY_348[21-16] PHY_PAD_DSLICE_IO_CFG_1 DDRSS_PHY_604[21-16] PHY_PAD_DSLICE_IO_CFG_2 DDRSS_PHY_860[21-16] PHY_PAD_DSLICE_IO_CFG_3 | Pad Controls |
Address Slice | |
DDRSS_PHY_1065[4-0] PHY_ADR0_SW_WRADDR_SHIFT_0 DDRSS_PHY_1065[28-24] PHY_ADR1_SW_WRADDR_SHIFT_0 DDRSS_PHY_1066[20-16] PHY_ADR2_SW_WRADDR_SHIFT_0 DDRSS_PHY_1067[20-16] PHY_ADR3_SW_WRADDR_SHIFT_0 DDRSS_PHY_1068[20-16] PHY_ADR4_SW_WRADDR_SHIFT_0 DDRSS_PHY_1069[20-16] PHY_ADR5_SW_WRADDR_SHIFT_0 | Overrides |
DDRSS_PHY_1070[19-16] PHY_ADR_SW_MASTER_MODE_0 | Master delay line |
DDRSS_PHY_1071[10-0] PHY_ADR_MASTER_DELAY_START_0 | |
DDRSS_PHY_1071[21-16] PHY_ADR_MASTER_DELAY_STEP_0 | |
DDRSS_PHY_1071[31-24] PHY_ADR_MASTER_DELAY_WAIT_0 | |
DDRSS_PHY_1072[7-0] PHY_ADR_MASTER_DELAY_HALF_MEASURE_0 | |
DDRSS_PHY_1064[7-0] PHY_ADR_TSEL_SELECT_0 | Termination settings |
DDRSS_PHY_1073[3-0] PHY_ADR_CALVL_DLY_STEP_0 | CA training |
DDRSS_PHY_1074[3-0] PHY_ADR_CALVL_CAPTURE_CNT_0 | |
DDRSS_PHY_1072[17-8] PHY_ADR_SW_CALVL_DVW_MIN_0 | |
DDRSS_PHY_1072[24] PHY_ADR_SW_CALVL_DVW_MIN_EN_0 | |
DDRSS_PHY_1065[18-8] PHY_ADR0_CLK_WR_SLAVE_DELAY_0 DDRSS_PHY_1066[10-0] PHY_ADR1_CLK_WR_SLAVE_DELAY_0 DDRSS_PHY_1067[10-0] PHY_ADR2_CLK_WR_SLAVE_DELAY_0 DDRSS_PHY_1068[10-0] PHY_ADR3_CLK_WR_SLAVE_DELAY_0 DDRSS_PHY_1069[10-0] PHY_ADR4_CLK_WR_SLAVE_DELAY_0 DDRSS_PHY_1070[10-0] PHY_ADR5_CLK_WR_SLAVE_DELAY_0 | Address delay lines |
DDRSS_PHY_1064[10-8] PHY_ADR_DC_CAL_CLK_SEL_0 | Duty cycle correction |
DDRSS_PHY_1074[25-16] PHY_ADR_DC_INIT_SLV_DELAY_0 | |
DDRSS_PHY_1075[0] PHY_ADR_DC_CALVL_ENABLE_0 | |
DDRSS_PHY_1075[15-8] PHY_ADR_DC_DM_CLK_THRSHLD_0 | |
DDRSS_PHY_1064[26-16] PHY_PAD_ADR_IO_CFG_0 | Miscellaneous |
PHY Level | |
DDRSS_PHY_1396[12-0] PHY_PLL_CTRL | PLL settings |
DDRSS_PHY_1395[0] PHY_PLL_BYPASS | |
DDRSS_PHY_1405[2-0] PHY_CLK_DC_CAL_CLK_SEL | Duty cycle correction |
DDRSS_PHY_1308[7-0] PHY_CLK_DC_DM_THRSHLD | |
DDRSS_PHY_1399[10-0] PHY_GRP0_SLAVE_DELAY_0 DDRSS_PHY_1399[26-16] PHY_GRP1_SLAVE_DELAY_0 DDRSS_PHY_1400[10-0] PHY_GRP2_SLAVE_DELAY_0 DDRSS_PHY_1400[26-16] PHY_GRP3_SLAVE_DELAY_0 DDRSS_PHY_1401[10-0] PHY_GRP0_SLAVE_DELAY_1 DDRSS_PHY_1402[10-0] PHY_GRP1_SLAVE_DELAY_1 DDRSS_PHY_1403[10-0] PHY_GRP2_SLAVE_DELAY_1 DDRSS_PHY_1404[10-0] PHY_GRP3_SLAVE_DELAY_1 | Address/control delay lines |
DDRSS_PHY_1397[27-24] PHY_CSLVL_DLY_STEP | CS training |
DDRSS_PHY_1396[16] PHY_LOW_FREQ_SEL | Low frequency select |
DDRSS_PHY_1422[2-0] PHY_CAL_CLK_SELECT_0 | Calibration |
DDRSS_PHY_1422[30-24] PHY_CAL_SETTLING_PRD_0 | |
DDRSS_PHY_1422[23-8] PHY_CAL_VREF_SWITCH_TIMER_0 | |
DDRSS_PHY_1393[17-0] PHY_PAD_CAL_IO_CFG_0 | |
DDRSS_PHY_1406[29-0] PHY_PAD_FDBK_DRIVE | Pad Controls |
DDRSS_PHY_1407[17-0] PHY_PAD_FDBK_DRIVE2 | |
DDRSS_PHY_1408[30-0] PHY_PAD_DATA_DRIVE | |
DDRSS_PHY_1409[31-0] PHY_PAD_DQS_DRIVE | |
DDRSS_PHY_1410[29-0] PHY_PAD_ADDR_DRIVE | |
DDRSS_PHY_1411[26-0] PHY_PAD_ADDR_DRIVE2 | |
DDRSS_PHY_1412[31-0] PHY_PAD_CLK_DRIVE | |
DDRSS_PHY_1413[17-0] PHY_PAD_CLK_DRIVE2 |
Some register settings in the PHY are both chip select based and frequency based. For them, the PHY_PER_CS_TRAINING_INDEX_0/1/2/3 bits and the DDRSS_PHY_1281[17-16] PHY_FREQ_SEL_INDEX field apply to the register access. The DDRSS_PHY_1281[8] PHY_FREQ_SEL_MULTICAST_EN bit applies as well. Table 8-89 shows the chip select based and frequency based register settings.
Register Settings | Category |
---|---|
Data Slice | |
DDRSS_PHY_628[10-0] PHY_CLK_WRDQ0_SLAVE_DELAY_2 DDRSS_PHY_628[26-16] PHY_CLK_WRDQ1_SLAVE_DELAY_2 DDRSS_PHY_629[10-0] PHY_CLK_WRDQ2_SLAVE_DELAY_2 DDRSS_PHY_629[26-16] PHY_CLK_WRDQ3_SLAVE_DELAY_2 DDRSS_PHY_630[10-0] PHY_CLK_WRDQ4_SLAVE_DELAY_2 DDRSS_PHY_630[26-16] PHY_CLK_WRDQ5_SLAVE_DELAY_2 DDRSS_PHY_631[10-0] PHY_CLK_WRDQ6_SLAVE_DELAY_2 DDRSS_PHY_631[26-16] PHY_CLK_WRDQ7_SLAVE_DELAY_2 DDRSS_PHY_884[10-0] PHY_CLK_WRDQ0_SLAVE_DELAY_3 DDRSS_PHY_884[26-16] PHY_CLK_WRDQ1_SLAVE_DELAY_3 DDRSS_PHY_885[10-0] PHY_CLK_WRDQ2_SLAVE_DELAY_3 DDRSS_PHY_885[26-16] PHY_CLK_WRDQ3_SLAVE_DELAY_3 DDRSS_PHY_886[10-0] PHY_CLK_WRDQ4_SLAVE_DELAY_3 DDRSS_PHY_886[26-16] PHY_CLK_WRDQ5_SLAVE_DELAY_3 DDRSS_PHY_887[10-0] PHY_CLK_WRDQ6_SLAVE_DELAY_3 DDRSS_PHY_887[26-16] PHY_CLK_WRDQ7_SLAVE_DELAY_3 DDRSS_PHY_116[10-0] PHY_CLK_WRDQ0_SLAVE_DELAY_0 DDRSS_PHY_116[26-16] PHY_CLK_WRDQ1_SLAVE_DELAY_0 DDRSS_PHY_117[10-0] PHY_CLK_WRDQ2_SLAVE_DELAY_0 DDRSS_PHY_117[26-16] PHY_CLK_WRDQ3_SLAVE_DELAY_0 DDRSS_PHY_118[10-0] PHY_CLK_WRDQ4_SLAVE_DELAY_0 DDRSS_PHY_118[26-16] PHY_CLK_WRDQ5_SLAVE_DELAY_0 DDRSS_PHY_119[10-0] PHY_CLK_WRDQ6_SLAVE_DELAY_0 DDRSS_PHY_119[26-16] PHY_CLK_WRDQ7_SLAVE_DELAY_0 DDRSS_PHY_372[10-0] PHY_CLK_WRDQ0_SLAVE_DELAY_1 DDRSS_PHY_372[26-16] PHY_CLK_WRDQ1_SLAVE_DELAY_1 DDRSS_PHY_373[10-0] PHY_CLK_WRDQ2_SLAVE_DELAY_1 DDRSS_PHY_373[26-16] PHY_CLK_WRDQ3_SLAVE_DELAY_1 DDRSS_PHY_374[10-0] PHY_CLK_WRDQ4_SLAVE_DELAY_1 DDRSS_PHY_374[26-16] PHY_CLK_WRDQ5_SLAVE_DELAY_1 DDRSS_PHY_375[10-0] PHY_CLK_WRDQ6_SLAVE_DELAY_1 DDRSS_PHY_375[26-16] PHY_CLK_WRDQ7_SLAVE_DELAY_1 | Write path |
DDRSS_PHY_120[10-0] PHY_CLK_WRDM_SLAVE_DELAY_0 DDRSS_PHY_376[10-0] PHY_CLK_WRDM_SLAVE_DELAY_1 DDRSS_PHY_632[10-0] PHY_CLK_WRDM_SLAVE_DELAY_2 DDRSS_PHY_888[10-0] PHY_CLK_WRDM_SLAVE_DELAY_3 | |
DDRSS_PHY_120[25-16] PHY_CLK_WRDQS_SLAVE_DELAY_0 DDRSS_PHY_376[25-16] PHY_CLK_WRDQS_SLAVE_DELAY_1 DDRSS_PHY_632[25-16] PHY_CLK_WRDQS_SLAVE_DELAY_2 DDRSS_PHY_888[25-16] PHY_CLK_WRDQS_SLAVE_DELAY_3 | |
DDRSS_PHY_131[10-8] PHY_WRITE_PATH_LAT_ADD_0 DDRSS_PHY_387[10-8] PHY_WRITE_PATH_LAT_ADD_1 DDRSS_PHY_643[10-8] PHY_WRITE_PATH_LAT_ADD_2 DDRSS_PHY_899[10-8] PHY_WRITE_PATH_LAT_ADD_3 | |
DDRSS_PHY_136[15-8] PHY_DATA_DC_DQ0_CLK_ADJUST_0 DDRSS_PHY_136[23-16] PHY_DATA_DC_DQ1_CLK_ADJUST_0 DDRSS_PHY_136[31-24] PHY_DATA_DC_DQ2_CLK_ADJUST_0 DDRSS_PHY_137[7-0] PHY_DATA_DC_DQ3_CLK_ADJUST_0 DDRSS_PHY_137[15-8] PHY_DATA_DC_DQ4_CLK_ADJUST_0 DDRSS_PHY_137[23-16] PHY_DATA_DC_DQ5_CLK_ADJUST_0 DDRSS_PHY_137[31-24] PHY_DATA_DC_DQ6_CLK_ADJUST_0 DDRSS_PHY_138[7-0] PHY_DATA_DC_DQ7_CLK_ADJUST_0 DDRSS_PHY_392[15-8] PHY_DATA_DC_DQ0_CLK_ADJUST_1 DDRSS_PHY_392[23-16] PHY_DATA_DC_DQ1_CLK_ADJUST_1 DDRSS_PHY_392[31-24] PHY_DATA_DC_DQ2_CLK_ADJUST_1 DDRSS_PHY_393[7-0] PHY_DATA_DC_DQ3_CLK_ADJUST_1 DDRSS_PHY_393[15-8] PHY_DATA_DC_DQ4_CLK_ADJUST_1 DDRSS_PHY_393[23-16] PHY_DATA_DC_DQ5_CLK_ADJUST_1 DDRSS_PHY_393[31-24] PHY_DATA_DC_DQ6_CLK_ADJUST_1 DDRSS_PHY_394[7-0] PHY_DATA_DC_DQ7_CLK_ADJUST_1 DDRSS_PHY_648[15-8] PHY_DATA_DC_DQ0_CLK_ADJUST_2 DDRSS_PHY_648[23-16] PHY_DATA_DC_DQ1_CLK_ADJUST_2 DDRSS_PHY_648[31-24] PHY_DATA_DC_DQ2_CLK_ADJUST_2 DDRSS_PHY_649[7-0] PHY_DATA_DC_DQ3_CLK_ADJUST_2 DDRSS_PHY_649[15-8] PHY_DATA_DC_DQ4_CLK_ADJUST_2 DDRSS_PHY_649[23-16] PHY_DATA_DC_DQ5_CLK_ADJUST_2 DDRSS_PHY_649[31-24] PHY_DATA_DC_DQ6_CLK_ADJUST_2 DDRSS_PHY_650[7-0] PHY_DATA_DC_DQ7_CLK_ADJUST_2 DDRSS_PHY_904[15-8] PHY_DATA_DC_DQ0_CLK_ADJUST_3 DDRSS_PHY_904[23-16] PHY_DATA_DC_DQ1_CLK_ADJUST_3 DDRSS_PHY_904[31-24] PHY_DATA_DC_DQ2_CLK_ADJUST_3 DDRSS_PHY_905[7-0] PHY_DATA_DC_DQ3_CLK_ADJUST_3 DDRSS_PHY_905[15-8] PHY_DATA_DC_DQ4_CLK_ADJUST_3 DDRSS_PHY_905[23-16] PHY_DATA_DC_DQ5_CLK_ADJUST_3 DDRSS_PHY_905[31-24] PHY_DATA_DC_DQ6_CLK_ADJUST_3 DDRSS_PHY_906[7-0] PHY_DATA_DC_DQ7_CLK_ADJUST_3 | Duty cycle correction |
DDRSS_PHY_138[15-8] PHY_DATA_DC_DM_CLK_ADJUST_0 DDRSS_PHY_394[15-8] PHY_DATA_DC_DM_CLK_ADJUST_1 DDRSS_PHY_650[15-8] PHY_DATA_DC_DM_CLK_ADJUST_2 DDRSS_PHY_906[15-8] PHY_DATA_DC_DM_CLK_ADJUST_3 | Duty cycle correction |
DDRSS_PHY_136[7-0] PHY_DATA_DC_DQS_CLK_ADJUST_0 DDRSS_PHY_392[7-0] PHY_DATA_DC_DQS_CLK_ADJUST_1 DDRSS_PHY_648[7-0] PHY_DATA_DC_DQS_CLK_ADJUST_2 DDRSS_PHY_904[7-0] PHY_DATA_DC_DQS_CLK_ADJUST_3 | |
DDRSS_PHY_131[25-16] PHY_WRLVL_DELAY_EARLY_THRESHOLD_0 DDRSS_PHY_387[25-16] PHY_WRLVL_DELAY_EARLY_THRESHOLD_1 DDRSS_PHY_643[25-16] PHY_WRLVL_DELAY_EARLY_THRESHOLD_2 DDRSS_PHY_899[25-16] PHY_WRLVL_DELAY_EARLY_THRESHOLD_3 | Write leveling |
DDRSS_PHY_132[9-0] PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0 DDRSS_PHY_388[9-0] PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1 DDRSS_PHY_644[9-0] PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2 DDRSS_PHY_900[9-0] PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3 | |
DDRSS_PHY_132[16] PHY_WRLVL_EARLY_FORCE_ZERO_0 DDRSS_PHY_388[16] PHY_WRLVL_EARLY_FORCE_ZERO_1 DDRSS_PHY_644[16] PHY_WRLVL_EARLY_FORCE_ZERO_2 DDRSS_PHY_900[16] PHY_WRLVL_EARLY_FORCE_ZERO_3 | |
DDRSS_PHY_121[1-0] PHY_WRLVL_THRESHOLD_ADJUST_0 DDRSS_PHY_377[1-0] PHY_WRLVL_THRESHOLD_ADJUST_1 DDRSS_PHY_633[1-0] PHY_WRLVL_THRESHOLD_ADJUST_2 DDRSS_PHY_889[1-0] PHY_WRLVL_THRESHOLD_ADJUST_3 | |
DDRSS_PHY_134[10-0] PHY_WDQLVL_DQDM_SLV_DLY_START_0 DDRSS_PHY_390[10-0] PHY_WDQLVL_DQDM_SLV_DLY_START_1 DDRSS_PHY_646[10-0] PHY_WDQLVL_DQDM_SLV_DLY_START_2 DDRSS_PHY_902[10-0] PHY_WDQLVL_DQDM_SLV_DLY_START_3 | Write DQ training |
DDRSS_PHY_134[19-16] PHY_NTP_WRLAT_START_0 DDRSS_PHY_390[19-16] PHY_NTP_WRLAT_START_1 DDRSS_PHY_646[19-16] PHY_NTP_WRLAT_START_2 DDRSS_PHY_902[19-16] PHY_NTP_WRLAT_START_3 | |
DDRSS_PHY_134[24] PHY_NTP_PASS_0 DDRSS_PHY_390[24] PHY_NTP_PASS_1 DDRSS_PHY_646[24] PHY_NTP_PASS_2 DDRSS_PHY_902[24] PHY_NTP_PASS_3 | |
DDRSS_PHY_121[17-8] PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0 DDRSS_PHY_122[25-16] PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0 DDRSS_PHY_123[25-16] PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0 DDRSS_PHY_124[25-16] PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0 DDRSS_PHY_125[25-16] PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0 DDRSS_PHY_126[25-16] PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0 DDRSS_PHY_127[25-16] PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0 DDRSS_PHY_128[25-16] PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0 DDRSS_PHY_377[17-8] PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1 DDRSS_PHY_378[25-16] PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1 DDRSS_PHY_379[25-16] PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1 DDRSS_PHY_380[25-16] PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1 DDRSS_PHY_381[25-16] PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1 DDRSS_PHY_382[25-16] PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1 DDRSS_PHY_383[25-16] PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1 DDRSS_PHY_384[25-16] PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1 DDRSS_PHY_633[17-8] PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2 DDRSS_PHY_634[25-16] PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2 DDRSS_PHY_635[25-16] PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2 DDRSS_PHY_636[25-16] PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2 DDRSS_PHY_637[25-16] PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2 DDRSS_PHY_638[25-16] PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2 DDRSS_PHY_639[25-16] PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2 DDRSS_PHY_640[25-16] PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2 DDRSS_PHY_889[17-8] PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3 DDRSS_PHY_890[25-16] PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3 DDRSS_PHY_891[25-16] PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3 DDRSS_PHY_892[25-16] PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3 DDRSS_PHY_893[25-16] PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3 DDRSS_PHY_894[25-16] PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3 DDRSS_PHY_895[25-16] PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3 DDRSS_PHY_896[25-16] PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3 | Read path |
DDRSS_PHY_122[9-0] PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0 DDRSS_PHY_123[9-0] PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0 DDRSS_PHY_124[9-0] PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0 DDRSS_PHY_125[9-0] PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0 DDRSS_PHY_126[9-0] PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0 DDRSS_PHY_127[9-0] PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0 DDRSS_PHY_128[9-0] PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0 DDRSS_PHY_129[9-0] PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0 DDRSS_PHY_378[9-0] PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1 DDRSS_PHY_379[9-0] PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1 DDRSS_PHY_380[9-0] PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1 DDRSS_PHY_381[9-0] PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1 DDRSS_PHY_382[9-0] PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1 DDRSS_PHY_383[9-0] PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1 DDRSS_PHY_384[9-0] PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1 DDRSS_PHY_385[9-0] PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1 DDRSS_PHY_634[9-0] PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2 DDRSS_PHY_635[9-0] PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2 DDRSS_PHY_636[9-0] PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2 DDRSS_PHY_637[9-0] PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2 DDRSS_PHY_638[9-0] PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2 DDRSS_PHY_639[9-0] PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2 DDRSS_PHY_640[9-0] PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2 DDRSS_PHY_641[9-0] PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2 DDRSS_PHY_890[9-0] PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3 DDRSS_PHY_891[9-0] PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3 DDRSS_PHY_892[9-0] PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3 DDRSS_PHY_893[9-0] PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3 DDRSS_PHY_894[9-0] PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3 DDRSS_PHY_895[9-0] PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3 DDRSS_PHY_896[9-0] PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3 DDRSS_PHY_897[9-0] PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3 | Read path |
DDRSS_PHY_129[25-16] PHY_RDDQS_DM_RISE_SLAVE_DELAY_0 DDRSS_PHY_385[25-16] PHY_RDDQS_DM_RISE_SLAVE_DELAY_1 DDRSS_PHY_641[25-16] PHY_RDDQS_DM_RISE_SLAVE_DELAY_2 DDRSS_PHY_897[25-16] PHY_RDDQS_DM_RISE_SLAVE_DELAY_3 | Read path |
DDRSS_PHY_130[9-0] PHY_RDDQS_DM_FALL_SLAVE_DELAY_0 DDRSS_PHY_386[9-0] PHY_RDDQS_DM_FALL_SLAVE_DELAY_1 DDRSS_PHY_642[9-0] PHY_RDDQS_DM_FALL_SLAVE_DELAY_2 DDRSS_PHY_898[9-0] PHY_RDDQS_DM_FALL_SLAVE_DELAY_3 | |
DDRSS_PHY_130[25-16] PHY_RDDQS_GATE_SLAVE_DELAY_0 DDRSS_PHY_386[25-16] PHY_RDDQS_GATE_SLAVE_DELAY_1 DDRSS_PHY_642[25-16] PHY_RDDQS_GATE_SLAVE_DELAY_2 DDRSS_PHY_898[25-16] PHY_RDDQS_GATE_SLAVE_DELAY_3 | |
DDRSS_PHY_131[3-0] PHY_RDDQS_LATENCY_ADJUST_0 DDRSS_PHY_387[3-0] PHY_RDDQS_LATENCY_ADJUST_1 DDRSS_PHY_643[3-0] PHY_RDDQS_LATENCY_ADJUST_2 DDRSS_PHY_899[3-0] PHY_RDDQS_LATENCY_ADJUST_3 | |
DDRSS_PHY_133[9-0] PHY_GTLVL_RDDQS_SLV_DLY_START_0 DDRSS_PHY_389[9-0] PHY_GTLVL_RDDQS_SLV_DLY_START_1 DDRSS_PHY_645[9-0] PHY_GTLVL_RDDQS_SLV_DLY_START_2 DDRSS_PHY_901[9-0] PHY_GTLVL_RDDQS_SLV_DLY_START_3 | Gate training |
DDRSS_PHY_133[19-16] PHY_GTLVL_LAT_ADJ_START_0 DDRSS_PHY_389[19-16] PHY_GTLVL_LAT_ADJ_START_1 DDRSS_PHY_645[19-16] PHY_GTLVL_LAT_ADJ_START_2 DDRSS_PHY_901[19-16] PHY_GTLVL_LAT_ADJ_START_3 | |
DDRSS_PHY_135[9-0] PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0 DDRSS_PHY_391[9-0] PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1 DDRSS_PHY_647[9-0] PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2 DDRSS_PHY_903[9-0] PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3 | Read data eye training |
DDRSS_PHY_138[31-16] PHY_DSLICE_PAD_BOOSTPN_SETTING_0 DDRSS_PHY_394[31-16] PHY_DSLICE_PAD_BOOSTPN_SETTING_1 DDRSS_PHY_650[31-16] PHY_DSLICE_PAD_BOOSTPN_SETTING_2 DDRSS_PHY_906[31-16] PHY_DSLICE_PAD_BOOSTPN_SETTING_3 | Miscellaneous |
DDRSS_PHY_139[5-0] PHY_DSLICE_PAD_RX_CTLE_SETTING_0 DDRSS_PHY_395[5-0] PHY_DSLICE_PAD_RX_CTLE_SETTING_1 DDRSS_PHY_651[5-0] PHY_DSLICE_PAD_RX_CTLE_SETTING_2 DDRSS_PHY_907[5-0] PHY_DSLICE_PAD_RX_CTLE_SETTING_3 |