Table 8-3266 lists the DDRSS0_ECC_AGGR_CFG registers. All register offset addresses not listed in Table 8-3266 should be considered as reserved locations and the register contents should not be modified.
Table 8-3265 DDRSS0_ECC_AGGR_CFG Instances Table 8-3266 DDRSS0_ECC_AGGR_CFG Registers 2.5.7.1 DDRSS_REV Register (Offset = 0h) [reset = 66A02A01h]
DDRSS_REV is shown in Figure 8-1625 and described in Table 8-3268.
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Revision parameters
Table 8-3267 DDRSS_REV InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 0800h |
Figure 8-1625 DDRSS_REV Register LEGEND: R = Read Only; -n = value after reset |
Table 8-3268 DDRSS_REV Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | bu |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 5h | RTL version |
10-8 | REVMAJ | R | 2h | Major version |
7-6 | CUSTOM | R | 0h | Custom version |
5-0 | REVMIN | R | 1h | Minor version |
2.5.7.2 DDRSS_VECTOR Register (Offset = 8h) [reset = X]
DDRSS_VECTOR is shown in Figure 8-1626 and described in Table 8-3270.
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ECC Vector Register
Table 8-3269 DDRSS_VECTOR InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 0808h |
Figure 8-1626 DDRSS_VECTOR Register LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3270 DDRSS_VECTOR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-25 | RESERVED | R | X | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R | X | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
2.5.7.3 DDRSS_STAT Register (Offset = Ch) [reset = X]
DDRSS_STAT is shown in Figure 8-1627 and described in Table 8-3272.
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Misc Status
Table 8-3271 DDRSS_STAT InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 080Ch |
Figure 8-1627 DDRSS_STAT Register LEGEND: R = Read Only; -n = value after reset |
Table 8-3272 DDRSS_STAT Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-11 | RESERVED | R | X | Reserved |
10-0 | NUM_RAMS | R | 6h | Indicates the number of RAMS serviced by the ECC aggregator |
2.5.7.4 DDRSS_RESERVED_SVBUS_y Register (Offset = 10h + formula) [reset = 0h]
DDRSS_RESERVED_SVBUS_y is shown in Figure 8-1628 and described in Table 8-3274.
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Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets.
Offset = 10h + (y * 4h); where y = 0h to 7h
Table 8-3273 DDRSS_RESERVED_SVBUS_y InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 0810h + formula |
Figure 8-1628 DDRSS_RESERVED_SVBUS_y Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 8-3274 DDRSS_RESERVED_SVBUS_y Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | DATA | R/W | 0h | Serial VBUS register data |
2.5.7.5 DDRSS_SEC_EOI_REG Register (Offset = 3Ch) [reset = X]
DDRSS_SEC_EOI_REG is shown in Figure 8-1629 and described in Table 8-3276.
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EOI Register
Table 8-3275 DDRSS_SEC_EOI_REG InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 083Ch |
Figure 8-1629 DDRSS_SEC_EOI_REG Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3276 DDRSS_SEC_EOI_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-1 | RESERVED | R | X | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI Register |
2.5.7.6 DDRSS_SEC_STATUS_REG0 Register (Offset = 40h) [reset = X]
DDRSS_SEC_STATUS_REG0 is shown in Figure 8-1630 and described in Table 8-3278.
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Interrupt Status Register 0
Table 8-3277 DDRSS_SEC_STATUS_REG0 InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 0840h |
Figure 8-1630 DDRSS_SEC_STATUS_REG0 Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3278 DDRSS_SEC_STATUS_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-6 | RESERVED | R | X | Reserved |
5 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend |
4 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_scr_scr_ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend |
3 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend |
2 | DST_M2P_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for dst_m2p_busecc_pend |
1 | M2M_M2M_VBUSS_PEND | R/W1S | 0h | Interrupt Pending Status for m2m_m2m_vbuss_pend |
0 | M2M_DST_VBUSS_PEND | R/W1S | 0h | Interrupt Pending Status for m2m_dst_vbuss_pend |
2.5.7.7 DDRSS_SEC_ENABLE_SET_REG0 Register (Offset = 80h) [reset = X]
DDRSS_SEC_ENABLE_SET_REG0 is shown in Figure 8-1631 and described in Table 8-3280.
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Interrupt Enable Set Register 0
Table 8-3279 DDRSS_SEC_ENABLE_SET_REG0 InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 0880h |
Figure 8-1631 DDRSS_SEC_ENABLE_SET_REG0 Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3280 DDRSS_SEC_ENABLE_SET_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-6 | RESERVED | R | X | Reserved |
5 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend |
4 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_scr_scr_ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend |
3 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend |
2 | DST_M2P_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for dst_m2p_busecc_pend |
1 | M2M_M2M_VBUSS_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for m2m_m2m_vbuss_pend |
0 | M2M_DST_VBUSS_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for m2m_dst_vbuss_pend |
2.5.7.8 DDRSS_SEC_ENABLE_CLR_REG0 Register (Offset = C0h) [reset = X]
DDRSS_SEC_ENABLE_CLR_REG0 is shown in Figure 8-1632 and described in Table 8-3282.
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Interrupt Enable Clear Register 0
Table 8-3281 DDRSS_SEC_ENABLE_CLR_REG0 InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 08C0h |
Figure 8-1632 DDRSS_SEC_ENABLE_CLR_REG0 Register LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 8-3282 DDRSS_SEC_ENABLE_CLR_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-6 | RESERVED | R | X | Reserved |
5 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend |
4 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_scr_scr_ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend |
3 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend |
2 | DST_M2P_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for dst_m2p_busecc_pend |
1 | M2M_M2M_VBUSS_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for m2m_m2m_vbuss_pend |
0 | M2M_DST_VBUSS_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for m2m_dst_vbuss_pend |
2.5.7.9 DDRSS_DED_EOI_REG Register (Offset = 13Ch) [reset = X]
DDRSS_DED_EOI_REG is shown in Figure 8-1633 and described in Table 8-3284.
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EOI Register
Table 8-3283 DDRSS_DED_EOI_REG InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 093Ch |
Figure 8-1633 DDRSS_DED_EOI_REG Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3284 DDRSS_DED_EOI_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-1 | RESERVED | R | X | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI Register |
2.5.7.10 DDRSS_DED_STATUS_REG0 Register (Offset = 140h) [reset = X]
DDRSS_DED_STATUS_REG0 is shown in Figure 8-1634 and described in Table 8-3286.
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Interrupt Status Register 0
Table 8-3285 DDRSS_DED_STATUS_REG0 InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 0940h |
Figure 8-1634 DDRSS_DED_STATUS_REG0 Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3286 DDRSS_DED_STATUS_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-6 | RESERVED | R | X | Reserved |
5 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend |
4 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_scr_scr_ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend |
3 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend |
2 | DST_M2P_BUSECC_PEND | R/W1S | 0h | Interrupt Pending Status for dst_m2p_busecc_pend |
1 | M2M_M2M_VBUSS_PEND | R/W1S | 0h | Interrupt Pending Status for m2m_m2m_vbuss_pend |
0 | M2M_DST_VBUSS_PEND | R/W1S | 0h | Interrupt Pending Status for m2m_dst_vbuss_pend |
2.5.7.11 DDRSS_DED_ENABLE_SET_REG0 Register (Offset = 180h) [reset = X]
DDRSS_DED_ENABLE_SET_REG0 is shown in Figure 8-1635 and described in Table 8-3288.
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Interrupt Enable Set Register 0
Table 8-3287 DDRSS_DED_ENABLE_SET_REG0 InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 0980h |
Figure 8-1635 DDRSS_DED_ENABLE_SET_REG0 Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3288 DDRSS_DED_ENABLE_SET_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-6 | RESERVED | R | X | Reserved |
5 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend |
4 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_scr_scr_ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend |
3 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend |
2 | DST_M2P_BUSECC_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for dst_m2p_busecc_pend |
1 | M2M_M2M_VBUSS_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for m2m_m2m_vbuss_pend |
0 | M2M_DST_VBUSS_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for m2m_dst_vbuss_pend |
2.5.7.12 DDRSS_DED_ENABLE_CLR_REG0 Register (Offset = 1C0h) [reset = X]
DDRSS_DED_ENABLE_CLR_REG0 is shown in Figure 8-1636 and described in Table 8-3290.
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Interrupt Enable Clear Register 0
Table 8-3289 DDRSS_DED_ENABLE_CLR_REG0 InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 09C0h |
Figure 8-1636 DDRSS_DED_ENABLE_CLR_REG0 Register LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 8-3290 DDRSS_DED_ENABLE_CLR_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-6 | RESERVED | R | X | Reserved |
5 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CTL_CFG_P2P_BRIDGE_CTL_CFG_BRIDGE_SRC_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_ctl_cfg_p2p_bridge_ctl_cfg_bridge_src_busecc_pend |
4 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_SCR_SCR_EDC_CTRL_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_scr_scr_ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_scr_scr_edc_ctrl_busecc_pend |
3 | DDR32V256SS_16FFC_EW_DV_WRAP_DDRSS_BRCTL_SC_CBASS_CFG_GCLK_EDC_CTRL_CBASS_INT_CFG_GBUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ddr32v256ss_16ffc_ew_dv_wrap_ddrss_brctl_sc_cbass_cfg_gclk_edc_ctrl_cbass_int_cfg_gbusecc_pend |
2 | DST_M2P_BUSECC_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for dst_m2p_busecc_pend |
1 | M2M_M2M_VBUSS_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for m2m_m2m_vbuss_pend |
0 | M2M_DST_VBUSS_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for m2m_dst_vbuss_pend |
2.5.7.13 DDRSS_AGGR_ENABLE_SET Register (Offset = 200h) [reset = X]
DDRSS_AGGR_ENABLE_SET is shown in Figure 8-1637 and described in Table 8-3292.
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AGGR interrupt enable set Register
Table 8-3291 DDRSS_AGGR_ENABLE_SET InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 0A00h |
Figure 8-1637 DDRSS_AGGR_ENABLE_SET Register LEGEND: R = Read Only; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 8-3292 DDRSS_AGGR_ENABLE_SET Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-2 | RESERVED | R | X | Reserved |
1 | TIMEOUT | R/W1S | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | interrupt enable set for parity errors |
2.5.7.14 DDRSS_AGGR_ENABLE_CLR Register (Offset = 204h) [reset = X]
DDRSS_AGGR_ENABLE_CLR is shown in Figure 8-1638 and described in Table 8-3294.
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AGGR interrupt enable clear Register
Table 8-3293 DDRSS_AGGR_ENABLE_CLR InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 0A04h |
Figure 8-1638 DDRSS_AGGR_ENABLE_CLR Register LEGEND: R = Read Only; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 8-3294 DDRSS_AGGR_ENABLE_CLR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-2 | RESERVED | R | X | Reserved |
1 | TIMEOUT | R/W1C | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | interrupt enable clear for parity errors |
2.5.7.15 DDRSS_AGGR_STATUS_SET Register (Offset = 208h) [reset = X]
DDRSS_AGGR_STATUS_SET is shown in Figure 8-1639 and described in Table 8-3296.
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AGGR interrupt status set Register
Table 8-3295 DDRSS_AGGR_STATUS_SET InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 0A08h |
Figure 8-1639 DDRSS_AGGR_STATUS_SET Register LEGEND: R = Read Only; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Table 8-3296 DDRSS_AGGR_STATUS_SET Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-4 | RESERVED | R | X | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | interrupt status set for svbus timeout errors |
1-0 | PARITY | R/Wincr | 0h | interrupt status set for parity errors |
2.5.7.16 DDRSS_AGGR_STATUS_CLR Register (Offset = 20Ch) [reset = X]
DDRSS_AGGR_STATUS_CLR is shown in Figure 8-1640 and described in Table 8-3298.
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AGGR interrupt status clear Register
Table 8-3297 DDRSS_AGGR_STATUS_CLR InstancesInstance | Physical Address |
---|
COMPUTE_CLUSTER0_ECC_AGGR_CFG | 4D200B 0A0Ch |
Figure 8-1640 DDRSS_AGGR_STATUS_CLR Register LEGEND: R = Read Only; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Table 8-3298 DDRSS_AGGR_STATUS_CLR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-4 | RESERVED | R | X | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/Wdecr | 0h | interrupt status clear for parity errors |