SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Figure 12-2 shows the ADC signals.
Table 12-2 describes the ADC I/O signals.
Module Pin | Device Level Signal | I/O(1) | Description | Module Pin Reset Value(2) |
---|---|---|---|---|
MCU_ADC0 | ||||
AIN0 | MCU_ADC0_AIN0 | A/I | Analog input 0 | HiZ |
AIN1 | MCU_ADC0_AIN1 | A/I | Analog input 1 | HiZ |
AIN2 | MCU_ADC0_AIN2 | A/I | Analog input 2 | HiZ |
AIN3 | MCU_ADC0_AIN3 | A/I | Analog input 3 | HiZ |
AIN4 | MCU_ADC0_AIN4 | A/I | Analog input 4 | HiZ |
AIN5 | MCU_ADC0_AIN5 | A/I | Analog input 5 | HiZ |
AIN6 | MCU_ADC0_AIN6 | A/I | Analog input 6 | HiZ |
AIN7 | MCU_ADC0_AIN7 | A/I | Analog input 7 | HiZ |
REFP | VDDA_ADC0 | PWR | Reference voltage input positive | - |
REFN | VSS | GND | Reference voltage input negative | - |
EXT_TRIGGER0 | MCU_ADC_EXT_TRIGGER0 | I | External trigger for ADC | HiZ |
EXT_TRIGGER1 | MCU_ADC_EXT_TRIGGER1 | I | External trigger for ADC | HiZ |
For more information about device level signals (pull-up/down resistors, buffer type, multiplexing and others), see tables Pin Attributes and Pin Multiplexing in the device-specific Datasheet.