SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
The CTRL_MMR0 module has a protection mechanism which prevents spurious writes from changing the values of its registers. The LOCKi_KICK0 and LOCKi_KICK1 registers are used for this purpose. A write is required first to the LOCKi_KICK0[31-1] KEY field and then to the LOCKi_KICK1[31-0] KEY field with exact data values to unlock the protection mechanism. Once released then all registers within Partition "i" having write permissions can be written to. The read only registers are still read only. An indication for unlocked Partition "i" is when the LOCKi_KICK0[0] UNLOCKED bit is set to 1h. When the protection mechanism is locked (indicated by LOCKi_KICK0[0] UNLOCKED = 0h) none of the registers within Partition "i" can be written to. They can only be read.
Table 5-686 shows the values that must be written to the LOCKi_KICK0 and LOCKi_KICK1 registers to unlock each partition. Writing any other data value to either of these registers locks the protection mechanism and blocks any writes to the registers that reside in Partition "i".
Register | Partition(1) | Unlock Value | Offset Range |
---|---|---|---|
CTRLMMR_LOCK0_KICK0 | Partition 0 | 68EF 3490h | 0000h to 1FFFh |
CTRLMMR_LOCK0_KICK1 | Partition 0 | D172 BC5Ah | |
CTRLMMR_LOCK1_KICK0 | Partition 1 | 68EF 3490h | 4000h to 5FFFh |
CTRLMMR_LOCK1_KICK1 | Partition 1 | D172 BC5Ah | |
CTRLMMR_LOCK2_KICK0 | Partition 2 | 68EF 3490h | 8000h to 9FFFh |
CTRLMMR_LOCK2_KICK1 | Partition 2 | D172 BC5Ah | |
CTRLMMR_LOCK3_KICK0 | Partition 3 | 68EF 3490h | C000h to DFFFh |
CTRLMMR_LOCK3_KICK1 | Partition 3 | D172 BC5Ah | |
CTRLMMR_LOCK5_KICK0 | Partition 5 | 68EF 3490h | 1 4000h to 1 5FFFh |
CTRLMMR_LOCK5_KICK1 | Partition 5 | D172 BC5Ah | |
CTRLMMR_LOCK7_KICK0 | Partition 7 | 68EF 3490h | 1 C000h to 1 DFFFh |
CTRLMMR_LOCK7_KICK1 | Partition 7 | D172 BC5Ah |
In order to ensure that all registers from all partitions are write protected, software must always re-lock the protection mechanism after completing the register writes.
The following registers are exceptions and are not write protected by the LOCKi_KICK0 and LOCKi_KICK1 registers:
The Inter-processor Communication Registers registers are not write protected in order to reduce the access latency.