Table 12-1686 lists the memory-mapped registers for the MCU_CPSW0_ECC. All register offset addresses not listed in Table 12-1686 should be considered as reserved locations and the register contents should not be modified.
Table 12-1685 MCU_CPSW0_ECC Instances Table 12-1686 MCU_CPSW0_ECC Registers 1.6.11.1 CPSW_ECC_REV Register (Offset = 0h) [reset = 66A0EA00h]
CPSW_ECC_REV is shown in Figure 12-873 and described in Table 12-1688.
Return to Summary Table.
Revision parameters
Table 12-1687 CPSW_ECC_REV InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 9000h |
Figure 12-873 CPSW_ECC_REV Register LEGEND: R = Read Only; -n = value after reset |
Table 12-1688 CPSW_ECC_REV Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-30 | SCHEME | R | 1h | Scheme |
29-28 | BU | R | 2h | bu |
27-16 | MODULE_ID | R | 6A0h | Module ID |
15-11 | REVRTL | R | 1Dh | RTL version |
10-8 | REVMAJ | R | 2h | Major version |
7-6 | CUSTOM | R | 0h | Custom version |
5-0 | REVMIN | R | 0h | Minor version |
1.6.11.2 CPSW_ECC_VECTOR Register (Offset = 8h) [reset = X]
CPSW_ECC_VECTOR is shown in Figure 12-874 and described in Table 12-1690.
Return to Summary Table.
ECC Vector Register
Table 12-1689 CPSW_ECC_VECTOR InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 9008h |
Figure 12-874 CPSW_ECC_VECTOR Register LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 12-1690 CPSW_ECC_VECTOR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-25 | RESERVED | R/W | X | |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R/W | X | |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
1.6.11.3 CPSW_ECC_STAT Register (Offset = Ch) [reset = X]
CPSW_ECC_STAT is shown in Figure 12-875 and described in Table 12-1692.
Return to Summary Table.
Misc Status
Table 12-1691 CPSW_ECC_STAT InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 900Ch |
Figure 12-875 CPSW_ECC_STAT Register LEGEND: R = Read Only; -n = value after reset |
Table 12-1692 CPSW_ECC_STAT Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-11 | RESERVED | R | X | |
10-0 | NUM_RAMS | R | 14h | Indicates the number of RAMS serviced by the ECC aggregator |
1.6.11.4 CPSW_ECC_RESERVED_SVBUS_y Register (Offset = 10h + formula) [reset = 0h]
CPSW_ECC_RESERVED_SVBUS_y is shown in Figure 12-876 and described in Table 12-1694.
Return to Summary Table.
Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets.
Offset = 10h + (y * 4h); where y = 0h to 7h
Table 12-1693 CPSW_ECC_RESERVED_SVBUS_y InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 9010h + formula |
Figure 12-876 CPSW_ECC_RESERVED_SVBUS_y Register LEGEND: R/W = Read/Write; -n = value after reset |
Table 12-1694 CPSW_ECC_RESERVED_SVBUS_y Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-0 | DATA | R/W | 0h | Serial VBUS register data |
1.6.11.5 CPSW_ECC_SEC_EOI_REG Register (Offset = 3Ch) [reset = X]
CPSW_ECC_SEC_EOI_REG is shown in Figure 12-877 and described in Table 12-1696.
Return to Summary Table.
EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Table 12-1695 CPSW_ECC_SEC_EOI_REG InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 903Ch |
Figure 12-877 CPSW_ECC_SEC_EOI_REG Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 12-1696 CPSW_ECC_SEC_EOI_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register |
1.6.11.6 CPSW_ECC_SEC_STATUS_REG0 Register (Offset = 40h) [reset = X]
CPSW_ECC_SEC_STATUS_REG0 is shown in Figure 12-878 and described in Table 12-1698.
Return to Summary Table.
Interrupt Status Register 0
Table 12-1697 CPSW_ECC_SEC_STATUS_REG0 InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 9040h |
Figure 12-878 CPSW_ECC_SEC_STATUS_REG0 Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 12-1698 CPSW_ECC_SEC_STATUS_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-20 | RESERVED | R/W | X | |
19 | RAMECC19_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc19_pend |
18 | RAMECC18_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc18_pend |
17 | RAMECC17_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc17_pend |
16 | RAMECC16_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc16_pend |
15 | RAMECC15_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc15_pend |
14 | RAMECC14_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc14_pend |
13 | RAMECC13_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc13_pend |
12 | RAMECC12_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc12_pend |
11 | RAMECC11_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc11_pend |
10 | RAMECC10_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc10_pend |
9 | RAMECC9_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc9_pend |
8 | RAMECC8_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc8_pend |
7 | RAMECC7_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc7_pend |
6 | RAMECC6_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc6_pend |
5 | RAMECC5_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc5_pend |
4 | RAMECC4_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc4_pend |
3 | RAMECC3_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc3_pend |
2 | RAMECC2_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc2_pend |
1 | RAMECC1_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc1_pend |
0 | RAMECC0_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc0_pend |
1.6.11.7 CPSW_ECC_SEC_ENABLE_SET_REG0 Register (Offset = 80h) [reset = X]
CPSW_ECC_SEC_ENABLE_SET_REG0 is shown in Figure 12-879 and described in Table 12-1700.
Return to Summary Table.
Interrupt Enable Set Register 0
Table 12-1699 CPSW_ECC_SEC_ENABLE_SET_REG0 InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 9080h |
Figure 12-879 CPSW_ECC_SEC_ENABLE_SET_REG0 Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 12-1700 CPSW_ECC_SEC_ENABLE_SET_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-20 | RESERVED | R/W | X | |
19 | RAMECC19_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc19_pend |
18 | RAMECC18_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc18_pend |
17 | RAMECC17_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc17_pend |
16 | RAMECC16_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc16_pend |
15 | RAMECC15_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc15_pend |
14 | RAMECC14_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc14_pend |
13 | RAMECC13_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc13_pend |
12 | RAMECC12_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc12_pend |
11 | RAMECC11_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc11_pend |
10 | RAMECC10_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc10_pend |
9 | RAMECC9_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc9_pend |
8 | RAMECC8_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc8_pend |
7 | RAMECC7_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc7_pend |
6 | RAMECC6_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc6_pend |
5 | RAMECC5_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc5_pend |
4 | RAMECC4_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc4_pend |
3 | RAMECC3_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc3_pend |
2 | RAMECC2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc2_pend |
1 | RAMECC1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc1_pend |
0 | RAMECC0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc0_pend |
1.6.11.8 CPSW_ECC_SEC_ENABLE_CLR_REG0 Register (Offset = C0h) [reset = X]
CPSW_ECC_SEC_ENABLE_CLR_REG0 is shown in Figure 12-880 and described in Table 12-1702.
Return to Summary Table.
Interrupt Enable Clear Register 0
Table 12-1701 CPSW_ECC_SEC_ENABLE_CLR_REG0 InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 90C0h |
Figure 12-880 CPSW_ECC_SEC_ENABLE_CLR_REG0 Register LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 12-1702 CPSW_ECC_SEC_ENABLE_CLR_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-20 | RESERVED | R/W | X | |
19 | RAMECC19_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc19_pend |
18 | RAMECC18_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc18_pend |
17 | RAMECC17_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc17_pend |
16 | RAMECC16_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc16_pend |
15 | RAMECC15_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc15_pend |
14 | RAMECC14_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc14_pend |
13 | RAMECC13_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc13_pend |
12 | RAMECC12_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc12_pend |
11 | RAMECC11_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc11_pend |
10 | RAMECC10_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc10_pend |
9 | RAMECC9_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc9_pend |
8 | RAMECC8_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc8_pend |
7 | RAMECC7_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc7_pend |
6 | RAMECC6_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc6_pend |
5 | RAMECC5_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc5_pend |
4 | RAMECC4_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc4_pend |
3 | RAMECC3_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc3_pend |
2 | RAMECC2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc2_pend |
1 | RAMECC1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc1_pend |
0 | RAMECC0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc0_pend |
1.6.11.9 CPSW_ECC_DED_EOI_REG Register (Offset = 13Ch) [reset = X]
CPSW_ECC_DED_EOI_REG is shown in Figure 12-881 and described in Table 12-1704.
Return to Summary Table.
EOI Register
The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Table 12-1703 CPSW_ECC_DED_EOI_REG InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 913Ch |
Figure 12-881 CPSW_ECC_DED_EOI_REG Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 12-1704 CPSW_ECC_DED_EOI_REG Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-1 | RESERVED | R/W | X | |
0 | EOI_WR | R/W1S | 0h | EOI Register |
1.6.11.10 CPSW_ECC_DED_STATUS_REG0 Register (Offset = 140h) [reset = X]
CPSW_ECC_DED_STATUS_REG0 is shown in Figure 12-882 and described in Table 12-1706.
Return to Summary Table.
Interrupt Status Register 0
Table 12-1705 CPSW_ECC_DED_STATUS_REG0 InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 9140h |
Figure 12-882 CPSW_ECC_DED_STATUS_REG0 Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 12-1706 CPSW_ECC_DED_STATUS_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-20 | RESERVED | R/W | X | |
19 | RAMECC19_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc19_pend |
18 | RAMECC18_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc18_pend |
17 | RAMECC17_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc17_pend |
16 | RAMECC16_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc16_pend |
15 | RAMECC15_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc15_pend |
14 | RAMECC14_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc14_pend |
13 | RAMECC13_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc13_pend |
12 | RAMECC12_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc12_pend |
11 | RAMECC11_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc11_pend |
10 | RAMECC10_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc10_pend |
9 | RAMECC9_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc9_pend |
8 | RAMECC8_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc8_pend |
7 | RAMECC7_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc7_pend |
6 | RAMECC6_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc6_pend |
5 | RAMECC5_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc5_pend |
4 | RAMECC4_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc4_pend |
3 | RAMECC3_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc3_pend |
2 | RAMECC2_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc2_pend |
1 | RAMECC1_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc1_pend |
0 | RAMECC0_PEND | R/W1S | 0h | Interrupt Pending Status for ramecc0_pend |
1.6.11.11 CPSW_ECC_DED_ENABLE_SET_REG0 Register (Offset = 180h) [reset = X]
CPSW_ECC_DED_ENABLE_SET_REG0 is shown in Figure 12-883 and described in Table 12-1708.
Return to Summary Table.
Interrupt Enable Set Register 0
Table 12-1707 CPSW_ECC_DED_ENABLE_SET_REG0 InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 9180h |
Figure 12-883 CPSW_ECC_DED_ENABLE_SET_REG0 Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 12-1708 CPSW_ECC_DED_ENABLE_SET_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-20 | RESERVED | R/W | X | |
19 | RAMECC19_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc19_pend |
18 | RAMECC18_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc18_pend |
17 | RAMECC17_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc17_pend |
16 | RAMECC16_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc16_pend |
15 | RAMECC15_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc15_pend |
14 | RAMECC14_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc14_pend |
13 | RAMECC13_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc13_pend |
12 | RAMECC12_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc12_pend |
11 | RAMECC11_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc11_pend |
10 | RAMECC10_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc10_pend |
9 | RAMECC9_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc9_pend |
8 | RAMECC8_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc8_pend |
7 | RAMECC7_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc7_pend |
6 | RAMECC6_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc6_pend |
5 | RAMECC5_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc5_pend |
4 | RAMECC4_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc4_pend |
3 | RAMECC3_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc3_pend |
2 | RAMECC2_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc2_pend |
1 | RAMECC1_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc1_pend |
0 | RAMECC0_ENABLE_SET | R/W1S | 0h | Interrupt Enable Set Register for ramecc0_pend |
1.6.11.12 CPSW_ECC_DED_ENABLE_CLR_REG0 Register (Offset = 1C0h) [reset = X]
CPSW_ECC_DED_ENABLE_CLR_REG0 is shown in Figure 12-884 and described in Table 12-1710.
Return to Summary Table.
Interrupt Enable Clear Register 0
Table 12-1709 CPSW_ECC_DED_ENABLE_CLR_REG0 InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 91C0h |
Figure 12-884 CPSW_ECC_DED_ENABLE_CLR_REG0 Register LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 12-1710 CPSW_ECC_DED_ENABLE_CLR_REG0 Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-20 | RESERVED | R/W | X | |
19 | RAMECC19_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc19_pend |
18 | RAMECC18_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc18_pend |
17 | RAMECC17_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc17_pend |
16 | RAMECC16_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc16_pend |
15 | RAMECC15_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc15_pend |
14 | RAMECC14_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc14_pend |
13 | RAMECC13_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc13_pend |
12 | RAMECC12_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc12_pend |
11 | RAMECC11_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc11_pend |
10 | RAMECC10_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc10_pend |
9 | RAMECC9_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc9_pend |
8 | RAMECC8_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc8_pend |
7 | RAMECC7_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc7_pend |
6 | RAMECC6_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc6_pend |
5 | RAMECC5_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc5_pend |
4 | RAMECC4_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc4_pend |
3 | RAMECC3_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc3_pend |
2 | RAMECC2_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc2_pend |
1 | RAMECC1_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc1_pend |
0 | RAMECC0_ENABLE_CLR | R/W1C | 0h | Interrupt Enable Clear Register for ramecc0_pend |
1.6.11.13 CPSW_ECC_AGGR_ENABLE_SET Register (Offset = 200h) [reset = X]
CPSW_ECC_AGGR_ENABLE_SET is shown in Figure 12-885 and described in Table 12-1712.
Return to Summary Table.
AGGR interrupt enable set Register
Table 12-1711 CPSW_ECC_AGGR_ENABLE_SET InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 9200h |
Figure 12-885 CPSW_ECC_AGGR_ENABLE_SET Register LEGEND: R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Table 12-1712 CPSW_ECC_AGGR_ENABLE_SET Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1S | 0h | interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | interrupt enable set for parity errors |
1.6.11.14 CPSW_ECC_AGGR_ENABLE_CLR Register (Offset = 204h) [reset = X]
CPSW_ECC_AGGR_ENABLE_CLR is shown in Figure 12-886 and described in Table 12-1714.
Return to Summary Table.
AGGR interrupt enable clear Register
Table 12-1713 CPSW_ECC_AGGR_ENABLE_CLR InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 9204h |
Figure 12-886 CPSW_ECC_AGGR_ENABLE_CLR Register LEGEND: R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Table 12-1714 CPSW_ECC_AGGR_ENABLE_CLR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-2 | RESERVED | R/W | X | |
1 | TIMEOUT | R/W1C | 0h | interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | interrupt enable clear for parity errors |
1.6.11.15 CPSW_ECC_AGGR_STATUS_SET Register (Offset = 208h) [reset = X]
CPSW_ECC_AGGR_STATUS_SET is shown in Figure 12-887 and described in Table 12-1716.
Return to Summary Table.
AGGR interrupt status set Register
Table 12-1715 CPSW_ECC_AGGR_STATUS_SET InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 9208h |
Figure 12-887 CPSW_ECC_AGGR_STATUS_SET Register LEGEND: R/W = Read/Write; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Table 12-1716 CPSW_ECC_AGGR_STATUS_SET Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wincr | 0h | interrupt status set for svbus timeout errors |
1-0 | PARITY | R/Wincr | 0h | interrupt status set for parity errors |
1.6.11.16 CPSW_ECC_AGGR_STATUS_CLR Register (Offset = 20Ch) [reset = X]
CPSW_ECC_AGGR_STATUS_CLR is shown in Figure 12-888 and described in Table 12-1718.
Return to Summary Table.
AGGR interrupt status clear Register
Table 12-1717 CPSW_ECC_AGGR_STATUS_CLR InstancesInstance | Physical Address |
---|
MCU_CPSW0_ECC | 4070 920Ch |
Figure 12-888 CPSW_ECC_AGGR_STATUS_CLR Register LEGEND: R/W = Read/Write; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Table 12-1718 CPSW_ECC_AGGR_STATUS_CLR Register Field DescriptionsBit | Field | Type | Reset | Description |
---|
31-4 | RESERVED | R/W | X | |
3-2 | TIMEOUT | R/Wdecr | 0h | interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/Wdecr | 0h | interrupt status clear for parity errors |