SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
For more information about the MSMC interrupts, see Section 8.1.3.8.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.