SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 12-3530 lists the memory-mapped registers for the PCIE_VMAP. All register offset addresses not listed in Table 12-3530 should be considered as reserved locations and the register contents should not be modified.
RequesterID to virtID mapping registers
Instance | Base Address |
---|---|
PCIE1_CORE_VMAP_MMRS | 0291 4000h |
Offset | Acronym | Register Name | PCIE1_CORE_VMAP_MMRS Physical Address |
---|---|---|---|
0h + formula | PCIE_VMAP_CTRL_j | 0291 4000h + formula | |
4h + formula | PCIE_VMAP_REQID_j | 0291 4004h + formula | |
8h + formula | PCIE_VMAP_VIRTID_j | 0291 4008h + formula | |
200h | PCIE_VMAP_DEFMAP | 0291 4200h | |
400h | PCIE_VMAP_OB_VIRTID_MATCH | 0291 4400h | |
300h + formula | PCIE_VMAP_DESC_j | 0291 4300h + formula |
PCIE_VMAP_CTRL_j is shown in Figure 12-1791 and described in Table 12-3532.
Return to Summary Table.
Control register
Offset = 0h + (j * Ch); where j = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_VMAP_MMRS | 0291 4000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R/W-X | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EN | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | X | |
0 | EN | R/W | 0h | ID enable |
PCIE_VMAP_REQID_j is shown in Figure 12-1792 and described in Table 12-3534.
Return to Summary Table.
Requester ID mask and value register
Offset = 4h + (j * Ch); where j = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_VMAP_MMRS | 0291 4004h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MASK | RID | ||||||||||||||||||||||||||||||
R/W-0h | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | MASK | R/W | 0h | RequesterID mask |
15-0 | RID | R/W | 0h | RequesterID |
PCIE_VMAP_VIRTID_j is shown in Figure 12-1793 and described in Table 12-3536.
Return to Summary Table.
Virt ID and Atype register
Offset = 8h + (j * Ch); where j = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_VMAP_MMRS | 0291 4008h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ATYPE | ||||||||||||||
R/W-X | R/W-0h | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VID | ||||||||||||||
R/W-X | R/W-FFFh | ||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-18 | RESERVED | R/W | X | |
17-16 | ATYPE | R/W | 0h | Address type attribute. |
15-12 | RESERVED | R/W | X | |
11-0 | VID | R/W | FFFh | Match ID |
PCIE_VMAP_DEFMAP is shown in Figure 12-1794 and described in Table 12-3538.
Return to Summary Table.
virtID default value register
Instance | Physical Address |
---|---|
PCIE1_CORE_VMAP_MMRS | 0291 4200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | ATS_DIS | BDF_MODE | RESERVED | DEF_ATYPE | |||
R/W-X | R/W-0h | R/W-0h | R/W-X | R/W-0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DEF_VID | ||||||
R/W-X | R/W-FFFh | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEF_VID | |||||||
R/W-FFFh | |||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-21 | RESERVED | R/W | X | |
20 | ATS_DIS | R/W | 0h | ATS mode. |
19 | BDF_MODE | R/W | 0h | Bus default mode. |
18 | RESERVED | R/W | X | |
17-16 | DEF_ATYPE | R/W | 0h | Default address type attribute. |
15-12 | RESERVED | R/W | X | |
11-0 | DEF_VID | R/W | FFFh | Default match ID |
PCIE_VMAP_OB_VIRTID_MATCH is shown in Figure 12-1795 and described in Table 12-3540.
Return to the Summary Table.
Outbound virtid match register
Instance | Physical Address |
---|---|
PCIE1_CORE_VMAP_MMRS | 0291 4400h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | VAL | RESERVED | |||||||||||||||||||||||||||||
R-0h | R/W-0h | R-0h | |||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | X | Reserved |
11-5 | VAL | R/W | 0h | Outbound virtid [11:5] match value. When outbound VBUSM slave interface virtid [11:5] matches the value in this register and the ASEL value is non-zero, the PCIe controller address translation unit (ATU) is bypassed. The PCIe TLP descriptor values are taken from the ext_desc registers. |
4-0 | RESERVED | R | X | Reserved |
PCIE_VMAP_DESC_j is shown in Figure 12-1796 and described in Table 12-3542.
Return to the Summary Table.
Outbound ASEL non-zero descriptor register
Offset = 300h + (j * 4h); where j = 0h to 1Fh
Instance | Physical Address |
---|---|
PCIE1_CORE_VMAP_MMRS | 0291 4300h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
TRAFFIC_CLASS | RESERVED | ||||||
R/W-0h | R-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | BD_EN | ||||||
R-0h | R/W-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
BUS_NUM | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DEV_FUNC_NUM | |||||||
R/W-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-29 | TRAFFIC_CLASS | R/W | 0h | PCIe Traffic Class (TC) associated with the non-zero ASEL request. |
28-17 | RESERVED | R | X | Reserved |
16 | BD_EN | R/W | 0h | External bus and device number enable. This bit enables the client to supply the bus and device numbers to be used in the requester ID. If this bit is 0, the core uses the captured values of the bus and device numbers to form the Requester ID. If this bit is 1, the core uses the bus and device numbers supplied by the client on dev_func_num[7:4] and bus_num[15:8] to form the Requester ID. This bit must always be set while originating requests in the RP mode, and the corresponding Requester ID must be placed on dev_func_num[7:4] and bus_num[15:8]. |
15-8 | BUS_NUM | R/W | 0h | PCI Bus Number associated with the request. When descriptor bit[16] is set, this field must specify the bus number to be used for the Requester ID. Otherwise, this field is ignored by the core. |
7-0 | DEV_FUNC_NUM | R/W | 0h | PCI Function and Device Number associated with the request. In ARI mode, all 8 bits are used to indicate the requesting function number. In legacy mode, only bits[3:0] are used to specify function number and bits[7:4] are used to specify the device number to be used within the Requester ID, if the descriptor bit[16] is set. If the descriptor bit[16] is not set, then bits[7:4] are ignored. |