SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-669 lists the memory-mapped registers for the nbss_cfg_regs0_cfg_mmrs registers. All register offset addresses not listed in Table 10-669 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
NAVSS0_NBSS_CFG_REGS0_MMRS | 0380 0000h |
The nbss_regs Register Address Space. The address map for this region is as follows:
Offset | Acronym | Register Name | NAVSS0_NBSS_CFG_REGS0_MMRS Physical Address |
---|---|---|---|
0h | NBSS_PID | Revision Register | 0380 0000h |
NBSS_PID is shown in Figure 10-249 and described in Table 10-671.
Return to Summary Table.
The Revision Register contains the major and minor revisions for the module.
Instance | Physical Address |
---|---|
NAVSS0_NBSS_CFG_REGS0_MMRS | 0380 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SCHEME | BU | FUNC | |||||||||||||
R-1h | R-2h | R-640h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RTL | MAJOR | CUSTOM | MINOR | ||||||||||||
R-15h | R-2h | R-0h | R-0h | ||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-30 | SCHEME | R | 1h | PID register scheme |
29-28 | BU | R | 2h | BU |
27-16 | FUNC | R | 640h | Module ID |
15-11 | RTL | R | 15h | RTL revision. |
10-8 | MAJOR | R | 2h | Major revision |
7-6 | CUSTOM | R | 0h | Custom |
5-0 | MINOR | R | 0h | Minor revision |