SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
For each VIM interrupt core, there is an associated interrupt vector table (VIM RAM) that is used to store the address of ISRs. During register vectored interrupt and hardware vectored interrupt, VIM accesses the interrupt vector table using the vector value to fetch the address of the corresponding ISR. Note that both interrupt vector tables are identical in their memory organization.
The VIM RAM is basically comprised of a set of interrupt vector registers (R5FSS_VIM_VEC_INT_j). Hence, the interrupt vector table is organized in 512 words of 30 bits, with a base address corresponding to the physical address of the first register in the group.
The lower two bits of the 32-bit interrupt vector are always 0s.
Figure 6-72 shows the VIM RAM interrupt vector map.
The interrupt vector table has protection by ECC to indicate corruption due to soft errors. The ECC logic inside VIM supports SECDED. See Table 6-171 for the VIM RAM ID in the ECC aggregator map.