SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
In each access register mode (operational mode or configuration mode A/B), some register accesses are conditional on the programming of a submode (MSR_SPR, TCR_TLR, and XOFF). These registers are identified in Table 12-771, UART Load FIFO Triggers Defined by the Concatenated Value.
Table 12-748 through Table 12-750 summarize the register access submodes.
Mode | Condition |
---|---|
MSR_SPR | (UART_EFR[4] = 0x0 or UART_MCR[6] = 0x0) |
TCR_TLR | UART_EFR[4] = 0x1 and UART_MCR[6] = 0x1 |
Mode | Condition |
---|---|
TCR_TLR | UART_EFR[4] = 0x1 and UART_MCR[6] = 0x1 |
XOFF | (UART_EFR[4] = 0x0 or UART_MCR[6] = 0x0) |
Mode | Condition |
---|---|
MSR_SPR | UART_EFR[4] = 0x0 or UART_MCR[6] = 0x0 |
TCR_TLR | UART_EFR[4] = 0x1 and UART_MCR[6] = 0x1 |