SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-518 lists the memory-mapped registers for the NAVSS0_SEC_PROXY0_CFG_SCFG. All register offset addresses not listed in Table 10-518 should be considered as reserved locations and the register contents should not be modified.
Sec Proxy Secure Config Region
Instance | Base Address |
---|---|
NAVSS0_SEC_PROXY0_CFG_SCFG | 3280 0000h |
MCU_NAVSS0_SEC_PROXY0_CFG_SCFG | 2A40 0000h |
Offset | Acronym | Register Name | NAVSS0_SEC_PROXY0_CFG_SCFG Physical Address | MCU_NAVSS0_SEC_PROXY0_CFG_SCFG Physical Address |
---|---|---|---|---|
0h | SEC_PROXY_BUFFER_L | Buffer Register | 3280 0000h | 2A40 0000h |
4h | SEC_PROXY_BUFFER_H | Buffer Register | 3280 0004h | 2A40 0004h |
8h | SEC_PROXY_TARGET_L | Target Register | 3280 0008h | 2A40 0008h |
Ch | SEC_PROXY_TARGET_H | Target Register | 3280 000Ch | 2A40 000Ch |
10h | SEC_PROXY_ORDERID | Buffer OrderID Register | 3280 0010h | 2A40 0010h |
1000h + formula | SEC_PROXY_CTL_j | Control Register | 3280 1000h + formula | 2A40 1000h + formula |
1004h + formula | SEC_PROXY_EVT_MAP_j | Event Map Register | 3280 1004h + formula | 2A40 1004h + formula |
1008h + formula | SEC_PROXY_DST_j | Destination Register | 3280 1008h + formula | 2A40 1008h + formula |
SEC_PROXY_BUFFER_L is shown in Figure 10-191 and described in Table 10-520.
Return to Summary Table.
The Buffer Register defines the pointer for the external buffer.
Instance | Physical Address |
---|---|
NAVSS0_SEC_PROXY0_CFG_SCFG | 3280 0000h |
MCU_NAVSS0_SEC_PROXY0_CFG_SCFG | 2A40 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BASE_L | |||||||||||||||||||||||||||||||
R/W-0h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BASE_L | R/W | 0h | The base address for the external buffer, lower 32 bits. |
SEC_PROXY_BUFFER_H is shown in Figure 10-192 and described in Table 10-522.
Return to Summary Table.
The Buffer Register defines the pointer for the external buffer.
Instance | Physical Address |
---|---|
NAVSS0_SEC_PROXY0_CFG_SCFG | 3280 0004h |
MCU_NAVSS0_SEC_PROXY0_CFG_SCFG | 2A40 0004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BASE_H | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | BASE_H | R/W | 0h | The base address for the external buffer, upper 16 bits. |
SEC_PROXY_TARGET_L is shown in Figure 10-193 and described in Table 10-524.
Return to Summary Table.
The Target Register defines the pointer for the external target.
Instance | Physical Address |
---|---|
NAVSS0_SEC_PROXY0_CFG_SCFG | 3280 0008h |
MCU_NAVSS0_SEC_PROXY0_CFG_SCFG | 2A40 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
BASE_L | |||||||||||||||||||||||||||||||
R/W-38300000h | |||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | BASE_L | R/W | 38300000h | The base address for the external target, lower 32 bits. |
SEC_PROXY_TARGET_H is shown in Figure 10-194 and described in Table 10-526.
Return to Summary Table.
The Target Register defines the pointer for the external target.
Instance | Physical Address |
---|---|
NAVSS0_SEC_PROXY0_CFG_SCFG | 3280 000Ch |
MCU_NAVSS0_SEC_PROXY0_CFG_SCFG | 2A40 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BASE_H | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | BASE_H | R/W | 0h | The base address for the external target, upper 16 bits. |
SEC_PROXY_ORDERID is shown in Figure 10-195 and described in Table 10-528.
Return to Summary Table.
The Buffer OrderID Register contains the bus SEC_PROXY_ORDERID value for the buffer memory access.
Instance | Physical Address |
---|---|
NAVSS0_SEC_PROXY0_CFG_SCFG | 3280 0010h |
MCU_NAVSS0_SEC_PROXY0_CFG_SCFG | 2A40 0010h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R/W-X | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R/W-X | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R/W-X | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | REPLACE | ORDERID | |||||
R/W-X | R/W-0h | R/W-0h | |||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-5 | RESERVED | R/W | X | |
4 | REPLACE | R/W | 0h | Indicates to replace the bus OrderID value for the buffer access with the ORDERID register field. 0 = bypass and use the OrderID from the source transaction for the destination transaction. 1 = use the ORDERID register field value for the destination transaction. |
3-0 | ORDERID | R/W | 0h | Defines the bus OrderID value for the buffer access. |
SEC_PROXY_CTL_j is shown in Figure 10-196 and described in Table 10-530.
Return to Summary Table.
The Control Register defines controls for proxy thread a.
Offset = 1000h + (j * 1000h); where
j = 0h to 9Fh for NAVSS0_SEC_PROXY0_CFG_SCFG
j = 0h to 59h for MCU_NAVSS0_SEC_PROXY0_CFG_SCFG
Instance | Physical Address |
---|---|
NAVSS0_SEC_PROXY0_CFG_SCFG | 3280 1000h + formula |
MCU_NAVSS0_SEC_PROXY0_CFG_SCFG | 2A40 1000h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DIR | RESERVED | MAX_CNT | |||||||||||||
R/W-0h | R/W-X | R/W-0h | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
QUEUE | |||||||||||||||
R/W-0h | |||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31 | DIR | R/W | 0h | Direction for the proxy thread. 0 = outbound, write only. 1 = inbound, read only. |
30-24 | RESERVED | R/W | X | |
23-16 | MAX_CNT | R/W | 0h | Max message count allowed for an outbound proxy thread. Is not used otherwise. |
15-0 | QUEUE | R/W | 0h | Queue number in the target to use for the proxy thread. If the target base does not start at queue 0 then this is the relative queue number from that base queue. |
SEC_PROXY_EVT_MAP_j is shown in Figure 10-197 and described in Table 10-532.
Return to Summary Table.
The Event Map Register defines the event numbers for proxy thread a.
Offset = 1004h + (j * 1000h); where
j = 0h to 9Fh for NAVSS0_SEC_PROXY0_CFG_SCFG
j = 0h to 59h for MCU_NAVSS0_SEC_PROXY0_CFG_SCFG
Instance | Physical Address |
---|---|
NAVSS0_SEC_PROXY0_CFG_SCFG | 3280 1004h + formula |
MCU_NAVSS0_SEC_PROXY0_CFG_SCFG | 2A40 1004h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ERR_EVT | THR_EVT | ||||||||||||||||||||||||||||||
R/W-FFFFh | R/W-FFFFh | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | ERR_EVT | R/W | FFFFh | Event number for an error from the proxy thread. |
15-0 | THR_EVT | R/W | FFFFh | Event number for a threshold event from the proxy thread. |
SEC_PROXY_DST_j is shown in Figure 10-198 and described in Table 10-534.
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The Destination Register defines the destination proxy thread for outbound proxy thread a.
Offset = 1008h + (j * 1000h); where
j = 0h to 9Fh for NAVSS0_SEC_PROXY0_CFG_SCFG
j = 0h to 59h for MCU_NAVSS0_SEC_PROXY0_CFG_SCFG
Instance | Physical Address |
---|---|
NAVSS0_SEC_PROXY0_CFG_SCFG | 3280 1008h + formula |
MCU_NAVSS0_SEC_PROXY0_CFG_SCFG | 2A40 1008h + formula |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | THREAD | ||||||||||||||||||||||||||||||
R/W-X | R/W-0h | ||||||||||||||||||||||||||||||
LEGEND: R/W = Read/Write; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | RESERVED | R/W | X | |
15-0 | THREAD | R/W | 0h | The proxy thread that is the destination of messages from this outbound proxy thread, based on the queue numbers. This is ignored for inbound proxy threads. |