SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
Table 10-687 lists the memory-mapped registers for the PDMA5. All register offset addresses not listed in Table 10-687 should be considered as reserved locations and the register contents should not be modified.
Instance | Base Address |
---|---|
PDMA5_REGS | 027E 0000h |
Offset | Acronym | Register Name | PDMA5_REGS Physical Address |
---|---|---|---|
0h | PDMA5_ECC_REV | Aggregator revision register | 027E 0000h |
8h | PDMA5_ECC_VECTOR | ECC vector register | 027E 0008h |
Ch | PDMA5_ECC_STAT | Misc status register | 027E 000Ch |
3Ch | PDMA5_ECC_SEC_EOI_REG | SEC EOI register | 027E 003Ch |
40h | PDMA5_ECC_SEC_STATUS_REG0 | SEC interrupt status register 0 | 027E 0040h |
80h | PDMA5_ECC_SEC_ENABLE_SET_REG0 | SEC interrupt enable set register 0 | 027E 0080h |
C0h | PDMA5_ECC_SEC_ENABLE_CLR_REG0 | SEC interrupt enable clear register 0 | 027E 00C0h |
13Ch | PDMA5_ECC_DED_EOI_REG | DED EOI register | 027E 013Ch |
140h | PDMA5_ECC_DED_STATUS_REG0 | DED interrupt status register 0 | 027E 0140h |
180h | PDMA5_ECC_DED_ENABLE_SET_REG0 | DED interrupt enable set register 0 | 027E 0180h |
1C0h | PDMA5_ECC_DED_ENABLE_CLR_REG0 | DED interrupt enable clear register 0 | 027E 01C0h |
200h | PDMA5_ECC_AGGR_ENABLE_SET | AGGR interrupt enable set register | 027E 0200h |
204h | PDMA5_ECC_AGGR_ENABLE_CLR | AGGR interrupt enable clear register | 027E 0204h |
208h | PDMA5_ECC_AGGR_STATUS_SET | AGGR interrupt status set register | 027E 0208h |
20Ch | PDMA5_ECC_AGGR_STATUS_CLR | AGGR interrupt status clear register | 027E 020Ch |
PDMA5_ECC_REV is shown in Figure 10-255 and described in Table 10-689.
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IP revision register.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 0000h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REV | |||||||||||||||||||||||||||||||
R-66A0EA00h | |||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-0 | REV | R | 66A0EA00h | TI internal data. Identifies revision of peripheral. |
PDMA5_ECC_VECTOR is shown in Figure 10-256 and described in Table 10-691.
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ECC vector register.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 0008h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | RD_SVBUS_DONE | ||||||
R-0h | R/W1C-0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RD_SVBUS_ADDRESS | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RD_SVBUS | RESERVED | ECC_VECTOR | |||||
R/W1S-0h | R-0h | R/W-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ECC_VECTOR | |||||||
R/W-0h | |||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-25 | RESERVED | R | 0h | Reserved |
24 | RD_SVBUS_DONE | R/W1C | 0h | Status to indicate if read on serial VBUS is complete, write of any value will clear this bit. |
23-16 | RD_SVBUS_ADDRESS | R/W | 0h | Read address |
15 | RD_SVBUS | R/W1S | 0h | Write 1 to trigger a read on the serial VBUS |
14-11 | RESERVED | R | 0h | Reserved |
10-0 | ECC_VECTOR | R/W | 0h | Value written to select the corresponding ECC RAM for control or status |
PDMA5_ECC_STAT is shown in Figure 10-257 and described in Table 10-693.
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Misc status register.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 000Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | NUM_RAMS | ||||||||||||||||||||||||||||||
R-0h | R-4h | ||||||||||||||||||||||||||||||
LEGEND: R = Read Only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-11 | RESERVED | R | 0h | Reserved |
10-0 | NUM_RAMS | R | 4h | Indicates the number of RAMs serviced by the ECC aggregator |
PDMA5_ECC_SEC_EOI_REG is shown in Figure 10-258 and described in Table 10-695.
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SEC EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 003Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI value |
PDMA5_ECC_SEC_STATUS_REG0 is shown in Figure 10-259 and described in Table 10-697.
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SEC interrupt status register 0.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 0040h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCF1_RAMECC_PEND | RPCF0_RAMECC_PEND | TPCF1_RAMECC_PEND | TPCF0_RAMECC_PEND | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RPCF1_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for rpcf1_ramecc_pend |
2 | RPCF0_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for rpcf0_ramecc_pend |
1 | TPCF1_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for tpcf1_ramecc_pend |
0 | TPCF0_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for tpcf0_ramecc_pend |
PDMA5_ECC_SEC_ENABLE_SET_REG0 is shown in Figure 10-260 and described in Table 10-699.
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SEC interrupt enable set register 0.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 0080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCF1_RAMECC_ENABLE_SET | RPCF0_RAMECC_ENABLE_SET | TPCF1_RAMECC_ENABLE_SET | TPCF0_RAMECC_ENABLE_SET | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | Reserved |
3 | RPCF1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for rpcf1_ramecc_pend |
2 | RPCF0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for rpcf0_ramecc_pend |
1 | TPCF1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for tpcf1_ramecc_pend |
0 | TPCF0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for tpcf0_ramecc_pend |
PDMA5_ECC_SEC_ENABLE_CLR_REG0 is shown in Figure 10-261 and described in Table 10-701.
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SEC interrupt enable clear register 0.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 00C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCF1_RAMECC_ENABLE_CLR | RPCF0_RAMECC_ENABLE_CLR | TPCF1_RAMECC_ENABLE_CLR | TPCF0_RAMECC_ENABLE_CLR | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R/W | 0h | Reserved |
3 | RPCF1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for rpcf1_ramecc_pend |
2 | RPCF0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for rpcf0_ramecc_pend |
1 | TPCF1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for tpcf1_ramecc_pend |
0 | TPCF0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for tpcf0_ramecc_pend |
PDMA5_ECC_DED_EOI_REG is shown in Figure 10-262 and described in Table 10-703.
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DED EOI register. The EOI register is used to re-trigger the pulse interrupt signal to ensure that any nested interrupt events are serviced. The software interrupt handler must write to the EOI register at the end of the current interrupt processing routine, so that new events can re-trigger the pulse interrupt signal again. For level interrupt signals the EOI register is not functional and must not be used.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 013Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | EOI_WR | ||||||
R-0h | R/W1S-0h | ||||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-1 | RESERVED | R/W | 0h | Reserved |
0 | EOI_WR | R/W1S | 0h | EOI value |
PDMA5_ECC_DED_STATUS_REG0 is shown in Figure 10-263 and described in Table 10-705.
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DED interrupt status register 0.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 0140h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCF1_RAMECC_PEND | RPCF0_RAMECC_PEND | TPCF1_RAMECC_PEND | TPCF0_RAMECC_PEND | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RPCF1_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for rpcf1_ramecc_pend |
2 | RPCF0_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for rpcf0_ramecc_pend |
1 | TPCF1_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for tpcf1_ramecc_pend |
0 | TPCF0_RAMECC_PEND | R/W1S | 0h | Interrupt pending status for tpcf0_ramecc_pend |
PDMA5_ECC_DED_ENABLE_SET_REG0 is shown in Figure 10-264 and described in Table 10-707.
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DED interrupt enable set register 0.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 0180h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCF1_RAMECC_ENABLE_SET | RPCF0_RAMECC_ENABLE_SET | TPCF1_RAMECC_ENABLE_SET | TPCF0_RAMECC_ENABLE_SET | |||
R-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | R/W1S-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RPCF1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for rpcf1_ramecc_pend |
2 | RPCF0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for rpcf0_ramecc_pend |
1 | TPCF1_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for tpcf1_ramecc_pend |
0 | TPCF0_RAMECC_ENABLE_SET | R/W1S | 0h | Interrupt enable set register for tpcf0_ramecc_pend |
PDMA5_ECC_DED_ENABLE_CLR_REG0 is shown in Figure 10-265 and described in Table 10-709.
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DED interrupt enable clear register 0.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 01C0h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RPCF1_RAMECC_ENABLE_CLR | RPCF0_RAMECC_ENABLE_CLR | TPCF1_RAMECC_ENABLE_CLR | TPCF0_RAMECC_ENABLE_CLR | |||
R-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | R/W1C-0h | |||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3 | RPCF1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for rpcf1_ramecc_pend |
2 | RPCF0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for rpcf0_ramecc_pend |
1 | TPCF1_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for tpcf1_ramecc_pend |
0 | TPCF0_RAMECC_ENABLE_CLR | R/W1C | 0h | Interrupt enable clear register for tpcf0_ramecc_pend |
PDMA5_ECC_AGGR_ENABLE_SET is shown in Figure 10-266 and described in Table 10-711.
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AGGR interrupt enable set register.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 0200h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1S-0h | R/W1S-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1S = Read/Write 1 to Set Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1S | 0h | Interrupt enable set for svbus timeout errors |
0 | PARITY | R/W1S | 0h | Interrupt enable set for parity errors |
PDMA5_ECC_AGGR_ENABLE_CLR is shown in Figure 10-267 and described in Table 10-713.
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AGGR interrupt enable clear register.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 0204h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/W1C-0h | R/W1C-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/W1C = Read/Write 1 to Clear Bit; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-2 | RESERVED | R | 0h | Reserved |
1 | TIMEOUT | R/W1C | 0h | Interrupt enable clear for svbus timeout errors |
0 | PARITY | R/W1C | 0h | Interrupt enable clear for parity errors |
PDMA5_ECC_AGGR_STATUS_SET is shown in Figure 10-268 and described in Table 10-715.
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AGGR interrupt status set register.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 0208h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wincr-0h | R/Wincr-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/Wincr = Read/Write to Increment Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wincr | 0h | Interrupt status set for svbus timeout errors |
1-0 | PARITY | R/Wincr | 0h | Interrupt status set for parity errors |
PDMA5_ECC_AGGR_STATUS_CLR is shown in Figure 10-269 and described in Table 10-717.
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AGGR interrupt status clear register.
Instance | Physical Address |
---|---|
PDMA5_REGS | 027E 020Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | TIMEOUT | PARITY | |||||
R-0h | R/Wdecr-0h | R/Wdecr-0h | |||||
LEGEND: R = Read Only; R/W = Read/Write; R/Wdecr = Read/Write to Decrement Field; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-4 | RESERVED | R | 0h | Reserved |
3-2 | TIMEOUT | R/Wdecr | 0h | Interrupt status clear for svbus timeout errors |
1-0 | PARITY | R/Wdecr | 0h | Interrupt status clear for parity errors |