SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
A single VTM module is integrated in the device WKUP domain. Figure 5-656 shows the integration of WKUP_VTM0.
Table 5-1332 shows the temperature sensors in this device.
Temperature Sensor | Monitored Subsystem |
VTM_TMPSENS0 | Sensor near MCU_R5FSS |
VTM_TMPSENS1 | Sensor near LPDDR4 and A72 region |
VTM_TMPSENS2 | Sensor near main R5FSS, PLL clustering |
VTM_TMPSENS[7-3] | Not used |
Table 5-1333 through Table 5-1335 summarize the integration of WKUP_VTM0 in device WKUP domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
WKUP_VTM0 | WKUP_PSC0 | PD0 | LPSC0 | WKUP_CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
WKUP_VTM0 | WKUP_VTM0_ICLK | MCU_SYSCLK0/6 | WKUP_PLLCTRL0 | WKUP_VTM interface clock |
WKUP_VTM0_FIX_REF_CLK | WKUP_HFOSC0_CLKOUT | WKUP_HFOSC0 | Reference clock, used for the sensors | |
WKUP_VTM0_FIX_REF2_CLK | CLK_12M_RC | WKUP_RC_OSC_12M | Reference clock, used for the sensors during LPM | |
VTM_TMPSENS0 | TEMPSENSOR0_CLK | WKUP_VTM0_TEMP_SENS_ROOT_CLK | WKUP_VTM0 | Temperature monitor modules clock (1 MHz to 2 MHz) |
VTM_TMPSENS1 | TEMPSENSOR1_CLK | WKUP_VTM0_TEMP_SENS_ROOT_CLK | WKUP_VTM0 | Temperature monitor modules clock (1 MHz to 2 MHz) |
VTM_TMPSENS2 | TEMPSENSOR2_CLK | WKUP_VTM0_TEMP_SENS_ROOT_CLK | WKUP_VTM0 | Temperature monitor modules clock (1 MHz to 2 MHz) |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
WKUP_VTM0 | WKUP_VTM0_RST | MOD_G_RST | LPSC0 | WKUP_VTM0 Reset |
WKUP_VTM0_POR_RST | MOD_POR_RST | LPSC0 | WKUP_VTM0 Power-On Reset |
Software must disable all sensors before switching the reference clock.
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
WKUP_VTM0 | WKUP_VTM0_THERM_LVL_GT_TH1_INTR | MCU_R5FSS0_CORE0_INTR_IN_156 | MCU_R5FSS0_CORE0 | Combined overtemperature interrupt(1) | Level |
MCU_R5FSS0_CORE1_INTR_IN_156 | MCU_R5FSS0_CORE1 | ||||
WKUP_DMSC0_INTR_IN_20 | WKUP_DMSC0 | ||||
GIC500_SPI_IN_936 | GIC500 SPI | ||||
WKUP_ESM0_LVL_IN_8 | WKUP_ESM0 | ||||
R5FSS0_CORE0_INTR_IN_366 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_366 | R5FSS0_CORE1 | ||||
WKUP_VTM0_THERM_LVL_LT_TH0_INTR | MCU_R5FSS0_CORE0_INTR_IN_157 | MCU_R5FSS0_CORE0 | Combined undertemperature interrupt(1) | Level | |
MCU_R5FSS0_CORE1_INTR_IN_157 | MCU_R5FSS0_CORE1 | ||||
WKUP_DMSC0_INTR_IN_21 | WKUP_DMSC0 | ||||
GIC500_SPI_IN_937 | GIC500 SPI | ||||
WKUP_ESM0_LVL_IN_9 | WKUP_ESM0 | ||||
R5FSS0_CORE0_INTR_IN_368 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_368 | R5FSS0_CORE1 | ||||
WKUP_VTM0_THERM_LVL_GT_TH2_INTR | MCU_R5FSS0_CORE0_INTR_IN_158 | MCU_R5FSS0_CORE0 | Combined maximum temperature interrupt(1) | Level | |
MCU_R5FSS0_CORE1_INTR_IN_158 | MCU_R5FSS0_CORE1 | ||||
WKUP_DMSC0_INTR_IN_22 | WKUP_DMSC0 | ||||
GIC500_SPI_IN_938 | GIC500 SPI | ||||
WKUP_ESM0_LVL_IN_10 | WKUP_ESM0 | ||||
R5FSS0_CORE0_INTR_IN_367 | R5FSS0_CORE0 | ||||
R5FSS0_CORE1_INTR_IN_367 | R5FSS0_CORE1 | ||||
WKUP_VTM_CORR | WKUP_ESM0_LVL_IN_11 | WKUP_ESM0 | WKUP_VTM0 correctable error | Level | |
WKUP_VTM_UNCORR | WKUP_ESM0_LVL_IN_12 | WKUP_ESM0 | WKUP_VTM0 uncorrectable error | Level |
For more information about logical processing of the internal interrupts of VTM, see Section 5.2.2.2.5.3.2, VTM Temperature Driven Alerts and Interrupts.
For more information on the interconnects, see Chapter 3, System Interconnect.
For more information on the power, reset and clock management, see the corresponding sections within Chapter 5, Device Configuration.
For more information on the device interrupt controllers, see Section 9.2, Interrupt Controllers.