SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
A single ELM module is integrated in the device MAIN domain - ELM0. Figure 12-2162 shows the ELM0 integration.
Table 12-4252 through Table 12-4254 summarize the integration of ELM0 in device MAIN domain.
Module Instance | Attributes | |||
Power Sleep Controller | Power Domain | Module Domain | Interconnect | |
ELM0 | PSC0 | PD0 | LPSC8 | CBASS0 |
Clocks | ||||
Module Instance | Module Clock Input | Source Clock Signal | Source | Description |
ELM0 | ELM0_FICLK | MAIN_SYSCLK0/4 | PLLCTRL0 | ELM0 functional and interface clock |
Resets | ||||
Module Instance | Module Reset Input | Source Reset Signal | Source | Description |
ELM0 | ELM0_RST | MOD_G_RST | LPSC8 | ELM0 hardware reset |
Interrupt Requests | |||||
Module Instance | Module Interrupt Signal | Destination Interrupt Input | Destination | Description | Type |
ELM0 | ELM0_ELM_POROCPSINTERRUPT_LVL_0 | GIC500_SPI_IN_41 | COMPUTE_CLUSTER0 | Error-location process complete interrupt | Level |
R5FSS0_CORE0_INTR_IN_279 | R5FSS0_CORE0 | Error-location process complete interrupt | Level | ||
R5FSS0_CORE1_INTR_IN_279 | R5FSS0_CORE1 | Error-location process complete interrupt | Level | ||
MAIN2MCU_LVL_INTRTR0_IN_7 | MAIN2MCU_LVL_INTRTR0 | Error-location process complete interrupt | Level |