SPRUIU1C July 2020 – February 2024 DRA821U , DRA821U-Q1
This register contains the lower address bits of the transaction error that was captured.
Bits | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | addr_l | r | 0x0 |
Lower Address bits – If the captured transaction was a Timeout Error, this field represents the lower address bits [31:0] of the original transaction. If the error was an Unexpected Response error, then this field is not applicable. If the address width is less than 32, then the bits above the address range will be read as 0. |